analog/mixed-signal

By Sowmyan Rajagopalan, Founder and CTO, Thalia Design Automation FD-SOI is receiving significant traction with analog designers, but analog IP reuse often equates to tough choices. Porting chips from bulk to FD-SOI or creating new chips on FD-SOI means making decisions on porting existing bulk IP or starting from scratch. To invest the time and resources in reusing an analog IP requires a judgement call on the potential returns from the market and the time it takes to get the IP to that market to generate revenue is key – if a competitor's project hits the market first, then the potential returns are greatly diminished. There is also a need to understand the differences in process technologies and the impact those differences have on the efficient reuse of analog IPs. All this means that the demands on resources and time are high. Decisions, decisions A typical decision fork faced by many companies is whether to design new IPs, or if they should instead build a portfolio of analog IPs. Given the opportunity cost, availability of resources, time and resources needed for each option means that doing both is a difficult option. Both have their advantages; designing new IPs allows companies to branch out and address new sectors or markets. New IPs often demand higher revenues and engages in-house designers as the work, by its nature, is more innovative and challenging. On the other hand, building a portfolio of analog IPs allows companies to expand in an existing market, bringing stabilisation and strengthening revenues from existing product sectors. But why should you have to choose when there’s a third option? Have your cake and eat it It is difficult for a company to drive both options internally – not least because there’s a paucity of good analog designers in the market, and the opportunity cost is simply too high. However, the good news is that firms like Thalia have the specialist expertise and toolsets required build a portfolio of analog IP, saving time and investment while in-house designers focus on new IP design. Looking back Over the last 18 months, there has been a rapid uptake of FD-SOI process technologies. With production at foundries such as GlobalFoundries and Samsung now in full swing, more and more analog designers are reaping the benefits of FD-SOI. At Thalia we’ve been at the forefront of some of these changes, having worked with multiple customers on projects that use FD-SOI technology. [bctt tweet="More more analog designers are reaping the benefits of #FDSOI. At Thalia we’ve been at the forefront of some of these changes, having worked with multiple customers on projects that use FD-SOI technology. - @Thalia_IP_Reuse CTO " username="soiconsortium"] Driving the shift to FD-SOI [caption id="attachment_34410" align="alignright" width="347"] (Courtesy: STMicroelectronics)[/caption] This figure contrasts the structures of traditional bulk planar and SOI type transistors. The main difference is the inclusion of a buried oxide layer that isolates the channel of the transistor from the bulk silicon of the substrate. This results in a very thin, controllable channel structure, with much lower leakage currents being ‘lost’ into the device substrate than traditional alternatives. This in turn improves two key figures of merit for the device. First, standby power consumption is dramatically reduced. Second, the threshold voltage is much more predictable and controllable – yields are improved, and power/performance tradeoffs via voltage scaling are more easily enabled. The penalty is that FD-SOI transistors are generally not so fast. But one other feature of the technology – particularly important for mixed signal and analog designs – allows smart designers to mitigate this effect. Biasing the body structure at a different voltage to the source enables the designer to trade speed for power: a reverse bias increases the threshold voltage of the device, making it slower, but reducing leakage current; conversely, forward biasing reduces the threshold voltage, increasing the speed of the device, at the cost of power. Design migration Thalia has worked on a number of projects that utilize SOI technologies. A recent RF front end for Bluetooth Low Energy (BLE), for example, used exactly the techniques I have outlined above. We migrated an entire subsystem design, composed of around 30 blocks (including ADCs, PLLs, mixers, amplifiers and power controllers), to a 28nm Samsung FD-SOI process. [caption id="attachment_34412" align="alignright" width="451"] Click on this slide to see a YouTube video of the full Thalia presentation given at the Design Reuse FDSOI Virtual Event in March 2020.[/caption] The circuit was verified for compliance with design specifications. Design changes were implemented to ‘nudge’ the design to meet the requirements. And we made full use of the body biasing techniques I have already outlined. We used reverse body biasing to keep leakage as low as possible in parts of the circuit in which speed was not a factor; and, where speed was a key requirement, implemented forward gate biasing to increase performance. We’re expecting increasing numbers of customers to start moving their analog and mixed signal designs to SOI technologies in the coming months and years. The process is not without its challenges: but with an intimate knowledge of circuit design and optimization, and of the subtleties of the processes themselves, there are substantial advantages to be reaped. Technology analyzer – identifying the root cause when circuits fail A large part of the effort involved with migrating an IP from one technology to another is involved with qualifying the IP in the target technology; if a block doesn’t meet the requirements of the target technology, it won’t function. Identifying the cause of this – the technology characteristics that cause it – and then addressing them is key to a successful outcome. Whenever a key specification is not being met in the target technology, we have to determine which process technology or circuit characteristic is causing this. By using our automated technology analyser, we can take a design-centric approach to analyse and compare base and target technologies to see where the process technologies are similar and where they differ the most. The technology analyser considers both first and second order effects including FT, gm/id, Vdsats among others. Using this technology, we can identify which characteristics differ between the origin and target technologies. With traditional methods, identifying differences in characteristics would be time consuming, but our technology analyzer gives a clear and rapid identification of the issues, allowing us to fix any mis-matched topologies and achieve a functioning result in the target technology. The reality? IP reuse is not a dream or a myth Our platform comprises three elements – Technology, Methodology and Design Expertise. Using this trifecta, we have been able to deliver IPs in different technologies, nodes and with improved characteristics. The AMALIA technology consists of four elements: a technology analyzer, schematic porting, design enabler and layout migration. Tech analyzer: Using a design-centric approach, the platform addresses key first and second order effects of process technologies and extracts and compares characteristics between base and target technologies to provide the user with clear inputs on how similar the technologies are. Automated schematic porting: Taking the inputs from the analyzer and generates a circuit in the target technology. This circuit can then be verified for response and characteristics. Design enabler: Once the circuit design for the target technology is correct, the design enabler and our team of experienced designers can nudge the circuit back into specification. Layout migration: The final stage is focussed on putting together the base layout framework which is then expanding on by our experienced layout designers. Who we are?We are Thalia Design Automation. I founded Thalia in 2011, with the aim of improving the efficiency and process cost of analog circuit design and to rollout an analog IP reuse platform. We’ve worked with vendors, numerous foundries and different nodes and have design centres in Germany and India with our headquarters in the UK. We have successfully rolled out an analog IP reuse platform that combines smart technology, a smart methodology and our smart and experienced resources to streamline the IP reuse process. In doing all this, Thalia regularly provides customers with a time saving of around 50% compared to a traditional circuit redesign. And as I stated at the beginning of this article, achieving a faster time to market is key to maximizing revenues from any IP.

Since the beginning of the year, there’s been a steady stream of excellent news around Samsung Foundry’s 28FDS, their highly successful 28nm FD-SOI offering. Let’s take a look at what’s been happening, as things do seem to be accelerating. By way of reminder, they announced the industry’s first eMRAM (embedded MagnetoResistive RAM) testchip tape-out milestone on 28FDS in September 2017 (you can read the press release here) - which was just a year after they had announced mass production of 28FDS process technology.At the end of 2018, Arm announced the industry’s first Embedded MRAM (eMRAM) compiler IP built on Samsung Foundry’s 28FDS process technology. Follow that with this announcement at the beginning of 2019: Soitec Expands Collaboration with Samsung Foundry on FD-SOI Wafer Supply. The two companies announced that Samsung had secured a high-volume supply of FD-SOI technology to meet industry's current and future demands especially in consumer, IoT and automotive applications. In March came two more big announcements. First: Samsung Electronics Starts Commercial Shipment of eMRAM Product Based on 28nm FD-SOI Process. As they noted in the PR, “Samsung’s 28FDS-based eMRAM solution offers unprecedented power and speed advantages with lower cost. Since eMRAM does not require an erase cycle before writing data, its writing speed is approximately a thousand times faster than eFlash. Also, eMRAM uses lower voltages than eFlash, and does not consume electric power when in power-off mode, resulting in great power efficiency.”Hard on the heals of that came the news that Arm and Samsung Announce IP Platform including eMRAM for 18nm FD-SOI. At the SOI Consortium’s Silicon Valley Symposium in April, Tim Dry (he’s Samsung’s Director of Foundry Marketing for Edge and End Point), gave a terrific presentation. Entitled Samsung’s FDS with MRAM: Enabling Today’s Innovative Low Power Endpoint Products, it details the company’s FDSOI roadmap for the IoT Endpoint Platform (and yes, you can download in its entirety). Then in May at the big Samsung Foundry Forum in Silicon Valley, Arm, in collaboration with Samsung Foundry, Cadence, and Sondrel, demonstrated the first 28nm FD-SOI eMRAM IoT test chip and development board. The Musca-S1 test chip demonstrates a new choice in SoC design for IoT solutions, said Arm. (Sondrel, btw, is Europe's largest independent IC design consultancy.)In parallel, Cadence announced: Cadence Custom/AMS Flow Certified for Samsung 28nm FD-SOI Process Technology. Especially aimed at digitally-assisted analog designs, what’s new here is that the Cadence custom and analog/mixed-signal IC design flow is now Samsung Foundry certified for 28FDS. Samsung’s 28FDS PDK techfile is Mixed-Signal OpenAccess ready, enabling customers to deploy OpenAccess-integrated, fully interoperable Virtuoso-Innovus implementation flows. For its part, at its Foundry Forum, Samsung unveiled extensions of the company’s FD-SOI (FDS) process and eMRAM together with an expanded set of state-of-the-art package solutions. They indicated that the development of the successor to the 28FDS process, 18FDS, and eMRAM with 1Gb capacity will be finished this year.And finally, companies like NXP are shipping exciting new products fabbed on Samsung’s 28FDS. Ron Martino, VP GM of NXP’s i.MX Application Processor Product Line covered key products in his presentation at the SOI Consortium’s Silicon Valley Symposium (see our coverage here). Among them: the i.MX7ULP for long battery life with 2D 3D graphics for wearables and portables in consumer and industrial applications; the i.MX 8 and 8X subsystems for automotive and industrial applications; and the i.MX RT series of “cross-over” processors. The i.MX RT ULP (real-time, ultra-low-power) series, which Martino says is the “new normal”, deals with a high number of sensor inputs. The i.MX RT 1100 MCUs, which have been qualified for automotive and industrial applications, are breaking the gigahertz performance barrier.In July, linuxgizmos.com reported that, “In June, NXP began volume shipments of its super power-efficient i.MX7 ULP, which it announced in 2017. The SoC is billed as the most power-efficient processor on the market that also includes a 3D GPU. […] the ULP version includes a 3D graphics capable Vivante GC7000.” (Vivante, btw, is a VeriSilicon company, which is an SOI Consortium member and a leading proponent of FD-SOI design and IP in China and worldwide.) This is leading to some really nice wins for NXP. For example, they’ve got Amazon's Alexa Voice Service (AVS) leveraging the i.MX RT crossover processor, enabling developers to quickly and easily add Alexa voice assistant capabilities to their products. The RT series has rapidly been expanded, with versions for voice-controlled devices and offline face and expression recognition capabilities for smart home, commercial and industrial devices.Also announced this summer: NXP and Microsoft Bring Microsoft Azure Sphere Security to the Intelligent Edge with a New Energy-Efficient Processor. That collaboration includes development of a new crossover applications processor in NXP’s i.MX 8 series integrating Microsoft’s Azure Sphere security architecture and Pluton Security Subsystem. Their customers “will be able to harness the high-performance and energy efficiency of NXP’s i.MX 8 applications processors combined with Microsoft’s unequaled security and assurance provided by Azure Sphere certified chips”. As Martino concluded in his presentation, “The future of embedded processing [is] enabled by FD-SOI.” And Samsung Foundry’s FD-SOI offerings are clearly a massive enabler of that future.

There were over 220 participants at the recent SOI Academy FD-SOI Training event organized in Shanghai. The event extended over two days, with the first day covering a basic introduction to the technology as well as the ecosystem worldwide and in China. The second day was hands-on professional training. Attendees got a comprehensive understanding of how to leverage the benefits and flexibility of FD-SOI design techniques for low-power chips including logic, mixed-signal/RF and analog blocks. They had a great line-up of experts from whom to learn – check out the agenda here. There was also a follow-up press release (in Chinese) from SITRI here. There will be more of these SOI Academy events in cities across China in the year to come – we'll keep you posted (and of course, keep checking back for news on the Consortium's Events page). [caption id="attachment_12981" align="aligncenter" width="1000"] SOI Academy '18 keynotes by: Dr. Mark Ding, CEO, SITRI; Dr. Carlos Mazure, EVP Soitec and Chairman/Executive Director SOI Consortium. Dr. Julien Arcamone, EVP Leti. (Images courtesy: SITRI). Lower right: the hands-on FD-SOI training.[/caption] The two-day seminar and hands-on FD-SOI design training was (superbly!) co-organized by SITRI and Leti, with the support of the SOI Industry Consortium at the Jiading SIMIT campus outside of Shanghai. Just to put this in perspective, SIMIT and SITRI are absolutely key players in China's chip ecosystem. SIMIT is the Shanghai Institute of Microsystem and Information Technology, one of the most venerable institutes in the Chinese Academy of Science (CAS) and one of the world's earliest pioneers in SOI. SITRI is the Shanghai Industrial μTechnology Research Institute, an international innovation center focused on globally accelerating innovation and commercialization of More-than-Moore for IoT. Both institutions are under the aegis of Dr. Xi Wang, Chairman of SITRI, Director General of SIMIT, Academician of CAS, and champion of all things SOI in China. At this Shanghai event, the participants came from industry (including big companies, SMEs and startups) and technical institutions. In fact as well as attendees from Shanghai people voyaged from other cities such as Shenzhen and Chengdu. The designers participating to the FD-SOI training day were all experienced in design and highly motivated in learning FD-SOI design, notes Carlos Mazure, Chairman Executive Director of the SOI Industry Consortium, and Executive VP of Soitec. “This made it possible to dive into the specificities of FD-SOI,” he said, adding that, “The focus on RF was very timely.” Day 1: Intro to FD-SOI The first afternoon opening keynotes were made by SITRI CEO Dr. Mark Ding and Leti EVP Dr. Julien Arcamone. These were followed by overview talks by execs from Soitec, Verisilicon and GlobalFoundries. After a lively networking break, three talks delved into FD-SOI technology. The first was by Professor Sorin Cristoloveanu, Laureate of the IEEE Andrew Grove Award and Director at the CNRS (the French National Center for Scientific Research – the largest governmental research organization in France and the largest fundamental science agency in Europe). He covered device physics and characterization techniques. This was followed by talks on the technology by Soitec Fellow Bich-Yen Nguygen, and by Dr. Christophe Tretz, IBM Sr. Engineer on product design methodology. The day ended with a dinner, where Professor Cristoloveanu says enthusiastic technical discussions continued unabated (and continued even further in follow-up emails), lots of business cards were exchanged, and opportunities for further education were explored. Day 2: Hands-on Training The second day, designers got hands-on training from Leti experts using FD-SOI PDKs, first in the morning on digital, then in the afternoon on RF. Everyone loved the lively discussion and in-depth exchanges between the experts and the designers. They agreed that FD-SOI has important applications and differentiated competitive advantages for IoT, 5G, automotive, AI and other fields. At the end of the training, Leti and SITRI jointly issued SOI Academy certificates of completion to the designers. Feedback from participants was very good. Some asked for further education and for hands-on testimonials from companies that are already designing and manufacturing products on FD-SOI. “The participants were focused, motivated, involved, with good knowledge, which helped make the three hours of Digital training effective,” said Dr. Alexandre Valentian, Leti Sr. Expert, Digital Design. “The IT team was very helpful in setting up the training, the students accounts and the hardware infrastructure.” “The training on Basics of FD-SOI RF circuit was a great success thanks to the efficiency of our Chinese partners and also thanks to the enthusiasm and the good level of our trainees. As senior Expert of CEA Leti I was really impressed by the professionalism of the organization team. For all these reasons, I’m very glad to have had the opportunity to contribute to the 2018 SOI Academy,” said Dr. Baudouin Martineau, Leti Sr. Expert, RFIC Design Technologies. “The professionalism, efficiency and enthusiasm of our Chinese partners and the level and technical relevance of all trainees made the training on Basics of FD-SOI RF circuit a great success and fruitful experience,” added Frédéric Hameau, Sr. RF Research Engineer, Leti Project Leader, Architecture, IC Design Embedded Software Division, RF Architectures and ICs Laboratory. “It was a pleasure to get the opportunity to be part of this first edition of SOI academy 2018.” The organizers would like to thank the sponsors, including: the SOI Consortium and its members Soitec, VeriSilicon, GlobalFoundries, Simgui and Cadence, as well as Mentor, ProPlus and other companies and institutions in China and worldwide. Dr. Mazure notes that special recognition must go to Dr. Julien Arcamone, EVP, Leti-CEA and to Qing Wang-Bousquet, SITRI representative, for the perfect and smooth organization, and to the Leti instructors, who are international experts and highly committed. “As one of the main initiators and organizers of the 2018 SOI Academy, I wanted to personally thank all of you for your respective contribution to this first edition of the SOI Academy,” concludes Dr. Arcamone. “Undoubtedly, it was a great success, very well organized and fluid and we can be proud of that.”

Following the immense success of last year's FD-SOI training day in Silicon Valley, the SOI Consortium has another one planned for the end of April this year. If you want to start learning how to leverage FD-SOI in your chip designs, this is a great place to start. Click here for information on how to sign up. ST Fellow Dr. Andreia Cathelin has put together another great line-up. World renowned professors and experts from industry will deliver a series of four training sections of 1.5 hours each, focused on energy efficient and low-power, low-voltage design techniques for analog, RF, high-speed, mmW and mixed-signal design. You'll learn about design techniques that take full advantage of the unique features of FD-SOI, including body biasing capabilities that further enhance the excellent analog/RF performances of these devices. Each section of this training day will take you through concrete design examples that illustrate new implementation techniques enabled by FD-SOI technologies at the 28nm and 22nm nodes – and beyond. The design examples will cover basic building blocks through SoC implementations. A global Q A session will close the day. Here's a little more info on how the day will unfold. Click on the slides to see them in full screen. Morning sessionsFDSOI-specific design techniques for analog, RF and mmW applications - Andreia Cathelin, Fellow, STMicroelectronics [caption id="attachment_11714" align="alignleft" width="300"] Quick preview from Andreia Cathelin's FD-SOI training session (Courtesy: STMicroelectronics, SOI Consortium)[/caption] Andreia Cathelin is ST's key design scientist for all advanced CMOS technologies, and is arguably the world's leading expert on leveraging FD-SOI in high-performance, low-power RF/AMS SoCs. Her course will first present a very short overview of the major analog and RF technology features of 28nm FDSOI technology. Then the focus moves to the benefits of FD-SOI technology for analog/RF and millimeter-wave circuits. She'll give design examples such as analog low-pass filters, inverter-based analog amplifiers and 30GHz and 60GHz Power Amplifiers, as well as mmW oscillators. There will be particular focus on the advantages of body biasing and special design techniques offering state-of-the-art performance. Circuit Design Techniques in 22nm FD-SOI for 5G 28GHz Applications - Frank Zhang, Principal Member of Technical Staff, GlobalFoundries [caption id="attachment_11716" align="alignright" width="300"] Quick preview from Frank Zhang's FD-SOI training session (Courtesy: GlobalFoundries, SOI Consortium)[/caption] Frank Zhang has designed chips using GF's 22nm FD-SOI (22FDX) process for WLAN, 5G cellular and automotive radar applications. His course will focus on how to take advantages of FD-SOI’s high-frequency performance at relatively low-current density to design high performance RF/mmWave circuits. Examples circuits include a 28GHz LNA, a 28GHz PA and an RF switch for 5G applications. The FD-SOI advantages such as low capacitance, high breakdown voltage and high-output impedance will be exploited in these design examples. This course will also discuss how to extend these techniques to applications at higher frequencies and/or higher current densities that are subject to extreme temperatures and EM requirements. Afternoon sessionsEnergy-Efficient Design in FDSOI - Bora Nikolic, Professor, UC Berkeley [caption id="attachment_11715" align="alignleft" width="300"] Quick preview from Bora Nikolić's FD-SOI training session (Courtesy: UC Berkeley, SOI Consortium)[/caption] Borivoje (“Bora”) Nikolić is known as one of the world’s top experts in body-biasing for digital logic (he and his team have designed more than ten chips in ST’s 28nm FD-SOI.) If you missed it, his team's RISC-V chip was cited as one of Dr. Cathelin's “Outstanding 28nm FD-SOI Chips Taped Out Through CMP” – read more about that here. His talk at the training day will present options for energy-efficient mixed-signal and digital design in FD-SOI technologies. He'll explain how to generate body bias and use it to improve efficiency, with examples in RF and baseband building blocks, temperature sensors, data converters and voltage regulators. The techniques will be presented in the context of UC Berkeley's latest RISC-V-based SoC, designed to operate in a very wide voltage range using 28nm FD-SOI. mm-Wave and Fiber-Optics Design in FD-SOI CMOS Technologies - Sorin Voinigescu, Professor, University of Toronto [caption id="attachment_11713" align="alignright" width="300"] Quick preview from Sorin Voinigescu's FD-SOI training session (Courtesy: U. Toronto, SOI Consortium)[/caption] Sorin Voinigescu is a world renowned expert on millimeter-wave and 100+Gb/s ICs and atomic-scale semiconductor device technologies. His lecture will cover the main features of FD-SOI CMOS technology and how to efficiently use its unique features and suitable circuit topologies for mm-wave and broadband SoCs. He'll begin with an overview of the impact of the back-gate bias and temperature on the measured I-V, transconductance, fT, and fMAX characteristics. Then he'll compare the maximum available gain, MAG, of FDSOI MOSFETs with those of planar bulk CMOS and SiGe BiCMOS transistors through measurements up to 325 GHz. Next, he'll provide biasing, sizing and step-by-step design examples for VCO, doubler, switches, PA, large swing optical modulator drivers and quasi-CML circuit topologies and layouts that make efficient use of the back-gate bias to overcome the limitations associated with the low breakdown voltage of 20nm and 12nm FD-SOI CMOS technologies. Sign Up Now!With over 100 attendees filling every chair in the auditorium, last year's training day was sold out. Although it was in Silicon Valley, people actually flew in from all over the world to be there. During the Q A at the end, most everyone prefaced their questions by saying, “Thank you. I really learned a lot today.” 2018 will be no different – except that it's sure to sell out even faster. Please note, though, that this is not a free event, so only the attendees will get copies of the slide decks. Here's key info you need to sign up. See you there!What: SOI Consortium's FD-SOI Training DayWhen: 27 April 2018, 7:30am – 5pm.Where: Crowne Plaza San Jose, Milpitas CA (parking is free)Registration fee: US $485.00 (includes training book, breakfast, box lunch and refreshments during breaks)How to sign up: Click here to go directly to the registration site.