Incize

With the CAGR for switches in cell-phone RF front-end modules running at 9% for the next five years, new players want to get in on the action, and established players want to up the ante. The specialists at Incize help wafer suppliers, foundries and fabless companies maximize switch performance starting at the substrate level. CEO Mostafa Emam explains how.SOI News (SN): Can you tell us about the role Incize plays in the RF-SOI ecosystem? [caption id="attachment_32519" align="alignright" width="140"] Incize CEO Mostafa Emam. (Photo courtesy: Incize)[/caption] Mostafa Emam (ME): Our clients are wafer suppliers, foundries and fabless companies. The services we offer are testing and modeling of substrates, with the vision of what will happen in the value chain. Based on what the customer will do with the substrates, we do testing and modeling to improve the technology and tune their processes. Although the big players have teams devoted to this, we can add a layer of characterization that they have no expertise in. Some of our customers are foundries that have been using bulk silicon, but now see opportunities in RF-SOI. But they’re starting from scratch and we help them to adopt the technology. We help them understand the physics behind the technology so they can migrate from bulk to SOI. We help them develop test structures and evaluate their technology. Then we create models for both fully-depleted and partially-depleted SOI with PD-SOI 130 nm or 60 nm technology dominating the RF front-end module market. We believe RF is an art and you need to see the whole picture. SN: Can you tell us a bit about the history of Incize? ME: The RF-SOI story started in the 1990s. Then came trap-rich RF-SOI wafers from Jean-Pierre Raskin’s team at UC Louvain, industrialized by Soitec. Our lab at UC Louvain became known for our expertise in RF-SOI, and in 2011 we created Incize as a spin-off. [Editor's note: for more background, see this SOI Consortium article about the birth of trap-rich substrates and the company’s founding.] At first our characterization services were very diverse, but by 2014 we focused mostly on RF-SOI because of the big demand. In 2015 we started doing radiation hardness tests for space applications and a new business unit was created. In 2016 we started our modeling and PDK activity, followed the next year by work on GaN on Si. In 2018, we started offering full support to RF-SOI newcomers, who were starting from scratch, usually smaller players in the RF market. It takes about two years to fully train the engineers, support the technology enhancements, design test vehicles, measure them and finally do the modeling and PDK. So some of these players are now fully established in the RF-SOI market and have contracts in place with big customers. SN: In your presentations, you often say there is room for all. What do you mean by that? ME: There is a big market for RF-SOI in the coming years. It can offer the low-power, the low-cost and the high performance. RF-SOI is the only mature technology that combines all of this today. It successfully competes with traditional III-V technology. More foundries want to employ RF-SOI. We show to them that it’s not black magic – you just need to know how it works. [bctt tweet="There is a big market for RF-SOI in the coming years. More foundries want to employ #RFSOI. We show them that it’s not black magic – you just need to know how it works. - Incize CEO Mostafa Emam #5G #semiconductors" username="@soiconsortium"] On our side, we have the knowledge and the infrastructure. Our added value is that we can do advanced tests the customers can’t do. So the foundry says there’s opportunities in switches, we’ll do this and develop it all with optimization for specific Ron and Coff [the figure of merit for RF switches]. The foundry develops an RF switch and aiming at certain performance (RonCoff). We help our customers during this development phase. Once the performance target is reached we start developing a model and a PDK. There is enough demand for RF-SOI, as even entry-level cell phones have SOI chips. Some opt for a fast and low-cost solution. Many target “good enough”, although some target to compete against the big players – it’s a question of their business strategy. And this is where our added value comes in. SN: Can you provide some more insight into how you see the RF market? ME: The Front End Module (FEM) is a fast growing market, with increasing demand in terms of volume and performance. This includes antenna switches, LNAs, tuners, filters, etc. Historically, III-V materials have been used for their high performance and high power handling. However, RF-SOI has become the material of choice, and the biggest driver is integration of the RF switch and LNAs in one chip. It’s not easy to integrate the power amplifiers (PAs) on the same chip (still being on III-V substrates). But as it decreases footprint and cost, there are those who’ll do it. There is no viable competition for SOI – nothing will replace it in the short term. There are other technologies, but they are long term. It’s a stable market with high demand. SN: For those of us who are not RF experts, can you help us understand the technology? ME: The switch is sort of the traffic light of the FEM, receiving and transmitting. The simplest RF switch can be composed of only four transistors. Transistors leak power so you need to determine your Ron Coff performance. [Editor's note: Resistance on vs. Capacitance off, the RF switch figure of merit, is measured in femtoseconds and should be as low as possible. Psemi has a good video explaining it.] When the Coff capacitance is small, the switch is really off. When the On resistance Ron is small, it means low losses, and the switch is turned On. Ron and Coff is a compromise. And as there are many frequency bands and antennas, the FEM becomes very complex. Another issue is power handling, since the switch is the first stage behind the antenna. And finally, there is the question of switch linearity. Trap rich SOI wafers suppress harmonics so you have less distortion originating in the substrate. You have to model this – the designer needs to know. In addition to single tone harmonics you also get intermodulation, where, two or more high power signals at two different frequencies create distortion at other frequencies. The danger is that these parasitic signals can be so close that the filter can’t reject them and the useful signals get distorted. This was a killer for the switch created on the bulk substrate. Trap-rich RF-SOI fixed this. So now 100% of switches are on trap-rich SOI substrates. While it’s still a niche market, there is demand from customers for increasing the number of bands – that’s driving this market. SN: And what happens as we move to 5G? ME: There’s more and more pressure on the specs. It’s an art when anything changes. Moving from 3G to 4G required complete upgrade of the [foundry’s] models. With 4G, the specs are severe and the FEM must be built on trap-rich substrates. But 5G is not well defined, so the RF industry is taking their best shot. What is clear: the performance requirements get more challenging. Once the technology is understood, it can be implemented. But the foundries and the fabless need our help to do it fast and do it well. We create more value working together. SN: How do you see things evolving? ME: The number of foundries today doing switches on RF-SOI is increasing, and this will continue for the next few years. We saw this opportunity and invested in it. Our company is just ten people, and we are self-funded. We are swimming in business, but we have fun. And we’re getting recognition. Any company with CMOS in place could adopt RF-SOI. But it’s a different mindset. We help with the transition. ~ ~ ~Click here to read more feature articles in SOI News.

The SOI Consortium’s Japan Symposium this past fall covered a wide array of topics over two days. The first day was devoted to IP and products for RF and ultra-low-power (ULP) on SOI. The second day covered high voltage and photonics. It will take several posts to summarize all the presentations. In this post, we’ll cover presentations related to 5G. In the next posts we’ll cover IoT/ultra-low-power/automotive and photonics. (BTW, if your company is a member of the SOI Consortium, you can now access most of these presentations on our website.) The Japan SOI Symposium was organized for the 4th time at the Yokohama Landmark Tower (from which there was a fabulous view of Mount Fuji). It was a great success, with both days well attended. The event followed the day after (and in the same location as) Silvaco’s SURGE user event, so there were plenty of opportunities for synergy there. (Samsung Foundry talked about their partnership with Silvaco, for example, and their work together on RF and eMRAM on 28nm FD-SOI.) STMicroelectronics [caption id="attachment_27068" align="alignnone" width="589"] From “5G Deployment Driving RF and SOI Technology Opportunity” (Courtesy: ST SOI Consortium)[/caption] As noted in the ST presentation, 5G standards are getting a big push in the Asia-Pacific region, and by China in particular, which is leaping ahead especially in sub-6GHz. It’s a complex standard, noted John Carey, the company’s director of Digital RF for the A-P region, and it’s disruptive, demanding new silicon architectures and technologies. Next year’s premium phones, he said, will include over $30 in RF components, 40mm2 of which will be based on SOI. ST has been working on RF-SOI for over two decades, and offers a range of technologies and foundry services supported by three high-volume fabs. The key benefits with RF-SOI, he explained, stem from RF FEM integration of switches, LNAs and PAs. RF-SOI technologies are here now and are successful in the markets: ST has a long-term technology roadmap and is making continued strategic investments, he concluded. Toshiba [caption id="attachment_27069" align="alignnone" width="410"] From “RF-SOI Switch LNA for Mobile Applications” (Courtesy: Toshiba SOI Consortium)[/caption] Another long-time RF-SOI user is Toshiba, although this marked their first participation in a recent Consortium event. As Group Manager Kazuyuki Uchida talked about RF techology trends, there was lots of note- and picture-taking in the audience. He pointed out that the character and size of the switch LNA modules are particularly important in the move to 5G. They’ve been leveraging their TaRFSOI(tm) process, which he said achieves the industry's lowest insertion loss, for about a decade now. The latest version, TaRF11 will be launching in Q1 of 2020. TaRF10 integrated the LNA with the switch and control circuitry in a single chip. TaRF11 will feature performance improved by about 25%. Incize [caption id="attachment_27065" align="alignnone" width="405"] From “RF Characterization” (Courtesy: Incize and SOI Consortium)[/caption] During the Incize presentation, the company’s CEO Mostafa Emam affirmed that RF-SOI is a very good business opportunity. Incize works with the complete supply chain. For foundries and wafer suppliers, they measure harmonics and output with very high precision, which is especially critical for switches. For the wafer suppliers, it’s predictive. For the foundries, it’s measuring noise for models and PDKs. While RF may be an art, second tier foundries using Incize services are now able to compete with the first tier players, he noted. He sees trap-rich RF-SOI wafers as being especially important for 5G. GlobalFoundries [caption id="attachment_27064" align="alignnone" width="599"] From “RF Reliability for SOI CMOS Si-based Power Amplifier for 5G applications” (Courtesy: GlobalFoundries SOI Consortium)[/caption] The focus of the GlobalFoundries talk was reliability in RF processes. In 5G, you need technologies that are viable for both mmWave and sub-6GHz across handsets, wifi and automotive, noted Purushothaman Srinivasan (who goes by SP and is a senior member of the company’s technical staff). In SOI, you can stack FETs (which you can’t do in bulk) for PAs, which is a big advantage in mmWave. However, delivering scalable, linear, efficient and reliable RF power technology is more challenging than digital, and requires a holistic, collaborative approach that includes the foundry, the customers and the test equipment suppliers. GF has used its RelXpert simulation tool on aging simulations and lifetime predictions for both their 22FDX and 45RFSOI processes. They have observed good RF model-to-hardware correlation, and have built Safe Operating Maps that provide guidance to RF designs. This first-in-industry RF reliability evaluation provides “highly differentiated” solutions for GF. Silvaco [caption id="attachment_27066" align="alignnone" width="606"] From “RFSOI TCAD Solution” (Courtesy: Silvaco and SOI Consortium)[/caption] Silvaco is a leading EDA provider of software tools used for process and device development and for analog/mixed-signal, power IC and memory design. Their presentation began with a review of recent updates to their TCAD simulation framework, including the TCAD design flow, Victory ProcessTM simulation for speeding up 2D/3D process simulations, and Victory DeviceTM simulation. Under Silvaco’s DTCO – Design Technology Co-Optimization – semiconductor physics are connected to circuit design, recognizing that each technology has specific requirements that need to be taken into account at every stage of the flow. Applications Engineer Sun Tao then continued by showing useful TCAD simulations and analysis of SOI for RF applications. In trap-rich substrate simulations, for example, the Silvaco tools can predict the harmonic balance from the active device, device biasing and substrate, all of which can be co-optimized using Victory Process and Device. SITRI [caption id="attachment_27067" align="alignnone" width="305"] From “NB IoT FEM based on SOI” (Courtesy: SITRI SOI Consortium)[/caption] Shanghai Industrial μTechnology Research Institute – aka SITRI – is an international innovation center, focused on globally accelerating the innovation and commercialization of “More than Moore” technologies to power IoT. SITRI Director Wenwei Yang’s talk focused on their narrowband front-end module for IoT (NB IoT FEM). NB-IoT is especially meant to handle small amounts of data from remote places over long periods. There are a lot of players in this market, so taking a “good-enough” approach to performance wherein cost is primordial is key. SITRI’s low-cost NB-IoT FEM integrates everything on a single chip, including the power amplifier (PA) and integrated passive devices (IPD), so packaging costs are low. Putting it on SOI (either trap-rich or high-resistivity) gives them better isolation and simplifies integration. ~ ~ ~ Our next post will continue our coverage of the Japan Symposium. Note: 2019 marks a decade of SOI Consortium events – yes, our first one was in 2009! Because a lot of the presentations in the past were so forward-looking, many of them are still of great interest today. Currently the presentations from 2015 through to the beginning of 2019 are available freely to everyone – and are well worth perusing.

The SOI Consortium’s China 2019 event ran for two days, and it’s taken four (!) posts to cover all the presentations. In this final post we cover the afternoon RF-SOI sessions, which were dedicated to the China RF-SOI ecosystem and the RF value chain. In case you missed them, our previous posts recapped: 1. major keynotes from both the FD-SOI and RF-SOI days; 2. the FD-SOI presentations; 3. the morning sessions of the RF-SOI day; and 4. (this post) the RF-SOI day afternoon sessions. As we noted in Part 1 of our RF-SOI coverage, there were over 500 attendees for the RF-SOI day. And impressively, the room was still packed right through to the very end of the afternoon. Read on! SESSION 2: CHINA RF-SOI ECOSYSTEMSuzhou HunterSun Electronics: Super Opportunity for Integrated RFFE (“Jacky” Yujun Ding, COO)This talk had two parts. First, how is 5G changing the world, and second, what are the RFFE opportunities? He cited IHS data indicating that 5G will create tens of millions of jobs. New products include NB IoT, cellular V2X, as well as traditional PC/tablets and smart phones. But you still need to cover 2/3/4G with 5G. Major growth will happen in 2025-27. In terms of opportunities for RFFE, you've currently got 550mm2 going for $8; in 5G, you'll need 600mm2, but it will cost $16. You need RFSOI for filters and antenna switches, which are in high demand. Parts of the supply chain have no China players. Revenue for BAW is higher than SAW, but there's more SAW. He sees the industry moving heavily into integrated FEM (versus chip-on-board). He finished by itemizing different parts of the RFFE, indicating where the opportunities are (citing some data from Yole), with a special emphasis on integrated products for Chinese companies, with continued investor confidence. SmarterMicro: RF-SOI: Key Technology of Smart Connection (Yangyang Pen, Director) RF-SOI is an enabler of smart connections. However he sees GaAs as better for power, so SmarterMicro has a solution combining RF-SOI and GaAs. They've developed the world's first mMTC RFFE for high-performance upgrades on a single die and software reconfigurable. He notes that for IoT, lifetimes will be longer than 10 years, and that terminals are becoming more powerful. CanaanTek: Critical SOI CMOS Blocks in the 5G NR Sub-6GHz RF Front-End Architectures (Wayne Ni, CTO Board Chairman) CanaanTek is a fabless company working in consumer markets, with switches, tuners and LNAs in SOI-CMOS. He wants to capture 10% of the market with a focus on sub-6. The antenna/tuner is a must, and they've developed solutions for switches here. The figure of merit is RonCoff. He showed a product roadmap on SOI-CMOS. Xpeedic: Innovative EDA Solutions to Enable Differentiated RF-SOI Designs (Feng Ling, CEO)RF-SOI is growing, but there are still design challenges in process, models, filters and packaging. To design a good front end, you need better models and filters. People think passives are easy, but you need accurate models here. Xpeedic has developed design flows that include the effects of packaging early in design. Their products include IRIS, iModeler and Metis (for packaging). They've also introduced substrate modeling in partnership with CWS in France. The product is called SiPEX: it can address linearity in switch or PA designs. You need accurate substrate models to do this. Customers indicate they're seeing big improvements as well as reductions of 25% in chip area. IDP filters is another place they're working, to provide RF filters to fabless IC or module companies. No single filter technology can fit all the needs – IDP is one of them, so they have a broad portfolio of IDP filter technologies. He closed by saying that especially in China, the SOI ecosystem is really growing. SESSION 3: RF VALUE CHAINTowerJazz: Specialized RFSOI Foundry Technology to Support Rapid New Product Development (Paul Hurwitz, Director of RF Technology Development)This presentation gave a full overview of what TowerJazz offers in terms of RF-SOI foundry services with its fabs in Isreal, the US and Japan. What's new in 2019 is a diversifying of 200mm and 300mm. 200mm is best for power handling (for infrastructure/basestation antenna tuners and switch power handling, for example). 300mm is best for SW and LNA integration and higher digital densities. They've got new SOI models for the latest technology generations, and physics-based modeling of RF breakdown for accuracy. With more die being flipped, they needed new substrate modeling. For LNA and switch integration in 300mm, they invested in RF modeling. They also have an in-house MPW (multi-project wafer) program. He noted that customers in China are moving quickly in response to their customer requirements. Okmetic: Tailored Silicon Substrates for RF Applications (Atte Haapalinna, CTO)Okmetic Oy is a niche player in the substrate materials market, with specialties in sensors and MEMS, where they are the market leader. Now part of China’s NSIG group, they are expanding their manufacturing facility in Finland. In this presentation, their CTO talked about their current offerings as well as what they have under development. They do 150-200mm wafers, with a special emphasis on thick SOI. In terms of silicon substrates for RF, ultra-high resistivity is key. Their wafers are also used in IDP – integrated passive devices – for RF and acoustic filters. They are continually improving their high resistivity Magnetic Czochralski (MCz) silicon wafers, and are developing substrates for RF passives for automotive V2X. For RF beyond 6 GHz, they are looking at customized high resistivity silicon wafers for mmWave with researchers and customers. For sensors, they do SOI wafers with built-in cavities. Incize: RF SOI Ecosystem – History Challenges (Mostafa Emam, CEO)The world is exceeding expectations in terms of data usage. While the CAGR for devices is 27%, for data it’s 46%. Therefore each device needs to be faster and more power efficient. Incize recognizes RF as an art, with each piece hand crafted. But artists need to see the whole picture: at Incize, they help 17 companies – including wafer suppliers, foundries and fabless – see that big picture, especially in measurement, characterization and modeling for RF. For wafer suppliers, they do very high-power and very precise on-wafer testing to determine things like intermodulation distortion and substrate interference. For foundries, their specialty is in RF switches, for whom they do harmonics testing and thermal noise management. With those insights, Incize foundry customers have drastically increased the performance of the RF chips they’re manufacturing on trap-rich, high-resistivity SOI wafers. Meanwhile, Incize is also preparing PDKs for future potential substrate generations including GaN-on-Silicon, silicon-on-porous, and new contactless testing techniques for piezoelectric-on-insulator (POI – used in filters in 4/5G). “There’s a really big business opportunity for RF-SOI,” concluded Emam, “and room for everyone.” Cadence: SOI Technology in Intelligent and IoT/Vision/AI Systems (Jonathan Smith, Senior Director)Cadence does SOI enablement at advanced nodes. Smith shared three recent success stories. First, there’s the Musca-S1 test chip they did with Arm, Samsung and Sondrel this past spring. Second, there’s the Tensilica DSP for automotive vision on GlobalFoundries’ 22FDX, which uses 1/10th of the power of existing solutions and was demonstrated at CES. And finally there’s the i.MX line from NXP. In recent news, there’s a new version (18.1) of Virtuoso RF. Though it’s been on the market for 30 years, they’ve added advanced methodologies so that system design and analysis are on the same platform. They’ve also announced National Instruments’ analysis solver, the Clarity 3D solver for next-gen 3D solutions, the integration of multiple electromagnetic (EM) solvers, and advance SiP options. Silvaco: Xena-IP Management Infrastructure for the SOI Ecosystem (Babak Taheri, CEO)Every multi-core SoC today has as many as 200 IPs, if not more. How do you manage that? Tracking and traceability of IP is complicated but important. For IP providers, how do they track where its being used? And for IP consumers, they need to know what they’ve used and where. What’s required is an IP management system to keep track of the different functions and different concerns. Today’s tracking systems don’t talk to each other. Silvaco’s Xena IP management solution organizes all IP data, accounts, products, contracts, devices, support, compliance and reporting. For compliance in particular, they do IP “fingerprinting” and “DNA analysis”, which they’ve patented. The fingerprint is a digital representation of the IP: it’s not just software. It is secure, and can’t be reverse engineered. It’s not a tag: a tag is inserted into the IP, whereas fingerprints are extracted. DNA analysis flags discrepancies and quickly identifies where they are and which files to look in. Xena works in the cloud, enterprise systems or hybrids. The SOI ecosystem will be hearing a lot more about this. ~~ Please note that the China event presentations are all available on our website to anyone whose company or organization is a member of the SOI Consortium.

The 45th (yes!) IEEE SOI Conference takes place 14-17 October 2019 in San Jose. Now called S3S –since it also covers 3D and subthreshold – it’s a networking event par excellence: a unique opportunity to meet firsthand the movers and shakers in the SOI ecosystem and the giants of R D. As always, it has a strong technical program you won’t want to miss. Plus this year there’s a full-day short course dedicated to FD-SOI design, and half-day tutorial on RF design. Get all the details and registration info at http://s3sconference.org/.The SOI Consortium’s own Executive Co-director Jon Cheek of NXP is one of the keynoters. In fact the consortium membership is extremely present at this event, with over half our member organizations having a hand in it. There’s a plenary talk by GF’s CTO/VP Subramani Kengeri, keynotes by ST Fellow Andreia Cathelin and NXP Fellow Rob Cosaro, and invited talks from Arm, Samsung and Dolphin Design, for example. And this year’s General Chair is Incize CEO Mostafa Emam. Focus Sessions #12 and 13 are all about FDSOI Platforms and Products, with invited speakers from Renesas, NXP, ST, ARM, GF, Huali and Dolphin Design, while focus Session #2 is all about RF-SOI. Here’s the agenda for the FD-SOI Design short course (which takes place on Thursday, 17 October):Short Course Opening and Welcome Philippe Flatresse, Business Development Marketing Director, Dolphin DesignGLOBALFOUNDRIES 22FDXTM Technology and Body Bias Compensation to Enable New Design Optimization Strategies Joerg Winkler, Fellow Design Engineer, GLOBALFOUNDRIESEmbedded Flash Memory Technologies and Applications in Advanced Nodes Memories Koji Nii, Vice President, Global Marketing Sales, Floadia CorporationEnabling the Adaptive Body Bias in Modern IoT Applications Vincent Huard, CTO, Dolphin DesignSoC Design Realization with Adaptive Body Bias Kripa Venkatachalam, IC Design Practice Director, Mentor Graphics Didier Roland, Application Engineers Manager, Mentor GraphicsAnalog Design Techniques for Microprocessors in FD-SOI: Power-Management, PVT Monitoring and Data Conversion Edevaldo Pereira Da Silva Junior, Senior Principal Engineer, NXP Semiconductors MPU/MCU R DLow Power Solutions for SoC Architectures Antonio Pullini, Senior Hardware Designer, GreenWaves TechnologiesSOI to RF Sidina Wane, CEO, eV-technologiesIf you know the way to San Jose, you'll want to be at S3S 2019, for sure!

The SOI Consortium and member companies had a significant presence at two important events in China recently: the World Semiconductor Congress (WCS) in Nanjing and the SOI Academy, including an FD-SOI Training Day in Shanghai. Nanjing is especially known as a leading RF chip design hub in China, but WCS went well beyond RF. The three-day 2019 event was held at the Nanjing International Expo Center. It attracted over 30,000 visitors, 5000 of whom attended the various summit forums. Presenting at WCS '19 in Nanjing (clockwise from top left): Wayne Dai, CEO/Founder, VeriSilicon; Carlos Mazure, Executive Director, SOI Consortium; Giorgio Cesana, Director, STMicroelectronics; Christophe Tretz, Design Expert, SOI Consortium. (Photos courtesy: WCS)The SOI Consortium organized the SOI Forum, which was part of an afternoon Innovation Summit. Presentations were given by members of the SOI Consortium team, and by leaders from our membership, including Simgui, NXP, Incize, ST, IBM, Cadence and Xpeedic. Some of those presentations are now available from our website -- click here to get them.Earlier in the day, SOI Consortium member VeriSilicon participated in a morning session on AI and IoT Wireless Communications. They presented their low-power Bluetooth design platform for GlobalFoundries 22FDX, and CEO Wayne Dai moderated a lively round-table discussion.Following hard on the heels of the Nanjing event, the SOI Consortium team and members headed to Shanghai for the SOI Academy 2019, hosted for the second year in a row by member SIMIT (Shanghai Institute of Microsystem and IT under the Chinese Academy of Sciences). The two-day event attracted more than 250 professionals from more than 100 domestic and foreign IC companies and research institutes. Keynotes by SOI Consortium Executive Director Carlos Mazure, SITRI CEO Mark Ding and Jean-Eric Michallet, Head of the Microelectronics Components Department at Leti and bizdev director for the SOI Consortium focused on the SOI ecosystem. The SITRI and Leti talks also gave updates on their research and industrialization alliance. Further talks were given by leaders from Soitec, GlobalFoundries, VeriSilicon, IBM and Xpeedic. These addressed the growing FD-SOI ecosystem, applications in automotive electronics, 22 nm and 10 nm FD-SOI devices, advanced SOI substrate technology, China’s FD-SOI development, the FD-SOI manufacturing process, product design, EDA tools and all aspects of industry’s software and modeling value chain.Several speakers noted that more and more local Chinese customers are actively adopting FD-SOI for low-power, high-performance chips. SOI Academy, Shanghai, 2019, FD-SOI Training Day attendees.(Photo credit: SIMIT)The second day was devoted to hands-on professional training, given by experts from Leti using an actual PDK and punctuated by in-depth discussions. This helped the IC designers to fully understand the advantages and flexibility of FD-SOI in low-power logic, analog/mixed-signal and RF. All in all, “It was a great success,” concluded Jean-Eric MICHALLET, Head of the Microelectronics Components Department at Leti and bizdev director for the SOI Consortium. Plans for the next SOI Academy are already underway, with plans to extend the topics to include more on photonics, RF, power and MEMS.

Join us! In partnership with our members, the SOI Consortium is co-organizing and participating in two key SOI events coming up in China over the next few weeks. On May 18th, we’ve put together an SOI Forum at the World Semiconductor Congress (WCS) in Nanjing. And on May 23rd 24th, we’ve teamed up with our members SIMIT, Sitri and Leti for another in our series of SOI Academies, including an FD-SOI Training Day. (The last one this past winter was a terrific success – read about that here if you missed our coverage at the time.) QR code for WCS, Nanjing '19At WCS, the SOI Forum (sub-forum #8) is part of the afternoon Innovation Summit. We’ll cover the broader SOI ecosystem, including both RF-SOI and FD-SOI – from wafers to design through manufacturing. Presentations will be given by members of the SOI Consortium team, and by leaders from our membership, including Simgui, NXP, Incize, ST, IBM, Cadence and Xpeedic. Click here or scan the QR code for the full program and registration information. Also at WCS, SOI Consortium member VeriSilicon will be participating in a morning session on AI and IoT Wireless Communications (sub-forum #4). They’ll be giving a presentation on their low-power Bluetooth design platform for GlobalFoundries 22FDX, and their CEO Wayne Dai will be moderating a round-table discussion. You can get more information on that (in Chinese only, tho) here, or follow VeriSilicon on WeChat. QR code for SOI Academy and FD-SOI Training, Shanghaid 2019The SOI Academy in Shanghai is an opportunity for experienced designers to gain solid expertise in FD-SOI. The event begins in the afternoon of May 23rd with a series of informative plenary talks by members of the SOI Consortium team, and by experts from our members Leti, Soitec, VeriSilicon, GlobalFoundries and NXP. The FD-SOI Training starts the next morning, on May 24th.. This is a hands-on event lead by top experts from Leti. The morning is devoted to digital design in FD-SOI, and the afternoon to RF design (including for 5G) in FD-SOI. Attendees will get a comprehensive understanding of design techniques for low-power chips leveraging the multiple benefits and flexibility of FD-SOI technology. Get more information here, or from the WeChat QR code.We've got a busy schedule! To keep up to date with where we and our members will be promoting the SOI ecosystem, be sure to check our Events page regularly.

FD-SOI for RF and mmWave communications is a hot topic. In high-data rate communications like RF and millimeter-wave devices in particular, FD-SOI delivers high-performance with numerous unique advantages, making it most likely the fastest RF-CMOS technology on the market. If you’d like to take a deep dive and learn more about it, Soitec and Incize are sponsoring a free, full-day workshop in Grenoble on April 4th, 2019. Click here for registration information. The workshop follows the day after the IEEE/EDS EuroSOI-ULIS conference there (you can read about the full conference in a previous ASN post). This technical workshop will cover the FD-SOI technology platform with a focus on its compatibility with RF mmWave communications. Attendees will hear from notable FD-SOI leaders and experts from leading industry and research institutions presenting updates on key developments and building blocks across the semiconductor value chain. Topics will include circuit design, device fundamentals, simulation and characterization of RF devices, test, CMOS technology and substrate technologies enabling FD-SOI. In addition, the workshop will include an overview about how FD-SOI technology is benefiting current and future end user applications. Here’s the agenda: [caption id="attachment_15990" align="alignleft" width="945"] FD-SOI technology platform: new standards for emerging consumer electronics [Click to enlarge.][/caption]

Lots of great information came out of the two days of workshops in Japan recently organized by the SOI Consortium. Some of the presentations are now posted on the consortium website (get them here). The first day (held in Yokohama and sponsored by Silvaco) focused on FD-SOI and RF-SOI design. The second day (held at U. Tokyo) focused on More than Moore (especially silicon photonics, MEMS sensors), and the SOI manufacturing ecosystem. The 1st day panel discussion was so interesting we'll give it a post of its own, then follow up with round-ups of the presentations from both days. And now to ramp! The morning panel discussion on end-user deployment for FD and RF-SOI was moderated by SOI Consortium Executive Director Giorgio Cesana. GF's CTO Subi Kengeri led off saying that that 2017 had been the year of FD-SOI adoption. Samsung Director Adam Lee noted that in the beginning nobody believed it would get traction, but now everybody does, and Samsung is commercializing it: chips coming out this year will ramp in volume in 2019. [caption id="attachment_12578" align="aligncenter" width="875"] Panel on FD-SOI and RF-SOI end-user deployment, SOI Workshop Japan, 2018. Giorgio Cesana, SOI Consortium Executive Director, Moderator; John Carey, ST Director; Adam Lee, Samsung Director; Subramani Kengeri, GF CTO; Wayne Dai, VeriSilicon CEO; Mostafa Emam, Incize CEO. (Courtesy: SOI Consortium)[/caption] VeriSilicon CEO Wayne Dai said he sees great potential in IoT, where the volumes are high but fragmented. In IoT, he said, you need RF, but you really only need very high performance about 20% of the time, which is a perfect fit for FD-SOI. ST Director John Carey noted that ST's been using FD-SOI since 2014. They've fabbed products for cryptocurrency and infrastructure. Now in their second and third generations of designing with it, they've got some big FD-SOI chips coming out next year with embedded memory and RF. He sees it being particularly successful in mmWave, automotive and IoT. The conversation then shifted to RF-SOI. Mostofa Emam, CEO of Incize, explained that since RF-SOI is already in every smart phone, it's in a different situation from FD-SOI. The emphasis here is now on adding more blocks. “RF is an art,” he said. “It takes an artist. You need talented artists and tools.” One of the biggest challenges for fabs that are newcomers is models – not just at the transistor level, but also at the substrate level. The big players have addressed this, but Incize is working to support more foundries with new, innovative approaches, and helping them develop robust PDKs. The industry needs more good RF designers as well as better RF design flow, he concluded. Coming back to FD-SOI, Cesana asked about non-volatile memory (NVM). Samsung's Lee said they've already got NVM options including eMRAM for 28nm, and customers are now requesting eMRAM PDKs for the next node (18FDS). ST's Kengeri added eNVM is important for FD-SOI, especially since flash is not scaling. While there are lots of options, MRAM gives you all the value, and in FD-SOI it only adds three more mask steps, so cost savings are maintained. With respect to local computing for AI with FD-SOI, everyone agreed on the importance of the edge. In addition to RF, FD-SOI gives you density even at 28nm, explained Carey. You can manually control power with back biasing, so you get something very flexible, especially for NB-IoT applications where the battery will have to last for 10 years. In fact Kengeri sees FD-SOI as enabling fog/edge computing. 5G – What's First? The next question was about 5G: which applications would we be seeing first, and how does FD-SOI help? Lee said Samsung's seeing it for apps up to 10GHz as well as mmWave. Customers are telling them they want FD-SOI for technical reasons. Kengeri expanded on that point, saying it comes down to fundamental physics: gate resistance, capacitance, mismatch. FD-SOI has lower Vmin and better Fmax compared to FinFETs, and that's what tier-one players want. Carey brought it back to RF-SOI (noting that ST's introducing a 45nm version), which supports a large number of elements and increased complexity with smaller power budgets. Emam then asked the foundry guys about mmWave. Substrates won't be the bottleneck he said, so what's the FD-SOI/mmWave roadmap? Kengeri responded that GF's ready. Lee said Samsung is also ready, and you'd see it next year on handsets. Samsung has engaged with customers on 30GHz for the middle of next year, he added: it's qualified. Carey said ST sees it first in consumer premises equipment that's connected by satellite. The right enabler Cesana then asked about image sensor processors (ISPs), noting that analyst Handel Jones has said this is a big opportunity for FD-SOI. You can do 3D integration with sensors, but heat makes noise, so you need technology that decreases heat production and doesn't give you hotspots (which would be visible in the image). Kengeri pointed to challenges in power density, thermal envelopes and the RTS (random telegraph noise signal). Although there are a lot of options, FD-SOI plays well for thermals and noise, so GF sees a good opportunity here. Dai added that the industry needs volume applications for FD-SOI, and ISPs need to bring more logic closer to the camera. And he concurred that you need FD-SOI for the thermals: it's very important. In closing, Dai noted that as a design house, “We walk on two legs: FinFETs and FD-SOI.” 28, 22, 18 and 12nm FD-SOI all enable differentiation. In particular, you need something between 20nm and 7nm: FD-SOI is here. Asked about Japan in particular, Dai said beyond automotive he saw lots of potential in ULP for AVR. Kengeri added that for any applications besides performance-at-any-cost, FD-SOI is the right enabler.

RF-SOI is in every smart phone out there, and with 5G, there are lots more applications on the horizon. If you’d like to learn more about designing in RF-SOI, there’s a great short course coming up the day before and in conjunction with the EuroSOI-ULIS Conference in Granada, Spain.The title of this short course is RFSOI: from basics to practical use of wireless technology. Program and registration details can be found here. The course runs for the full day on Sunday, 18 March 2018.The talks, which are being given by a stellar line-up of experts, include: RF SOI, fabrication, materials and eco-system - Ionut Radu Director of Advanced R D, Soitec Fundamentals of RF SOI technology - Jean-Pierre Raskin, Professor, UCL 22nm FDSOI Technology optimized for RF/mmWave Applications - David L. Harame, RF CTO Development and Enablement, GlobalFoundries RF SOI technology and components for 5G connectivity - Christine Raynaud, Program Manager (Business Development – Technology to Design), CEA-Leti Analog and RF design on SOI - Barend van Liempd, Senior Researcher, imec Techniques and tricks for RF measurements on SOI - Andrej Rumiantsev, Director RF Technologies, MPI Corporation FOSS TCAD/EDA tools for advanced SOI-device modeling - Wladek Grabinski, R D CM Manager, MOS-AK RF design flow for SOI - Ian Dennison, Design Systems Senior Group Director, Cadence The course is being organized by SOI Consortium members Incize and Soitec. BTW, this year marks the 4th joint EUROSOI – ULIS Conference. The EuroSOI Conference, which has been ongoing for decades, is well paired with the ULtimate Integration on Silicon Conference. The joint conference provides an interactive forum for scientists and engineers working in the field of SOI technology and advanced nanoscale devices. One of the key objectives is to promote collaboration and partnership between different players from academia, research and industry. As such, it covers technical topics, industry trends and updates from pertinent European programs. EuroSOI-ULIS will take place 19–21 March 2018 at the University of Granada in Spain. For information on the program and how to register, see the website. Following the conference, the papers will be available at the IEEE Xplore® digital library, and the best papers will be published in a special issue of Solid-State Electronics.