VeriSilicon

VeriSilicon provides platform-based, all-round, one-stop custom silicon services and semiconductor IP. For two years running, they’ve been the #1 Chinese IP provider and well into the Top 10 worldwide (per IPnest 2020). They’re also an FD-SOI design powerhouse. Founded in 2001, VeriSilicon first began work on FD-SOI in 2013. Now they’re headed for listing on the Shanghai STAR exchange. SOI News talked to President CEO Dr. Wayne Wei-Ming Dai about his company’s innovative business model, and opportunities for FD-SOI.SOI News (SN): You call the VeriSilicon business model “SiPaaS”, for Silicon Platform as a Service. Can you tell us what that means? Is it particularly well-suited to designs based on FD-SOI? Dr. Wayne Wei-Ming Dai (WD): We see SiPaaS as the third transformation in the semiconductor industry. If you take a minute to look at the evolution, first was the IDM model of the 1960’s and 70’s, largely based in the US and Japan and driven first by the US military, then home appliances and consumer electronics. The second transformation was the foundry model, driven heavily by the PC and cellular communication, with a geographic center heavily based in Taiwan and Korea. That solved the CAPEX challenge. Now with the IoT, we solve the OPEX – operational expenses – challenge. Although 60% of our business comes from outside China, we do see particularly good opportunities for China. With AI and AIoT, there’s a lot of custom designs. You have a new model with the chip as a system, with lots of IP – but it also is much more expensive. The VeriSilicon SiPaaS model covers everything from IP to final tape-out, delivers packaged and tested parts, and that accelerates time to market and saves money. If you consider the share of R D expenses as a percentage of chip revenue, for leading fabless companies, they can be 20-30%, and you need to have a gross margin of 50% and higher. But if your gross margin is 40% or below, you might out of business. The VeriSilicon model seeks to transform the design-heavy model, where designers use their own IP, to the next wave, which is design-lite. When you’ve got a design-lite model for A/IoT, you don’t need such a big team. This is the third transformation. You first saw this starting in a major way in Israel, where going to design-lite enabled fabless companies to move very quickly. But you still need IPs, and for those working under a traditional model, we have those. In SiPaaS, we offer IP platforms. Chip design is kind of like building a house. If you want, we can just give you the kitchen – so that’s some specific IP. But we can also give you the entire house. The IPs form the solutions. For each type of application, there are similar IPs that need to be integrated. Sets of IPs form subsystems for IoT, automotive, medical, wearables, audio, video, etc. There are no boundaries on the platforms, but each have typical elements. In this industrial transformation, and now especially for AIoT, you’ll need many more chips in many different places. We have a lot of IP that we created organically, but we also made some major acquisitions over the years. For example, 13 years ago we bought a Dallas based DSP division from LSI Logic. Our design-lite platform approach plays particularly well in FD-SOI, where designers want to maximize the advantages of the technology. Remember that much of the original IP for FD-SOI comes from ST or Samsung. When Samsung first licensed 28nm FD-SOI from ST, we got a whole set of 28nm FD-SOI IP from ST with modification rights. So we started to play with them. Then that IP went to Synopsys. We have modified, optimized and customized it for customers. And with GlobalFoundries’ 22nm FD-SOI, when the IP comes out, we're the first ones invited to test it. So we focus on those IPs. We do benchmarks on ARM and others. And we’ve designed our own IPs for RF and more. We’ve done the body biasing circuits and software control, so we support design methodologies. People often ask us to show them how good FD-SOI is. So we do a lot of benchmarking. At 28 bulk, we can do apple-to-apple comparisons. And 28 bulk or 22 FD-SOI, it’s the same team, so we can do those comparisons, so they can compare the two nodes. And we’re partnering with more 3rd party IP companies – including smaller players – providing FD-SOI IP, which is great. [bctt tweet="Our design-lite platform approach plays particularly well in #FDSOI, where designers want to maximize the advantages of the technology - @VeriSilicon CEO Wayne Dai #IoT #edgeAI #wearables" username="SOIConsortium"] SN: You have been a very vocal champion of FD-SOI. Why? WD: We’re not against FinFET – that a really big part of our business and we’re very advanced in it. We were the first to do a tape-out on Samsung’s 7nm UV FinFET test chip and are working on 5nm. While overall we tape out over 30-50 chips a year, we are foundry neutral. But we recognize that FinFETs are not for everything: there are some things that FD-SOI does much better. Integrating RF, for example – it’s not impossible but it’s not natural in FinFET. Yes, if you’ve got a big digital chip running at high speed most of time, FinFET is better. But if you’re running high speed some of time, say around 20%, especially integrating RF, FD-SOI is better. And back biasing is impossible in FinFET. In the end, we “walk on two legs”. SN: What do designers need to know about FD-SOI? WD: Body biasing can sound complicated, but the thing is, you don't play with each transistor. In theory, you can control each transistor with body bias, but in reality, you do it region by region. With body biasing, you can dynamically make different parts of the chip behave differently. This is key. Some parts are reverse biased. Some parts are forward biased. You play with this block by block, and kick it in as-needed by software after the chip comes back. So in IoT, for example, where it's very serious low power, you may want to shut down certain parts when you're not using them, while other parts always need to be on. If you choose one of our platforms, we’ve taken care of that. There may be parts you only need to bring up and run at high-speed for certain tasks. So body biasing gives you all sorts of controls. With FinFETs you can't do that, you can just play with voltage scaling. You can drive up the speed – the dynamic power – when needed with forward biasing. During that time, you're not really worrying about leakage power because when the task is done you can completely shut down those parts again. It also changes tape out. Typically designers do worst case. But you might not need to design for the worst case: you leave too much on the table. With body biasing, if you solve for typical, when the chip comes back, you can tune and make adjustments post-silicon. So you can do an aggressive tape-out, which is much more effective than starting off with a worst case. True, if you sign off worst case, your chip can always run very fast, but sometimes you don't need that. And in order to solve for worst-case, you put in a lot of buffers or whatever for timing closure, which is unnecessary effort. What's more, for different applications, the worst case can be different: some applications may need some higher speeds and sometimes less. If you solve for typical, then depending on the application you can software-tune the device. In the past, you never had that kind of thing. With body biasing in FD-SOI, you can solve for typical, so you can save a lot of area and a lot of design cycle in terms of timing closure, in terms of use of buffers. If silicon comes back, and it's missing something – say you need it to go a little faster – I’ve done body biasing, so I adjust the timing. Most times it's probably ok, it's good enough. Of course, some applications you need some combination of fast and slow, and you can leverage the body-biasing post silicon to change what's fast and what's slow on the fly. Like in wearables, power is very critical – some parts are always on, and some parts are sometimes on. For the parts that are always on, you need to reduce the leakage, and you do that with reverse body biasing. For other parts, you bring them up and you run as fast as you can for a short period of time – in this case leakage isn't as important because most of the time it's shut down. But dynamic power is important. High performance is important. For that part you need forward biasing. With different parts of the chip, you can play with different things. Before, you had to do this before tape-out, and sometimes had to do worst-case, which should never happen: you leave too much margin on the table, because after silicon you couldn’t do anything. But now with body biasing in FD-SOI, you have the capability – you don't need to do worst case – if needed you can always adjust. And for different applications in the chip, you might need a different kind of operating frequency, right? So you can create different chips from the same chip. With body biasing, you can always tune to whatever you want. If I’m short of something, I can do some body biasing bring up the speed. Now that's different from voltage scaling. You cannot dynamically achieve voltage scaling. You might have two voltages – one's high, one's low. But you cannot continuously change. In FD-SOI the same die maybe has different applications with different performance requirements, so we don't need to do worst case design. They can come up with different performance chips in the same silicon. SN: What do you see as the drivers? WD: IoT, AIoT and automotive. Also RF, mmWave and connectivity. And at the edge, where you need very low power. FinFET and FD-SOI both solve the leakage problem. But if you need sleep mode most of the time and high performance 20% of the time, it is more energy efficient to use FD-SOI. There are a lot of applications in this category. In 12nm FD-SOI, you’ll reach almost the same performance as 7nm FinFET at 14nm cost. [bctt tweet="#FinFET #FDSOI both solve the leakage problem. But if you need sleep mode most of the time and high performance 20% of the time, it is more energy efficient to use FD-SOI /@VeriSilicon CEO #edgecomputing" username="soiconsortium"] You’ve seen some stagnation of IoT at the 40/55nm process nodes because at those nodes the performance was not as good as expected. You needed two AA batteries. The value of the IoT data was not generated, collected or analyzed. What you need is AI at the edge to pre-process the raw data so you lower network capacity requirements. AI at the edge is a great opportunity for FD-SOI. SN: How do you see the role of the SOI Consortium? WD: We work with the consortium for these big forums; in particular VeriSilicon co-founded and has now co-sponsored the Shanghai FD-SOI Forum for seven years. They’re the most visible and high quality. The consortium knows the people that need to know each other. There are a lot of meetings during these events, and a lot of deals are sealed; one signature event is the river dinner cruise where “everyone is on the same boat”. ~ ~ ~ Related VeriSilicon press releases: VeriSilicon Releases Most Advanced FD-SOI Design IP Platform on GlobalFoundries 22FDX for Edge AI and IoT Applications (2019-10-24). The VeriSilicon 22FDX IP Platform includes over 30 low-power, low-leakage and high-density memory compiler IPs and various key mixed signal IPs. VeriSilicon provides a one-stop silicon design service to customers designing for AIoT with mature IPs to shorten custom design cycles and reduce their R D costs. FD-SOI Body-Bias technology allows the user to adjust device threshold even after silicon is manufactured: it can enable dynamic tuning between High-Performance and Low-Power, and enhance the design flexibility without extra cost. Advanced ATSC 3.0 Chip Launched for Mobile and Broadcast Applications (2019-01-08). The demodulator SoC was designed and developed by Saankhya Labs with ASIC turnkey design and manufacturing services from VeriSilicon, using Samsung Foundry’s state of the art 28FDS (its Fully Depleted SOI process technology), chosen for its unique low power capabilities offered by the back bias option. (See more in-depth coverage on this announcement from SOI News here.) VeriSilicon Announces Ultra Low Power BLE 5.0 RF IP based on GLOBALFOUNDRIES 22FDX FD-SOI Process for IoT Applications (2018-11-01). The IP includes a transceiver that is compliant with the BLE 5.0 specification and supports GFSK modulation and demodulation. The silicon measurement shows that the sensitivity can be tested up to -98dBm with less than 7mW power dissipation in typical conditions. It largely improves battery life for low power IoT applications. In addition, the RF transceiver saves 40% area compared to a similar implementation on 55nm bulk CMOS. Besides the RF transceiver, this IP integrates on-chip balun, TX/RX switch and 32K RC OSC driver to save the BOM. Moreover, high efficiency DC/DC and LDOs are also available for power management. “Wearable and IoT markets especially the wireless earplug market are growing rapidly, and it will surge through consumer use, hearing aids, personal care and other industrial applications.” said Dr. Wayne Dai, Founder, Chairman, President and CEO of VeriSilicon. “By taking advantage of integrated RF capabilities of FD-SOI, in particular GF’s 22FDX, our BLE 5.0 RF IP will significantly reduce the system cost and greatly boost the growth momentum of wearable products such as wireless earplugs.” GlobalFoundries and VeriSilicon to Enable Single-Chip Solution for Next-Gen IoT Networks (2017-07-13). The integrated solution leverages GF's 22FDX technology to decrease power, area, and cost for NB-IoT and LTE-M applications. VeriSilicon's Artificial Intelligence Engine Delivers Multi-Sensory Experiences in NXP's i.MX 8 Flagship Applications Processor. (2017-06-08).

The first day of the SOI Consortium’s recent China event – the 7th Shanghai FD-SOI Forum – was full to bursting in every way: the room, the networking, the level of expertise, the in-depth presentations and the overall energy. We covered the Samsung and GlobalFoundry keynotes in our previous post (if you missed it, read it here).This post will recap the rest of the presentations given during the day. (If your company or institution is a member of the SOI Consortium, you’ll be able to access the full presentations online.)International Business Strategies (IBS) – Impact of AI on Automotive and IoT, and Opportunities in China (Handel Jones, CEO) When it comes to deep insights on China + tech + analytics, and especially with a thorough understanding of FD-SOI markets, Handel Jones is arguably the world’s leading expert. Here are some of the observations he shared. Though the chip industry will see declines across the board in 2019 (he sees 13.5%), he sees a return to growth in 2020. By 2030, he sees it as a trillion dollar market, of which China will have half. AI is a key driver – and will become more prevalent at the edge. Major drivers will include preventative medicine, gaming, NB-IoT and 5G. At the chip level, FD-SOI has a lower cost/chip compared to bulk – you’ve got small chips and high yields. Sensors – especially image sensors – are a key area, and this is another place where FD-SOI is better than bulk. He sees chip shortages in the 2022-24 time frame (as opposed to the current oversupply), so now is the time that China should be establishing large FD-SOI capacity.NXP – Automotive, Industrial and IoT Solutions Leveraging FD-SOI (Ron Martino, VP GM) In terms of power consumption, computing is easy but data transmission is hard, Ron Martino reminded the audience at the onset. That’s why you need the edge. This is where FD-SOI comes in, and if you want to have leadership, you should be leveraging body biasing, he said. In terms of machine learning, a lot can happen at the edge on the smallest devices. NXP is now shipping a very wide range of products based on FD-SOI, including the i.Mx7 and 8 families and the new RT crossovers. The latest announcement is the i.Mx RT 1100 MCUs, a very low-cost processor solution for high volumes. The i.MX7 ULP is in mass production for wearables, with record low leakage and high performance. The i.Mx8 and 8x are going into a broad range of applications – from retail solutions for automated checkout to pasta makers, and automotive applications for full cockpits with vision detection, as well as things like parking, V2X and in-vehicle monitoring.Sony Semi – Low Power IoT Products with FD-SOI eMRAM Technology (Kenichi Nakano, GM) Chips built on FD-SOI with eMRAM are in production, said Kenichi Nakano. In GNSS/GPS, Sony is the #1 in lowest power consumption worldwide, thanks to FD-SOI, he continued. They’ve had 70 remarkable design wins, giving them over 50% market share in the sports and health watch markets, he said with a tip of the hat to the FD-SOI ecosystem and SOI Consortium. In GNSS, performance is very important – and now they can do it in water, which is huge. Development cycles are shorter than ever – for the latest chip it started in February 2018 and was in production by the spring of 2019, achieving decreases of 20% in power, 30% in area and 10% in cost. Integrating eMRAM was easy in terms of the design flow and manufacturing, with production yield of 97-100%. So with the GXD5605GF they’ve got the first GNSS chip with FD-SOI/eMRAM/RF in the world and it’s on 28FDS/eMRAM technology. It’s very reliable and very good, he concluded.Rockchip – Challenges of AIoT Chip (Feng Chen, SVP) At the beginning of this year Rockchip announced the launch of their RK1808, a low-power AIoT solution with built-in high performance (3TOPS) NPU fabbed in GlobalFoundries 22FDX, said Feng Chen. Their clients were very happy that Rockchip delivered the real power and performance numbers they’d promised. Because of the power/performance it delivers, FD-SOI (both 22 and 28nm) is very well suited for AIoT chips, he said. It’s very cost-effective in terms of NRE and die, and there’s room for further savings. While the ecosystem needs a unified push, FD-SOI is good for the market in China, and China has the volumes FD-SOI needs. Rockchip sees particular potential in retail and smartphones.Panel – Verticals Driving FD-SOI VeriSilicon CEO Wayne Dai moderated the first panel, asking first why China should adopt FD-SOI. Soitec CEO Paul Boudre said because it is a big, dynamic market (noting that Sony’s first FD-SOI GPS win was in China). Handel Jones said that at the wafer level, there was cost parity, but with FD-SOI chips are smaller and higher yield. The main reason it’s taken so long to get going was IP, but that’s changing now, he added. Dai’s next question was about the top application fields the panelists predicted for 2020. Sony’s Kenichi Nakano said wearables with connectivity, low power consumption, small size and high levels of integration; Rockchip’s Feng Chen agreed. NXP’s Ron Martino said FD-SOI for automotive, machine learning and edge computing was shipping now, with wearables ramping.VeriSilicon – Low Power IoT Connectivity IP Design Based on FD-SOI (Yi Zeng, Director, IoT Connectivity Platform) The “value” of IoT data is not yet being generated, noted Yi Zeng but AI can help here. The IoT industry needs innovation for both chips and networking. SiPaaS – which stands for Silicon Platform as a Service – as offered by VeriSilicon can help lower the barrier to entry. [In the SiPaaS model, VeriSilicon has its own IP-based core. Based on the company's advanced chip design capabilities and mass production service experience, it has created a variety of silicon-proven chip design platforms that can significantly reduce the customer's chip design cycle.] They have FD-SOI IP for NB-IoT, BLE, GNSS and sub-1 GHz. The BLE (Bluetooth) RF IP is a complete offering optimized for low power on GlobalFoundry’s 22FDX. The NB-IoT IP is also optimized on their 22FDX ZSPNano, an energy efficient general purpose MCU+DSP core on 22FDX. And they’ll have results of test chips for GNSS RF IP on 22FDX by the end of this year.Secure-IC – AIoT Embedded Security Using FD-SOI (Hassan Triqui, CEO) While AI enables products and services, it’s important to plan for security early in the design cycle, said Hassan Triqui. Software is not enough to protect edge-to-cloud. Secure-IC’s hardware security module, Securyzr, is an IP block that can be embedded into every device to answer security functionalities such as root-of-trust and key management. In sleep-mode/tunable cryptography, FD-SOI allows the creation of physically secure systems. (Note that designers are leveraging FD-SOI’s unique body biasing for ultra-low-power deep-sleep modes.) Because safety and privacy require a combined solution, Securyzer is particularly well-suited to IoT chips built on FD-SOI, he concluded, so that IoT adds value to AI, and not just the other way around.Soitec: FD-SOI – The 5th Gear for mm-Wave Radio (Michael Reiha, GM FD-SOI Business Unit) There are four key areas to 5G, explained Michael Reiha: coverage, number of antennas, frequency and traffic density. 5G mmW access architectures are currently inefficient in terms of power and performance, but FD-SOI is ready for 5G access as both an analog and hybrid beamformer. For MU-mMIMO (massive MIMO), the RF front-end modules (FEMs) and transceiver will fully exploit FD-SOI. Sensing, calibration and control enabling hybrid beamforming and multiple users is easy in FD-SOI. The adaptive body biasing on the horizon will reduce power of FEM mixed-signal circuitry, and be a disruptive technology.STMicroelectronics – Automotive MCUs in 28nm FD-SOI for ePCM NVM (Shan-Lin Liu, Automotive Marketing Manager) As a leader in the automotive market, ST has seen that increased data flows in automotive are driving demand for higher performance and bigger memory in automotive MCUs, said Shan-Lin Liu. ST has taken a unique approach to NVM with embedded PCM (phase change memory) on 28nm FD-SOI. This gives them energy-efficient, high-performance cores with larger NVM memories, and it’s already qualified up to auto grade-0. PCM (vs MRAM) is BEOL. It uses two cells, so it’s more reliable and is good at high temperatures, he said. With FD-SOI, they can go up to 165o, and it’s soldering compliant. The preliminary results of the first MCU chip are excellent. It’s now running in a car, replacing the previous generation 40nm eFlash product.Leti – Advanced FD-SOI for Edge AI (Emmanuel Sabonnadiere, CEO) To fully run artificial intelligence on the edge, research powerhouse Leti is working on an unsupervised learning neural network using advanced FD-SOI and a mix of other technologies. These include embedded non-volatile memory (NVM), 3D integration, and new design tools. Sabonnadière said this new approach is expected to exceed the performance levels of current digital deep learning with neural networks that are capable of handling time-domain signals, sound and speech—and may produce a first "killer app" for advanced SOI. AI will require compact and power-efficient circuits for the inference phase, when neural networks infer things based on new data they receive, close to the end user. The combination of FD-SOI, 3D integration, and NVM opens a path towards dedicated circuits with major performance improvement within the limited power budgets of distributed electronics. In Europe, he noted, privacy concerns are driving the move from the cloud to the edge. On the Leti roadmap, they’ve broken through the 10nm limit for FD-SOI, using strain and body biasing to compensate for transistor mismatch. Also of note: since 2016 Leti has had an ongoing collaboration with SITRI, the Shanghai Industrial μTechnology Research Institute, an international innovation center focused on globally accelerating the innovation and commercialization of More than Moore technologies to power IoT.GlobalFoundries – GF Fab 1 Dresden: Delivering Differentiation with FDX for the Future of Automotive (Thomas Morgenstern, SVP GM Fab 1) Dresden Fab 1, Thomas Morgenstern reminded the audience, is the biggest in Europe, where it is part of the Saxony ecosystem. GF is moving advanced mask-making to Dresden, which is the lead site and Center of Competence for FD-SOI. With the “pivot”, GF is providing platforms. Fab 1 is automotive certified for 22FDX (GF’s 22nm FD-SOI technology), with automotive tapeouts in 2019. “Automotive is a journey,” he said, of continuous improvement, and a mindset: it’s a zero defects culture. The ramp to volume production is well underway, with 26 tapeouts of 22FDX products this year – almost double that of last year. He showed high yield data of about a dozen products, adding that since the beginning of the year every tapeout was first-time right with decreased cycle time. The key specifications for 22FDX with eMRAM for Auto Grade-1 have all been demonstrated, and customer feedback has been excellent.Next: Shanghai International RF-SOI Workshop recap As you can see, it was a packed day for the FD-SOI part of the SOI Consortium’s Shanghai event. In fact the room was still packed at the very end of the day. Several hundred VIPs then headed out for the ever-popular and festive evening riverboat dinner cruise, where the non-stop networking continued.A big shout-out to our sponsors and supporters: VeriSilicon, Simgui, SIMIT, Soitec, Samsung, IBS Ion Implant, ShinEtsu, GlobalFoundries and NXP.The next day of the event was devoted to RF-SOI. That will be the subject of our next post.

The 45th (yes!) IEEE SOI Conference takes place 14-17 October 2019 in San Jose. Now called S3S –since it also covers 3D and subthreshold – it’s a networking event par excellence: a unique opportunity to meet firsthand the movers and shakers in the SOI ecosystem and the giants of R D. As always, it has a strong technical program you won’t want to miss. Plus this year there’s a full-day short course dedicated to FD-SOI design, and half-day tutorial on RF design. Get all the details and registration info at http://s3sconference.org/.The SOI Consortium’s own Executive Co-director Jon Cheek of NXP is one of the keynoters. In fact the consortium membership is extremely present at this event, with over half our member organizations having a hand in it. There’s a plenary talk by GF’s CTO/VP Subramani Kengeri, keynotes by ST Fellow Andreia Cathelin and NXP Fellow Rob Cosaro, and invited talks from Arm, Samsung and Dolphin Design, for example. And this year’s General Chair is Incize CEO Mostafa Emam. Focus Sessions #12 and 13 are all about FDSOI Platforms and Products, with invited speakers from Renesas, NXP, ST, ARM, GF, Huali and Dolphin Design, while focus Session #2 is all about RF-SOI. Here’s the agenda for the FD-SOI Design short course (which takes place on Thursday, 17 October):Short Course Opening and Welcome Philippe Flatresse, Business Development Marketing Director, Dolphin DesignGLOBALFOUNDRIES 22FDXTM Technology and Body Bias Compensation to Enable New Design Optimization Strategies Joerg Winkler, Fellow Design Engineer, GLOBALFOUNDRIESEmbedded Flash Memory Technologies and Applications in Advanced Nodes Memories Koji Nii, Vice President, Global Marketing Sales, Floadia CorporationEnabling the Adaptive Body Bias in Modern IoT Applications Vincent Huard, CTO, Dolphin DesignSoC Design Realization with Adaptive Body Bias Kripa Venkatachalam, IC Design Practice Director, Mentor Graphics Didier Roland, Application Engineers Manager, Mentor GraphicsAnalog Design Techniques for Microprocessors in FD-SOI: Power-Management, PVT Monitoring and Data Conversion Edevaldo Pereira Da Silva Junior, Senior Principal Engineer, NXP Semiconductors MPU/MCU R DLow Power Solutions for SoC Architectures Antonio Pullini, Senior Hardware Designer, GreenWaves TechnologiesSOI to RF Sidina Wane, CEO, eV-technologiesIf you know the way to San Jose, you'll want to be at S3S 2019, for sure!

Since the beginning of the year, there’s been a steady stream of excellent news around Samsung Foundry’s 28FDS, their highly successful 28nm FD-SOI offering. Let’s take a look at what’s been happening, as things do seem to be accelerating. By way of reminder, they announced the industry’s first eMRAM (embedded MagnetoResistive RAM) testchip tape-out milestone on 28FDS in September 2017 (you can read the press release here) - which was just a year after they had announced mass production of 28FDS process technology.At the end of 2018, Arm announced the industry’s first Embedded MRAM (eMRAM) compiler IP built on Samsung Foundry’s 28FDS process technology. Follow that with this announcement at the beginning of 2019: Soitec Expands Collaboration with Samsung Foundry on FD-SOI Wafer Supply. The two companies announced that Samsung had secured a high-volume supply of FD-SOI technology to meet industry's current and future demands especially in consumer, IoT and automotive applications. In March came two more big announcements. First: Samsung Electronics Starts Commercial Shipment of eMRAM Product Based on 28nm FD-SOI Process. As they noted in the PR, “Samsung’s 28FDS-based eMRAM solution offers unprecedented power and speed advantages with lower cost. Since eMRAM does not require an erase cycle before writing data, its writing speed is approximately a thousand times faster than eFlash. Also, eMRAM uses lower voltages than eFlash, and does not consume electric power when in power-off mode, resulting in great power efficiency.”Hard on the heals of that came the news that Arm and Samsung Announce IP Platform including eMRAM for 18nm FD-SOI. At the SOI Consortium’s Silicon Valley Symposium in April, Tim Dry (he’s Samsung’s Director of Foundry Marketing for Edge and End Point), gave a terrific presentation. Entitled Samsung’s FDS with MRAM: Enabling Today’s Innovative Low Power Endpoint Products, it details the company’s FDSOI roadmap for the IoT Endpoint Platform (and yes, you can download in its entirety). Then in May at the big Samsung Foundry Forum in Silicon Valley, Arm, in collaboration with Samsung Foundry, Cadence, and Sondrel, demonstrated the first 28nm FD-SOI eMRAM IoT test chip and development board. The Musca-S1 test chip demonstrates a new choice in SoC design for IoT solutions, said Arm. (Sondrel, btw, is Europe's largest independent IC design consultancy.)In parallel, Cadence announced: Cadence Custom/AMS Flow Certified for Samsung 28nm FD-SOI Process Technology. Especially aimed at digitally-assisted analog designs, what’s new here is that the Cadence custom and analog/mixed-signal IC design flow is now Samsung Foundry certified for 28FDS. Samsung’s 28FDS PDK techfile is Mixed-Signal OpenAccess ready, enabling customers to deploy OpenAccess-integrated, fully interoperable Virtuoso-Innovus implementation flows. For its part, at its Foundry Forum, Samsung unveiled extensions of the company’s FD-SOI (FDS) process and eMRAM together with an expanded set of state-of-the-art package solutions. They indicated that the development of the successor to the 28FDS process, 18FDS, and eMRAM with 1Gb capacity will be finished this year.And finally, companies like NXP are shipping exciting new products fabbed on Samsung’s 28FDS. Ron Martino, VP GM of NXP’s i.MX Application Processor Product Line covered key products in his presentation at the SOI Consortium’s Silicon Valley Symposium (see our coverage here). Among them: the i.MX7ULP for long battery life with 2D 3D graphics for wearables and portables in consumer and industrial applications; the i.MX 8 and 8X subsystems for automotive and industrial applications; and the i.MX RT series of “cross-over” processors. The i.MX RT ULP (real-time, ultra-low-power) series, which Martino says is the “new normal”, deals with a high number of sensor inputs. The i.MX RT 1100 MCUs, which have been qualified for automotive and industrial applications, are breaking the gigahertz performance barrier.In July, linuxgizmos.com reported that, “In June, NXP began volume shipments of its super power-efficient i.MX7 ULP, which it announced in 2017. The SoC is billed as the most power-efficient processor on the market that also includes a 3D GPU. […] the ULP version includes a 3D graphics capable Vivante GC7000.” (Vivante, btw, is a VeriSilicon company, which is an SOI Consortium member and a leading proponent of FD-SOI design and IP in China and worldwide.) This is leading to some really nice wins for NXP. For example, they’ve got Amazon's Alexa Voice Service (AVS) leveraging the i.MX RT crossover processor, enabling developers to quickly and easily add Alexa voice assistant capabilities to their products. The RT series has rapidly been expanded, with versions for voice-controlled devices and offline face and expression recognition capabilities for smart home, commercial and industrial devices.Also announced this summer: NXP and Microsoft Bring Microsoft Azure Sphere Security to the Intelligent Edge with a New Energy-Efficient Processor. That collaboration includes development of a new crossover applications processor in NXP’s i.MX 8 series integrating Microsoft’s Azure Sphere security architecture and Pluton Security Subsystem. Their customers “will be able to harness the high-performance and energy efficiency of NXP’s i.MX 8 applications processors combined with Microsoft’s unequaled security and assurance provided by Azure Sphere certified chips”. As Martino concluded in his presentation, “The future of embedded processing [is] enabled by FD-SOI.” And Samsung Foundry’s FD-SOI offerings are clearly a massive enabler of that future.

The SOI Consortium and member companies had a significant presence at two important events in China recently: the World Semiconductor Congress (WCS) in Nanjing and the SOI Academy, including an FD-SOI Training Day in Shanghai. Nanjing is especially known as a leading RF chip design hub in China, but WCS went well beyond RF. The three-day 2019 event was held at the Nanjing International Expo Center. It attracted over 30,000 visitors, 5000 of whom attended the various summit forums. Presenting at WCS '19 in Nanjing (clockwise from top left): Wayne Dai, CEO/Founder, VeriSilicon; Carlos Mazure, Executive Director, SOI Consortium; Giorgio Cesana, Director, STMicroelectronics; Christophe Tretz, Design Expert, SOI Consortium. (Photos courtesy: WCS)The SOI Consortium organized the SOI Forum, which was part of an afternoon Innovation Summit. Presentations were given by members of the SOI Consortium team, and by leaders from our membership, including Simgui, NXP, Incize, ST, IBM, Cadence and Xpeedic. Some of those presentations are now available from our website -- click here to get them.Earlier in the day, SOI Consortium member VeriSilicon participated in a morning session on AI and IoT Wireless Communications. They presented their low-power Bluetooth design platform for GlobalFoundries 22FDX, and CEO Wayne Dai moderated a lively round-table discussion.Following hard on the heels of the Nanjing event, the SOI Consortium team and members headed to Shanghai for the SOI Academy 2019, hosted for the second year in a row by member SIMIT (Shanghai Institute of Microsystem and IT under the Chinese Academy of Sciences). The two-day event attracted more than 250 professionals from more than 100 domestic and foreign IC companies and research institutes. Keynotes by SOI Consortium Executive Director Carlos Mazure, SITRI CEO Mark Ding and Jean-Eric Michallet, Head of the Microelectronics Components Department at Leti and bizdev director for the SOI Consortium focused on the SOI ecosystem. The SITRI and Leti talks also gave updates on their research and industrialization alliance. Further talks were given by leaders from Soitec, GlobalFoundries, VeriSilicon, IBM and Xpeedic. These addressed the growing FD-SOI ecosystem, applications in automotive electronics, 22 nm and 10 nm FD-SOI devices, advanced SOI substrate technology, China’s FD-SOI development, the FD-SOI manufacturing process, product design, EDA tools and all aspects of industry’s software and modeling value chain.Several speakers noted that more and more local Chinese customers are actively adopting FD-SOI for low-power, high-performance chips. SOI Academy, Shanghai, 2019, FD-SOI Training Day attendees.(Photo credit: SIMIT)The second day was devoted to hands-on professional training, given by experts from Leti using an actual PDK and punctuated by in-depth discussions. This helped the IC designers to fully understand the advantages and flexibility of FD-SOI in low-power logic, analog/mixed-signal and RF. All in all, “It was a great success,” concluded Jean-Eric MICHALLET, Head of the Microelectronics Components Department at Leti and bizdev director for the SOI Consortium. Plans for the next SOI Academy are already underway, with plans to extend the topics to include more on photonics, RF, power and MEMS.

Why FD-SOI? What can you do with it that you couldn’t do before? That was the big question from IHS Markit’s Matthew Short that kicked off the first panel discussion at the SOI Consortium’s Silicon Valley Symposium. And there were some great answers.VeriSilicon, Analog Bits and Silicon Catalyst were among the consortium members with stands at the SOI Symposium, Silicon Valley 2019.Here in this final part of our coverage of the event, we’ll detail who said what in the two panel discussions, as well as the presentations by Leti, Intento Design the SOI Consortium’s IP/EDA roundup.If you missed the previous two installments of our coverage, you can catch up on the rest of the presentations in part 1 (NXP, Samsung more) here and part 2 here (Synaptics, GlobalFoundries more). Almost all of the presentations are now freely available under "events" on the consortium website - or just click here to get them.How FD-SOI Changes What You Can DoThe presentation by Matthew Short, Sr. Director of IoT Technology at IHS Markit, was not specific to SOI, but it sure did lay out out the market opportunities. Entitled IoT, 5G, ADAS and AI Market, it’s available on our website. Matt spent most of his career in chip design at NXP/Freescale, so he really has an engineer’s perspective on where this all is going. At IHS Markit, they define IoT as anything with an IP address. Over the past year more than 10 billion devices were shipped, and there were more “things” than cellular handsets, so the world has really changed. He outlined the growth drivers, suggested that 5G won’t be a “wow” thing for consumers, and noted there is a lot of debate raging regarding how smart sensors should be (the Tier 1’s want smart).He was then joined on the stage by the participants in the first panel discussion, which looked at product and application drivers. That included: NXP Fellow Rob Cosaro; Tim Dry, Director of Edge Endpoints Marketing at Samsung Foundry; ST biz dev director Roger Forchhammer; CoreAVI biz dev VP Lee Melatti; Nokia VP Michael Reiha; and Analog Bits EVP Mahesh Tirupattur.First Short asked why customers wanted more integrated solutions. For CoreAvi, it’s about safety, for ST in automotive it’s about security, for Analog Bits, it’s about integrating more analog, for Nokia it’s just a necessity.Then he asked Why FD-SOI? What can you do that you couldn’t do before? For ST, which is doing MCUs for automotive, it’s about energy efficiency, speed, the density of non-volatile memory and the robustness of the technology. For NXP, it’s back biasing, low voltage and power numbers never seen before. “FD-SOI really makes a difference in the products we can bring to market,” said Cosaro. For CoreAVI, it’s the long-term power impact. And for Analog Bits, “Customers see huge benefits,” said Tirupattur, for cost sensitive applications. He has customers selling their technology in high volumes in FD-SOI. What about edge vs. cloud? For Nokia, it’s monolithic integration for best-in-class RF, advanced memory, biasing and voltage regulation adding a layer of intelligence. Samsung sees edge as distributed cloud, and CoreAVI sees safety in the edge, because you can’t completely rely on the cloud.Where are the weak points in the FD-SOI ecosystem? For Samsung, more people need to use back biasing. “People need to use the knobs,” said Dry. For Analog Bits, the next step is innovation around back biasing, as many in logic don’t understand the benefits, so the ecosystem needs to promote the value proposition. ST suggests that with more products out there, customers will see the benefits. NXP did “a lot of the heavy lifting” at 28nm – now you need more people using these nodes, not just the cellphone nodes.How will the architecture change? For NXP, it’s all about memory bandwidth. For Samsung, it’s the promise of analog and interconnect. Nokia sees the back-end and heterogeneous integration with FD-SOI and RF enablement. Analog Bits’ Tirupattur said he’s pushing his engineers for even lower power in a still smaller form factor, noting that most analog engineers had been more focused on performance than power, but now that’s changed. For ST, it’s AI/ML throughout automotive, and FD-SOI is beneficial there.Leti the Connected Car Leti's slide 27, SOI Symposium, Silicon Valley 2019Research giant Leti’s presentation was entitled Applications Around the Connected Car. 85% of Leti’s €315M budget comes from R D contracts with its 350 industrial partners. Truly a driving force in FD-SOI, Leti is involved in a dizzying array of projects. For the connected car, they cover (much of it on SOI): high precision smart sensing, embedded processing fusion, new computing paradigms and deep learning, ultra-low power computing nodes framework, ultra-low power connectivity for IoT, energy management and scavenging, and security. They do vision at the edge, 3D technology for smart imagers, and ways to dramatically reduce power. They’ve got a Qbits platform on FD-SOI for AI at the edge, a super low power neural network accelerator, and ULP connectivity. Check out the presentation for lots of details.EDA/IP OverviewSlide 9 from SOI EDA/IP Overview.SOI Consortium Executive Co-Director Jon Cheek gave a quick round-up presentation aggregating various IP and EDA offerings entitled , SOI EDA/IP Overview. It is taken from recent member presentations including Cadence, Silvaco, VeriSilicon, Synopsys and GlobalFoundries, giving you an idea of how dynamic the ecosystem has become.Automating Analog While the logic side of the design equation has long had robust automation tools, some consider the analog side as sort of black magic. New consortium member Intento Design aims to fix that. Here at ASN we covered their work with ST briefly a few months ago here. At the SOI Symposium, the company’s CEO Dr. Ramy ISKANDER presented their solution in ID-XploreTM: A Disruptive EDA for Emerging FDSOI Applications. Intento, a partner in GlobalFoundries FDXcelerator program, has cognitive software for first-time right analog design. It determines the appropriate static and dynamic body biasing ranges to meet PVTB (Process/Voltage/Temperature/Body Bias), and is fully integrated into the Cadence Environment. They produced multiple correct-by-construction FD-SOI designs, and the total time spent to generate eight candidates FD-SOI designs took less than a day. The Tools Are in the BoxThe last panel discussion, entitled Are the Tools in the Box? was moderated by the Consortium’s Jon Cheek. Participants included: VeriSilicon SVP David Jarmon; Arm PDG Marketing VP Kelvin Low; NXP’s Stefano Pietri, Technical Director of the company’s Microcontrollers Analog Design Team; Jamie Schaeffer, who’s GF’s Sr. Product Offering Manager for 22FDX and 12FDX; and Cadence Strategic Alliances Director Jonathan Smith. 2nd panel discussion, SOI Symposium, Silicon Valley 2019Yes, the tools are in the box. Smith of Cadence said they’re providing them, and NXP’s Pietro said that they’re very well positioned in his specialty, analog. VeriSilicon has IP, and anything they don’t have in house they’ll license. So why be afraid of body biasing? NXP has proof by example – they see such huge cost advantages that they try to leverage it as much as possible. GF’s doing training, since each area (automotive, IoT, etc.) has different needs. Some VeriSilicon customers already see such substantial benefits from FD-SOI that they’re not bothering to do biasing. Cadence points out that the Arm POP announcement is huge, and Arm’s Low wondered if the SOI Consortium could do an IP portal? “Our sales departments need to explain the advantages to our customers!” said NXP’s Pietro.From the audience, NXP VP longtime FD-SOI proponent Ron Martino (who, btw, wrote some great articles for ASN when they first got into FD-SOI – read them here), asked why designers think FD-SOI means a lot of corners? How do we convince the industry that FD-SOI simplifies design? Cadence is working with GF, responded Smith, and will have some big new at Arm’s TechCon this fall. “We need more training and marketing to show it’s not scary," he added. For GF, the corners don’t get more complicated, and they’re working with Dolphin Integration on getting them covered early in the planning. Ease of access to IP will help, per Arm. And in a great concluding remark, VeriSilicon’s Jarmon said, “The craft is being automated. The more we work together, the greater success of FD-SOI.”

Join us! In partnership with our members, the SOI Consortium is co-organizing and participating in two key SOI events coming up in China over the next few weeks. On May 18th, we’ve put together an SOI Forum at the World Semiconductor Congress (WCS) in Nanjing. And on May 23rd 24th, we’ve teamed up with our members SIMIT, Sitri and Leti for another in our series of SOI Academies, including an FD-SOI Training Day. (The last one this past winter was a terrific success – read about that here if you missed our coverage at the time.) QR code for WCS, Nanjing '19At WCS, the SOI Forum (sub-forum #8) is part of the afternoon Innovation Summit. We’ll cover the broader SOI ecosystem, including both RF-SOI and FD-SOI – from wafers to design through manufacturing. Presentations will be given by members of the SOI Consortium team, and by leaders from our membership, including Simgui, NXP, Incize, ST, IBM, Cadence and Xpeedic. Click here or scan the QR code for the full program and registration information. Also at WCS, SOI Consortium member VeriSilicon will be participating in a morning session on AI and IoT Wireless Communications (sub-forum #4). They’ll be giving a presentation on their low-power Bluetooth design platform for GlobalFoundries 22FDX, and their CEO Wayne Dai will be moderating a round-table discussion. You can get more information on that (in Chinese only, tho) here, or follow VeriSilicon on WeChat. QR code for SOI Academy and FD-SOI Training, Shanghaid 2019The SOI Academy in Shanghai is an opportunity for experienced designers to gain solid expertise in FD-SOI. The event begins in the afternoon of May 23rd with a series of informative plenary talks by members of the SOI Consortium team, and by experts from our members Leti, Soitec, VeriSilicon, GlobalFoundries and NXP. The FD-SOI Training starts the next morning, on May 24th.. This is a hands-on event lead by top experts from Leti. The morning is devoted to digital design in FD-SOI, and the afternoon to RF design (including for 5G) in FD-SOI. Attendees will get a comprehensive understanding of design techniques for low-power chips leveraging the multiple benefits and flexibility of FD-SOI technology. Get more information here, or from the WeChat QR code.We've got a busy schedule! To keep up to date with where we and our members will be promoting the SOI ecosystem, be sure to check our Events page regularly.

For the second consecutive year the SOI Consortium will have a stand at the Networking Reception during the Samsung Foundry Forum (SFF). This important Silicon Valley event will be held on May 14, 2019 at the Santa Clara Marriott. We hope you'll stop by to learn more about the SOI Consortium and the FD-SOI ecosystem. There’s been a steady stream of news about Samsung’s FD-SOI offerings and support, including their highly successful 28FDS and coming very soon: 18FDS. (If you need to catch up, click here to read more.) As in the previous 3 years, Samsung will be making major announcements on their technology roadmap and application solutions. SFF is a unique opportunity to network with Korean and US based executives from Samsung Foundry as well as customers and ecosystem partners. SOI Consortium members ARM, Synopsys, Cadence, Analog Bits, VeriSilicon and Xpeedic will also have stands, and NXP will be on the customer panel.Seats are limited, so go to http://www.samsungfoundryforum.com/2019/ to register now.

Takeaway #1: As NXP VP Ron Martino noted in his opening keynote at the recent SOI Symposium in San Jose, FD-SOI is the technology platform for enabling edge computing, and ultra-low power is the sweet spot. Organized by the SOI Consortium with support from our members, the recent SOI Symposium in Silicon Valley was an enormous success. Close to 300 decision makers signed up – more than double what we saw just a couple years ago. Attendees spanned the ecosystem: from end-users to design to foundries and right up to the investment community. The presentations and panel discussions were absolutely terrific, and almost all are now freely available - click here to get them.The focus was heavily on FD-SOI this time, but some very interesting RF-SOI talks were given as well. This was a day packed with presentations by players from across the SOI ecosystem. In this post, we’ll only cover a few. But the others will follow quickly, so watch this page. And now without further ado, let’s dive in.NXP: In the Sweet SpotNXP VP Ron Martino presenting at the 2019 SOI Symposium in San Jose.NXP is designing FD-SOI into many new products, said Martino, GM of the i.MX Processor Application Product Line. There’s a new wave of products – generically you could call them IoT but in fact they’re found throughout the industry. It’s about interacting with the cloud, so edge processing is critical. His presentation, Embedded Processors for Future Applications, is now freely available for downloading from our website.The new i.MX7ULP is a great example of ULP in the sweet spot. From a design standpoint, it leverages IP, power optimization, and what he described as “starter biasing”. That gets them the long battery life with 2D 3D graphics they need for wearables and portables in consumer and industrial applications.NXP slide 10, SOI Symposium, San Jose '19 (Courtesy: NXP)Having deepened their expertise in biasing, NXP has now moved on to “advanced biasing” for the next generation of products. For example, the i.MX RT ULP (real-time, ultra-low-power) series are “cross-over” processors, which Martino says are the “new normal”. They deal with a high number of sensor inputs. The i.MX RT 1100 MCUs, which have been qualified for automotive and industrial applications, are breaking the gigahertz performance barrier with a low-power, 28nm FD-SOI process.Another new product leveraging advanced biasing is the i.MX RT 600. They’ve done hardware acceleration on specific functions and optimized around visionand voice integration at low cost and power.As shown at Embedded World '19, automotive app for NXP'x i.MX 8, which is on 28nm FD-SOI. (Courtesy: NXP)Likewise for the i.MX 8 and 8X subsystems for automotive and industrial applications. At Embedded World, they showed it driving advanced OLED screens, cameras (for parking, for example), V2X, audio, user monitoring (like driver pupil tracking), and integration into the windshield in a heads-up system. This is the high end of the capability of 28nm FD-SOI, he said. It’s a 6 CPU core system with multiple operating systems, about which he said: “It’s the dashboard...it’s amazing.”BTW, in another presentation, CoreAVI, which builds avionics, automotive and industrial products on NXP’s i.MX 8, addressed safety. You can get that here.FD-SOI enables a scalable solution for real-time and general compute with the lowest leakage memory, the best dynamic and static power, Martino concluded. NXP’s leadership in body biasing is enabling edge compute, and we can expect to see more content coming soon.In another NXP presentation later in the day, Stefano Pietri, Technical Director of the company’s Microcontrollers Analog Design Team caught a lot of people’s attention. A wave of cameras went up to capture each of his slides in Analog Techniques for Low Power, High Performance MPU in FD-SOI – but you can get the whole thing now from our website. It’s a very technical presentation, in which he details the many ways FD-SOI makes the analog team’s job easier, enabling them to get performance not available from bulk technologies. They developed a lot of in-house expertise and IP (see slide 16 for a catalog of the IP).Samsung: Enabling LP Endpoint ProductsTim Dry, Samsung Foundry Director of Edge Endpoint, SOI Symposium, San Jose '19Tim Dry, Director of Foundry Marketing: Edge and End Point presented Samsung’s FDS with MRAM: Enabling Today’s Innovative Low Power Endpoint Products. In a telling first, Samsung has made this presentation available on our website.FD-SOI covers the wide range of requirements for intelligent IoT, he explained: from high to low processing loads; and active to dormant processing duty cycles. That includes chips that will last for ten years, and need to be able to wake up fast and kick right into high performance. These products are 50% analog, and packaging is part of the solution (especially for the RF component).Samsung has been shipping 28nm FD-SOI (which they call 28FDS) since 2015, first in IoT/wearables, then in automotive/industrial and consumer. Yields are fully mature. In March 2019, they announced mass production of eMRAM on 28FDS. It’s a BEOL process, adding only 3 masks. It cuts chip-level power by 65% and RF power by 76% over 40nm bulk with external memory. Beyond the fact that it's 1000x faster than eFlash, eMRAM also has other advantages that make it especially good for over-the-air updates, for example.Samsung Foundry FD-SOI IP slide, SOI Symposium, San Jose '19 (Source: Samsung Foundry Keynote at SOI Symposium 2019, USA)Samsung also has RF and 5G mmWave products shipping in 28FDS. The company has a fantastic ecosystem of partners helping here, said Dry. In AI at the endpoint, they’re shipping IoT products for video surveillance cameras: some are high speed, but some are also low speed – it depends on the detection use case. And most importantly for the design ecosystem, the IP is all ready.Next up for Samsung is 18FDS, which will ship this year with RF, then in 2020 with eMRAM. 18FDS, Dry said, is optimized for power reduction. Compared to 28FDS, it’s got 55% lower power consumption, 25% less area and 17% better performance at the same power. You’ll hear more about it as well as their design services if you’re at the Samsung Foundry Forum in May (registration info here).ARM’s Biased ViewsKelvin Low, VP of Marketing for Arm’s Physical Design Group (PDG) gave a presentation entitled Biased Views on the Industry’s Broadest FDSOI Physical IP Solution. By way of background, Arm and Samsung Foundry recently announced a comprehensive, foundry-sponsored physical IP platform, including an eMRAM compiler for 18FDS. In case you missed it, at the time Arm Senior Product Marketing Manager Umang Doshi described the offering in an Arm Community / Developer physical IP blog, which Arm graciously agreed to share with ASN readers. Slide 9 from Arm's presentation, Silicon Valley SOI Symposium 2019.At the SOI Symposium, Low emphasized to the audience that Arm now has the broadest range of FD-SOI + IP solutions. It addresses mobile, consumer, IoT, automotive and AI/ML. There are 18FDS POP (processor optimized pipe) packages for Arm Cortex-A55, Cortex-R52 and Cortex-M33 processors. IP integrates biasing and a number of standard PVTs (corners). And since the Samsung platform is foundry-sponsored, it’s free.Slides 6 and 11 from Arm's presentation, Silicon Valley SOI Symposium 2019. The goal of POP IP is to enable partners to implement and tapeout Arm cores with the fastest turn-around time and best-in-class PPA while maximizing the benefits of process technology.Arm did a test chip with eMRAM, which they’ve just gotten back. It’s functional (some details are available in slide 14 of their presentation), and the company is now preparing a demo board that they’ll be showing shortly. Watch this page!That's all for this post. The next post -- part 2, covering presentations by Synaptics, GlobalFoundries, STMicroelectronics, Dolphin Integration and Anokiwave -- is now available. Click here to read on.

There were over 220 participants at the recent SOI Academy FD-SOI Training event organized in Shanghai. The event extended over two days, with the first day covering a basic introduction to the technology as well as the ecosystem worldwide and in China. The second day was hands-on professional training. Attendees got a comprehensive understanding of how to leverage the benefits and flexibility of FD-SOI design techniques for low-power chips including logic, mixed-signal/RF and analog blocks. They had a great line-up of experts from whom to learn – check out the agenda here. There was also a follow-up press release (in Chinese) from SITRI here. There will be more of these SOI Academy events in cities across China in the year to come – we'll keep you posted (and of course, keep checking back for news on the Consortium's Events page). [caption id="attachment_12981" align="aligncenter" width="1000"] SOI Academy '18 keynotes by: Dr. Mark Ding, CEO, SITRI; Dr. Carlos Mazure, EVP Soitec and Chairman/Executive Director SOI Consortium. Dr. Julien Arcamone, EVP Leti. (Images courtesy: SITRI). Lower right: the hands-on FD-SOI training.[/caption] The two-day seminar and hands-on FD-SOI design training was (superbly!) co-organized by SITRI and Leti, with the support of the SOI Industry Consortium at the Jiading SIMIT campus outside of Shanghai. Just to put this in perspective, SIMIT and SITRI are absolutely key players in China's chip ecosystem. SIMIT is the Shanghai Institute of Microsystem and Information Technology, one of the most venerable institutes in the Chinese Academy of Science (CAS) and one of the world's earliest pioneers in SOI. SITRI is the Shanghai Industrial μTechnology Research Institute, an international innovation center focused on globally accelerating innovation and commercialization of More-than-Moore for IoT. Both institutions are under the aegis of Dr. Xi Wang, Chairman of SITRI, Director General of SIMIT, Academician of CAS, and champion of all things SOI in China. At this Shanghai event, the participants came from industry (including big companies, SMEs and startups) and technical institutions. In fact as well as attendees from Shanghai people voyaged from other cities such as Shenzhen and Chengdu. The designers participating to the FD-SOI training day were all experienced in design and highly motivated in learning FD-SOI design, notes Carlos Mazure, Chairman Executive Director of the SOI Industry Consortium, and Executive VP of Soitec. “This made it possible to dive into the specificities of FD-SOI,” he said, adding that, “The focus on RF was very timely.” Day 1: Intro to FD-SOI The first afternoon opening keynotes were made by SITRI CEO Dr. Mark Ding and Leti EVP Dr. Julien Arcamone. These were followed by overview talks by execs from Soitec, Verisilicon and GlobalFoundries. After a lively networking break, three talks delved into FD-SOI technology. The first was by Professor Sorin Cristoloveanu, Laureate of the IEEE Andrew Grove Award and Director at the CNRS (the French National Center for Scientific Research – the largest governmental research organization in France and the largest fundamental science agency in Europe). He covered device physics and characterization techniques. This was followed by talks on the technology by Soitec Fellow Bich-Yen Nguygen, and by Dr. Christophe Tretz, IBM Sr. Engineer on product design methodology. The day ended with a dinner, where Professor Cristoloveanu says enthusiastic technical discussions continued unabated (and continued even further in follow-up emails), lots of business cards were exchanged, and opportunities for further education were explored. Day 2: Hands-on Training The second day, designers got hands-on training from Leti experts using FD-SOI PDKs, first in the morning on digital, then in the afternoon on RF. Everyone loved the lively discussion and in-depth exchanges between the experts and the designers. They agreed that FD-SOI has important applications and differentiated competitive advantages for IoT, 5G, automotive, AI and other fields. At the end of the training, Leti and SITRI jointly issued SOI Academy certificates of completion to the designers. Feedback from participants was very good. Some asked for further education and for hands-on testimonials from companies that are already designing and manufacturing products on FD-SOI. “The participants were focused, motivated, involved, with good knowledge, which helped make the three hours of Digital training effective,” said Dr. Alexandre Valentian, Leti Sr. Expert, Digital Design. “The IT team was very helpful in setting up the training, the students accounts and the hardware infrastructure.” “The training on Basics of FD-SOI RF circuit was a great success thanks to the efficiency of our Chinese partners and also thanks to the enthusiasm and the good level of our trainees. As senior Expert of CEA Leti I was really impressed by the professionalism of the organization team. For all these reasons, I’m very glad to have had the opportunity to contribute to the 2018 SOI Academy,” said Dr. Baudouin Martineau, Leti Sr. Expert, RFIC Design Technologies. “The professionalism, efficiency and enthusiasm of our Chinese partners and the level and technical relevance of all trainees made the training on Basics of FD-SOI RF circuit a great success and fruitful experience,” added Frédéric Hameau, Sr. RF Research Engineer, Leti Project Leader, Architecture, IC Design Embedded Software Division, RF Architectures and ICs Laboratory. “It was a pleasure to get the opportunity to be part of this first edition of SOI academy 2018.” The organizers would like to thank the sponsors, including: the SOI Consortium and its members Soitec, VeriSilicon, GlobalFoundries, Simgui and Cadence, as well as Mentor, ProPlus and other companies and institutions in China and worldwide. Dr. Mazure notes that special recognition must go to Dr. Julien Arcamone, EVP, Leti-CEA and to Qing Wang-Bousquet, SITRI representative, for the perfect and smooth organization, and to the Leti instructors, who are international experts and highly committed. “As one of the main initiators and organizers of the 2018 SOI Academy, I wanted to personally thank all of you for your respective contribution to this first edition of the SOI Academy,” concludes Dr. Arcamone. “Undoubtedly, it was a great success, very well organized and fluid and we can be proud of that.”