low-power

VeriSilicon provides platform-based, all-round, one-stop custom silicon services and semiconductor IP. For two years running, they’ve been the #1 Chinese IP provider and well into the Top 10 worldwide (per IPnest 2020). They’re also an FD-SOI design powerhouse. Founded in 2001, VeriSilicon first began work on FD-SOI in 2013. Now they’re headed for listing on the Shanghai STAR exchange. SOI News talked to President CEO Dr. Wayne Wei-Ming Dai about his company’s innovative business model, and opportunities for FD-SOI.SOI News (SN): You call the VeriSilicon business model “SiPaaS”, for Silicon Platform as a Service. Can you tell us what that means? Is it particularly well-suited to designs based on FD-SOI? Dr. Wayne Wei-Ming Dai (WD): We see SiPaaS as the third transformation in the semiconductor industry. If you take a minute to look at the evolution, first was the IDM model of the 1960’s and 70’s, largely based in the US and Japan and driven first by the US military, then home appliances and consumer electronics. The second transformation was the foundry model, driven heavily by the PC and cellular communication, with a geographic center heavily based in Taiwan and Korea. That solved the CAPEX challenge. Now with the IoT, we solve the OPEX – operational expenses – challenge. Although 60% of our business comes from outside China, we do see particularly good opportunities for China. With AI and AIoT, there’s a lot of custom designs. You have a new model with the chip as a system, with lots of IP – but it also is much more expensive. The VeriSilicon SiPaaS model covers everything from IP to final tape-out, delivers packaged and tested parts, and that accelerates time to market and saves money. If you consider the share of R D expenses as a percentage of chip revenue, for leading fabless companies, they can be 20-30%, and you need to have a gross margin of 50% and higher. But if your gross margin is 40% or below, you might out of business. The VeriSilicon model seeks to transform the design-heavy model, where designers use their own IP, to the next wave, which is design-lite. When you’ve got a design-lite model for A/IoT, you don’t need such a big team. This is the third transformation. You first saw this starting in a major way in Israel, where going to design-lite enabled fabless companies to move very quickly. But you still need IPs, and for those working under a traditional model, we have those. In SiPaaS, we offer IP platforms. Chip design is kind of like building a house. If you want, we can just give you the kitchen – so that’s some specific IP. But we can also give you the entire house. The IPs form the solutions. For each type of application, there are similar IPs that need to be integrated. Sets of IPs form subsystems for IoT, automotive, medical, wearables, audio, video, etc. There are no boundaries on the platforms, but each have typical elements. In this industrial transformation, and now especially for AIoT, you’ll need many more chips in many different places. We have a lot of IP that we created organically, but we also made some major acquisitions over the years. For example, 13 years ago we bought a Dallas based DSP division from LSI Logic. Our design-lite platform approach plays particularly well in FD-SOI, where designers want to maximize the advantages of the technology. Remember that much of the original IP for FD-SOI comes from ST or Samsung. When Samsung first licensed 28nm FD-SOI from ST, we got a whole set of 28nm FD-SOI IP from ST with modification rights. So we started to play with them. Then that IP went to Synopsys. We have modified, optimized and customized it for customers. And with GlobalFoundries’ 22nm FD-SOI, when the IP comes out, we're the first ones invited to test it. So we focus on those IPs. We do benchmarks on ARM and others. And we’ve designed our own IPs for RF and more. We’ve done the body biasing circuits and software control, so we support design methodologies. People often ask us to show them how good FD-SOI is. So we do a lot of benchmarking. At 28 bulk, we can do apple-to-apple comparisons. And 28 bulk or 22 FD-SOI, it’s the same team, so we can do those comparisons, so they can compare the two nodes. And we’re partnering with more 3rd party IP companies – including smaller players – providing FD-SOI IP, which is great. [bctt tweet="Our design-lite platform approach plays particularly well in #FDSOI, where designers want to maximize the advantages of the technology - @VeriSilicon CEO Wayne Dai #IoT #edgeAI #wearables" username="SOIConsortium"] SN: You have been a very vocal champion of FD-SOI. Why? WD: We’re not against FinFET – that a really big part of our business and we’re very advanced in it. We were the first to do a tape-out on Samsung’s 7nm UV FinFET test chip and are working on 5nm. While overall we tape out over 30-50 chips a year, we are foundry neutral. But we recognize that FinFETs are not for everything: there are some things that FD-SOI does much better. Integrating RF, for example – it’s not impossible but it’s not natural in FinFET. Yes, if you’ve got a big digital chip running at high speed most of time, FinFET is better. But if you’re running high speed some of time, say around 20%, especially integrating RF, FD-SOI is better. And back biasing is impossible in FinFET. In the end, we “walk on two legs”. SN: What do designers need to know about FD-SOI? WD: Body biasing can sound complicated, but the thing is, you don't play with each transistor. In theory, you can control each transistor with body bias, but in reality, you do it region by region. With body biasing, you can dynamically make different parts of the chip behave differently. This is key. Some parts are reverse biased. Some parts are forward biased. You play with this block by block, and kick it in as-needed by software after the chip comes back. So in IoT, for example, where it's very serious low power, you may want to shut down certain parts when you're not using them, while other parts always need to be on. If you choose one of our platforms, we’ve taken care of that. There may be parts you only need to bring up and run at high-speed for certain tasks. So body biasing gives you all sorts of controls. With FinFETs you can't do that, you can just play with voltage scaling. You can drive up the speed – the dynamic power – when needed with forward biasing. During that time, you're not really worrying about leakage power because when the task is done you can completely shut down those parts again. It also changes tape out. Typically designers do worst case. But you might not need to design for the worst case: you leave too much on the table. With body biasing, if you solve for typical, when the chip comes back, you can tune and make adjustments post-silicon. So you can do an aggressive tape-out, which is much more effective than starting off with a worst case. True, if you sign off worst case, your chip can always run very fast, but sometimes you don't need that. And in order to solve for worst-case, you put in a lot of buffers or whatever for timing closure, which is unnecessary effort. What's more, for different applications, the worst case can be different: some applications may need some higher speeds and sometimes less. If you solve for typical, then depending on the application you can software-tune the device. In the past, you never had that kind of thing. With body biasing in FD-SOI, you can solve for typical, so you can save a lot of area and a lot of design cycle in terms of timing closure, in terms of use of buffers. If silicon comes back, and it's missing something – say you need it to go a little faster – I’ve done body biasing, so I adjust the timing. Most times it's probably ok, it's good enough. Of course, some applications you need some combination of fast and slow, and you can leverage the body-biasing post silicon to change what's fast and what's slow on the fly. Like in wearables, power is very critical – some parts are always on, and some parts are sometimes on. For the parts that are always on, you need to reduce the leakage, and you do that with reverse body biasing. For other parts, you bring them up and you run as fast as you can for a short period of time – in this case leakage isn't as important because most of the time it's shut down. But dynamic power is important. High performance is important. For that part you need forward biasing. With different parts of the chip, you can play with different things. Before, you had to do this before tape-out, and sometimes had to do worst-case, which should never happen: you leave too much margin on the table, because after silicon you couldn’t do anything. But now with body biasing in FD-SOI, you have the capability – you don't need to do worst case – if needed you can always adjust. And for different applications in the chip, you might need a different kind of operating frequency, right? So you can create different chips from the same chip. With body biasing, you can always tune to whatever you want. If I’m short of something, I can do some body biasing bring up the speed. Now that's different from voltage scaling. You cannot dynamically achieve voltage scaling. You might have two voltages – one's high, one's low. But you cannot continuously change. In FD-SOI the same die maybe has different applications with different performance requirements, so we don't need to do worst case design. They can come up with different performance chips in the same silicon. SN: What do you see as the drivers? WD: IoT, AIoT and automotive. Also RF, mmWave and connectivity. And at the edge, where you need very low power. FinFET and FD-SOI both solve the leakage problem. But if you need sleep mode most of the time and high performance 20% of the time, it is more energy efficient to use FD-SOI. There are a lot of applications in this category. In 12nm FD-SOI, you’ll reach almost the same performance as 7nm FinFET at 14nm cost. [bctt tweet="#FinFET #FDSOI both solve the leakage problem. But if you need sleep mode most of the time and high performance 20% of the time, it is more energy efficient to use FD-SOI /@VeriSilicon CEO #edgecomputing" username="soiconsortium"] You’ve seen some stagnation of IoT at the 40/55nm process nodes because at those nodes the performance was not as good as expected. You needed two AA batteries. The value of the IoT data was not generated, collected or analyzed. What you need is AI at the edge to pre-process the raw data so you lower network capacity requirements. AI at the edge is a great opportunity for FD-SOI. SN: How do you see the role of the SOI Consortium? WD: We work with the consortium for these big forums; in particular VeriSilicon co-founded and has now co-sponsored the Shanghai FD-SOI Forum for seven years. They’re the most visible and high quality. The consortium knows the people that need to know each other. There are a lot of meetings during these events, and a lot of deals are sealed; one signature event is the river dinner cruise where “everyone is on the same boat”. ~ ~ ~ Related VeriSilicon press releases: VeriSilicon Releases Most Advanced FD-SOI Design IP Platform on GlobalFoundries 22FDX for Edge AI and IoT Applications (2019-10-24). The VeriSilicon 22FDX IP Platform includes over 30 low-power, low-leakage and high-density memory compiler IPs and various key mixed signal IPs. VeriSilicon provides a one-stop silicon design service to customers designing for AIoT with mature IPs to shorten custom design cycles and reduce their R D costs. FD-SOI Body-Bias technology allows the user to adjust device threshold even after silicon is manufactured: it can enable dynamic tuning between High-Performance and Low-Power, and enhance the design flexibility without extra cost. Advanced ATSC 3.0 Chip Launched for Mobile and Broadcast Applications (2019-01-08). The demodulator SoC was designed and developed by Saankhya Labs with ASIC turnkey design and manufacturing services from VeriSilicon, using Samsung Foundry’s state of the art 28FDS (its Fully Depleted SOI process technology), chosen for its unique low power capabilities offered by the back bias option. (See more in-depth coverage on this announcement from SOI News here.) VeriSilicon Announces Ultra Low Power BLE 5.0 RF IP based on GLOBALFOUNDRIES 22FDX FD-SOI Process for IoT Applications (2018-11-01). The IP includes a transceiver that is compliant with the BLE 5.0 specification and supports GFSK modulation and demodulation. The silicon measurement shows that the sensitivity can be tested up to -98dBm with less than 7mW power dissipation in typical conditions. It largely improves battery life for low power IoT applications. In addition, the RF transceiver saves 40% area compared to a similar implementation on 55nm bulk CMOS. Besides the RF transceiver, this IP integrates on-chip balun, TX/RX switch and 32K RC OSC driver to save the BOM. Moreover, high efficiency DC/DC and LDOs are also available for power management. “Wearable and IoT markets especially the wireless earplug market are growing rapidly, and it will surge through consumer use, hearing aids, personal care and other industrial applications.” said Dr. Wayne Dai, Founder, Chairman, President and CEO of VeriSilicon. “By taking advantage of integrated RF capabilities of FD-SOI, in particular GF’s 22FDX, our BLE 5.0 RF IP will significantly reduce the system cost and greatly boost the growth momentum of wearable products such as wireless earplugs.” GlobalFoundries and VeriSilicon to Enable Single-Chip Solution for Next-Gen IoT Networks (2017-07-13). The integrated solution leverages GF's 22FDX technology to decrease power, area, and cost for NB-IoT and LTE-M applications. VeriSilicon's Artificial Intelligence Engine Delivers Multi-Sensory Experiences in NXP's i.MX 8 Flagship Applications Processor. (2017-06-08).

GlobalFoundries and Dolphin Integration are collaborating on the development of a series of adaptive body bias (ABB) solutions to improve the energy efficiency and reliability of SoCs on GF’s 22nm FD-SOI (22FDX®) process technology for a wide range of high-growth applications such as 5G, IoT and automotive. The goal of the IP is to accelerate energy-efficient SoC designs and push the boundaries of single-chip integration. The design kits with turnkey ABB solutions will be available starting in Q2 2019. As part of the collaboration, Dolphin and GF are working together to develop a series of off-the-shelf ABB solutions for accelerating and easing body bias* implementation on SoC designs. ABB is a unique feature of FD-SOI that enables designers to leverage forward and reverse body bias techniques to dynamically compensate for process, supply voltage, temperature (PVT) variations and aging effects to achieve additional performance, power, area and cost improvements beyond those from scaling alone. The ABB solutions in development by GF and Dolphin consist of self-contained IPs embedding the body bias voltage regulation, PVT and aging monitors and control loop as well as complete design methodologies to fully leverage the benefits of corner tightening. GF says its 22FDX technology offers the industry’s lowest static and dynamic power consumption. With automated transistor body biasing adjustment, Dolphin Integration can achieve up to 7x energy efficiency with power supply as low as 0.4V on 22FDX designs. “We have been working with GF for more than two years on advanced and configurable power management IPs for low power and energy efficient applications,” said Philippe Berger, CEO of Dolphin Integration. “Through our ongoing collaboration with GF, we are focused on creating turnkey IP solutions that allow designers to realize the full benefit of FD-SOI for any SoC design in 22FDX.” “In order to simplify our client designs and shorten their time-to-market, GF and our ecosystem partners are helping to pave the way to future performance standards in 5G, IoT and automotive,” said Mark Ireland, vice president of ecosystem partnerships at GF. “With the support of silicon IP providers like Dolphin Integration, new power, performance and reliability design infrastructures will be available to customers to fully leverage the benefits of GF’s 22FDX technology.” As STMicroelectronics Fellow and Professor Andreia Cathelin has beautifully noted, “Body biasing is not an obligation. It’s an opportunity.” And GF/Dolphin clearly aim to make that opportunity a much easier and more powerful one to take advantage of. ~ ~ ~ *A note on terminology: the terms back bias and body bias are used interchangeably. Likewise the terms adaptive and dynamic when used in the FD-SOI context. Here is a quick explanation of how it works, from an ST paper from several years ago: Back-biasing consists of applying a voltage just under the BOX of target transistors. Doing so changes the electrostatic control of the transistors and shifts their threshold voltage VT, to either get more drive current (hence higher performance) at the expense of increased leakage current (forward back-bias, FBB) or cut leakage current at the expense of reduced performance. While back-bias in planar FD is somewhat similar to body-bias that can be implemented in bulk CMOS technology, it offers a number of key advantages in terms of level and efficiency of the bias that can be applied. Back-biasing can be utilized in a dynamic way, on a block-by-block basis. It can be used to boost performance during the limited periods of time when maximum peak performance is required from that block. It can also be used to cut leakage during the periods of time when limited performance is not an issue. In other words, back-bias offers a new and efficient knob on the speed/power trade-off. For another good discussion of body biasing in FD-SOI, you might want to check out The Return Of Body Biasing by Semiconductor Engineering's Ann Steffora Mutschler from a couple years ago.

FD-SOI was a very important topic during the recent Mount Qingcheng China IC Ecosystem Forum. To situate things, Mount Qingcheng, with its lush hills and waterways, is located just outside of Chengdu. That of course is where GlobalFoundries is building its new fab, which will be the first in China to run FD-SOI. Chengdu is also a key city in China's automotive electronics landscape. [caption id="attachment_12236" align="alignright" width="300"] (Image Courtesy: VeriSilicon)[/caption] The theme of the forum was Building a Smart Automotive Electronics Industry Chain. Over 260 decision-makers from government, academia and industry attended – and the SOI Consortium had a significant presence. The event was chaired by Wayne Dai, CEO/Founder of consortium member VeriSilicon, and tireless champion of the the FD-SOI ecosystem in China and worldwide. Morning keynotes were given by: Carlos Mazure, Soitec CTO and SOI Consortium Executive Co-Director; Mark Granger, GF's VP of Automotive Product Line Management; and Tony King-Smith, Executive Advisor at AImotive, a GF 22FDX customer. BTW, transcripts of all the talks are available through Gasgoo, China's largest automotive B2B marketplace. You can click here to access them. (They're in Chinese – but you can open them in the language of your choice using the major translation websites.) Chengdu Officials Affirm Support for FD-SOI Fan Yi, Deputy Mayor of Chengdu, spoke extensively of FD-SOI in his keynote on the importance of rapidly developing smart cars. He heralded the “spectacular” new GlobalFoundries fab there. Following a meeting with the company's top brass the day before, he affirmed GF's confidence in their investment. There is a solid roadmap for FD-SOI, he noted, and efforts are underway to accelerate the move into production and expand education and training. He cited the benefits of FD-SOI for the entire supply chain, from design through package and test, raising the level of the entire IC industry to new heights. The government, he said, attaches great importance to this enterprise. Their thinking regarding intelligent transport in China is integrated with the overall approach to smart cities. SOI Consortium Leads Industry Keynotes [caption id="attachment_12232" align="alignleft" width="300"] Wayne Dai, VeriSilicon Founder and CEO (Photo courtesy VeriSilicon)[/caption] In his opening remarks, Wayne Dai emphasized the need for China to seize the advantage in the next round of development opportunities in the automotive electronics industry. This year's Qingcheng forum, he noted, brought together key representatives from across the supply chain, from of the highest to the deepest reaches of the smart car electronics industry, and across markets, technologies, solutions, industrial ecosystem, standards and regulations. In his talk on how FD-SOI is boosting the accelerated development of automotive electronics, Carlos Mazure presented the SOI Industry Consortium. He noted that the Consortium promotes mutual understanding and development across the ecosystem. SOI is already present throughout automotive applications, he noted. There are currently about 100mm2 of SOI per car, in such diverse areas power systems, transmissions, entertainment, in-vehicle networking and more. SOI will experience especially high growth in electrification, information/entertainment, networking, 5G, AI/edge computing and ADAS. He then went on to give some history and an extensive overview of the major trends and highlights we've seen over recent years. He finished by giving examples of convergence across the supply chain with IC manufacturers working with automakers to lower power, increase processor performance and advance 5G. [caption id="attachment_12233" align="alignright" width="665"] Carlos Mazure, Soitec CTO and SOI Consortium Executive Co-Director; Tony King-Smith, Executive Advisor at AImotive and Mark Granger, GF's VP of Automotive Product Line Management (Photo courtesy VeriSilicon)[/caption] GF's Mark Granger addressed the rapid development of automotive electronics. In certain areas, he said, he sees growth rates of over 20%. They are working on building the Chengdu ecosystem, especially for design, and in cooperation with the rest of the supply chain. Furthermore, he reminded the audience, when you talk about cars, travel implies that you also talk about IoT as well as things like infotainment and integrated radar ICs. In addition to cost and power efficiencies, the AEC-Q100 standard for IC reliability in automotive applications is also pushing designers to turn to FD-SOI. In the GF meeting with Chengdu government officials (referenced above in deputy mayor Fan Yi's talk), he too confirmed their support of FD-SOI as a key technology for China. GF is currently cooperating with about 75 automotive partners, he said, and the company is looking to increase cooperation with partners in the Chengdu region. Tony King-Smith talked about the 22FDX test chip AImotive is doing with Verisilicon and GF. In case you missed it, in June 2017 AImotive announced its AI-optimized hardware IP was available to global chip manufacturers for license. AiWare is built from the ground up for running neural networks, and the company says it is up to 20 times more power efficient than other leading AI acceleration hardware solutions on the market. In the same announcement, they revealed that VeriSilicon would be the first to integrate aiWare into a chip design,and that aiWare-based test chips would be fabricated on GF's 22FDX. The chip is expected to debut this year. While the afternoon agenda was not specific to FD-SOI, it did focus on the "smart cockpit" and "intelligent driving", with talks by nine leading players in China's automotive IC and investment communities. ~ ~ ~Note: Many thanks to the folks at VeriSilicon, who wrote up this event for their WeChat feed, and shared photos with us here at ASN.

GlobalFoundries has announced that the company’s 22nm FD-SOI (22FDX®) technology has delivered more than two billion dollars of client design win revenue. With more than 50 client designs, 22FDX is being used in power-optimized chips across a broad range of high-growth applications such as automotive, 5G connectivity and IoT. Their clients chose it for the significant reductions in power and die size relative to a traditional bulk CMOS process, says the company. 22FDX offers the industry’s lowest operating voltage, delivering up to 500MHz frequencies at only 0.4 volts. The technology also delivers efficient single-chip integration of RF, transceiver, baseband, processor, and power management components, “...providing an unparalleled combination of high performance RF and mmWave functionality with low-power, high density logic for devices that require long-lasting battery life, increased processing capability, and connectivity.” 22FDX is in early production, with yields and performance matching client expectations. A recent VLSI Research survey indicated that FD-SOI technology is seen as a complementary technology to FinFET. It's gaining traction in application spaces such as IoT, where power consumption is important and the product life is relatively short. “We’re only just beginning,” said GF CEO Tom Caulfied. “We have found a way to separate ourselves from the pack by emphasizing our differentiated FD-SOI roadmap and client-focused offerings that are poised to enable connected intelligence. We will continue to build on our momentum and look for ways to expand our reach to address the evolving needs of the industry.” Here's a sampling of customer quotes from the press release (read more here): “At Synaptics, as we expand upon our industry-leading mobile and PC businesses to include delivering new and innovative products that address the booming IoT market, we require the best available technologies to enable us to deliver top-notch solutions including voice and multimedia processing capabilities for our customers,” said the company's CEO, Rick Bergman. “GF’s 22FDX technology delivers a potent mix of low static and dynamic power along with excellent performance to give us a great platform for our world-class products.” “As our customers increasingly demand more from their mobile experiences, our partnership with GF on its 22FDX technology is critical to differentiate ourselves in the competitive market and deliver powerful and efficient mobile SoCs,” said Rockchip CEO Min Li. “Our goal has always been to provide more secure, connected experiences for drivers. Combining our leadership in radar technology with GF's 22FDX automotive-qualified process, we are able to deliver a cost-effective, high performance, low power solution that opens new opportunities for car manufacturers to provide better experiences for drivers around the world," said Kobi Marenko, CEO of Arbe Robotics. “The automotive industry realizes that assisted driving solutions require more camera information besides Radar and Lidar, integrating information from multiple cameras. The resulting DreamChip multi-core vision processor platform, based on the 22FDX process is providing European auto makers and Tier 1 automotive component suppliers with a platform from which they can create custom derivatives with a massively reduced time to market," said Dream Chip Technologies CEO Jens Benndorf. “With 22FDX, the value proposition for us is the potential power and area savings, two key metrics for our highly optimized LTE NB-IoT and CAT-M chipsets. In addition, leveraging the growing ecosystems of IP available in the 22FDX process helps to accelerate time to market,” said Peter Wong, CEO at Riot Micro, which designs purpose-built silicon for wireless IoT applications. (Read more about that here.) GF adds that it is preparing to deliver 12FDX™ technology, which will provide a full node scaling benefit and improved power efficiency for a new generation of applications, from edge-node artificial intelligence and AR/VR to 5G networking and ADAS.

Dolphin Integration, a partner in the ENIAC THINGS2DO European FD-SOI project, showcased its achievements with PowerStudio™ during the project final review. Power Studio is Dolphin's cutting-edge EDA tool for safe Power Regulation Networks implementation. THINGS2DO, which stands for THIN but Great Silicon to Design Objects, was a 4-year, €120 million EU project (85% industry-funded) with over 40 partners that just finished up at the end of 2017. The goal was to build a design development ecosystem for FD-SOI. The project funded and supported the development of major FD SOI-based IPs and ASICs as well as EDA tools. (Another recent THINGS2DO announcement was Dream Chips’ ADAS SoC fabbed in GlobalFoundries’ 22FDX technology -- read about that here.) “Being involved in the THINGS2DO project was an opportunity for Dolphin Integration to start introducing FD-SOI in its automatic design methodologies,” said Frederic Poullet, Dolphin Integration’s CTO (read the press release here). “Dolphin Integration plans to offer a full suite of tools allowing its customers to implement right-on-first-pass Power Regulation Networks.” The company notes that THINGS2DO also proved that low power consumption makes FD-SOI a perfect fit for IoT and automotive applications. For instance, dynamic control of threshold voltage can be used to compensate for temperature variations, and to drive speed improvements by 200% in ultra-low voltage applications. Dolphin Integration provides energy efficient IPs and ASIC services dedicated to the low-power application market and supports its internal teams with tailor-made software tools. To address the specific needs of its customers in low-power design, Dolphin developed PowerStudio™, a global solution for the optimization of Power Regulation Networks (PRNet) to be used at an early stage of the SoC design process. In particular, it addresses new design challenges in noise and power supply integrity. The first module of PowerStudio™ will also embed architecture optimization features at the schematic level, in terms of FoM-based cost optimization, mode management, margin cuts and integrability rate-based risk optimization. Btw, Dolphin Integration Director Frederic Renoux gave an excellent great presentation at an SOI Consortium event in Nanjing, China last year, entitled Embedding power regulation activity control networks for best SoC PPA. Dolphin Integration joined Global foundries’ FDXcelerator™ Program last year (read the press release here) to streamline design in 22FDX®. "Our comprehensive and robust library of voltage regulators, power gating cells and logic modules, enables to deal cost-effectively and securely with power distribution, power gating, power monitoring and power control of any SoC design in 22FDX," Michel Depeyrot, Dolphin Integration's Chairman, said at the time. "As connected devices sleep most of their time, users of 22FDX also benefit from our ultra-low power and accurate oscillators to design an always-on RTC which consumes as little as 60 nA." See the Dolphin Integration website for the full catalog of their IP, EDA and ASIC/SoC service offerings, including for GF's 22FDX.

They're calling it, “The most advanced, lowest power-consuming GPU-enabled MPU on the market.” It's NXP's new i.MX 7ULP general-purpose processor, and it's on 28nm FD-SOI. They've got a nifty video summing it all up – you can watch it here. [caption id="attachment_10388" align="alignleft" width="300"] NXP is first to market with a general-purpose processor on FD-SOI: the i.MX 7ULP. It's got both ultra-low power consumption and rich graphics for battery powered applications. (Courtesy: NXP)[/caption] With the i.MX 7ULP, NXP is first to market with an FD-SOI applications processor offering the industry’s lowest power consumption. The debut was made at the recent Embedded World Conference in Nuremberg, Germany, and it made a big splash in media across the globe. (Read the full press release here.) In deep sleep mode, it boasts power consumption of just 15 uW or less: 17 times less than previous (and highly successful) low power i.MX 7 devices. Dynamic power efficiency is improved by 50 percent on the real-time domain.The i.MX 7ULP applications processor family is currently sampling to select customers. Broader availability of pre-production samples is scheduled for Q3 2017.Hello, IoT!The high-performance, low-power solution is optimized for customers developing applications that spend a significant amount of time in standby mode with short bursts of performance-intense activity that require exceptional graphics processing. Sounds like IoT – and indeed it is, and more.With the i.MX 7ULP, NXP's targeting wearables, portable healthcare, smart home controls, gaming accessories, building automation, general embedded control and IoT edge solutions. Bottom line: it's designed to enable ultra-low-power and secure, portable applications – especially those demanding long battery life. (Read the current fact sheet here.)The detailsThe i.MX 7ULP features an advanced implementation of the ARM® Cortex®-A7 core, the ARM Cortex-M4 core, as well as a 3D and 2D Graphic Processing Units (GPUs). It's got a 32-bit LPDDR2/LPDDR3 memory interface and a number of other interfaces for connecting peripherals, such as WLAN, Bluetooth, GPS, displays, and camera sensors. [caption id="attachment_10387" align="alignnone" width="834"] (Courtesy: NXP)[/caption] NXP says this new design, based on FD-SOI’s lower voltage capability, enables rich user experience through extremely power-efficient graphics acceleration, a fundamental requirement in many of today’s consumer and industrial battery-operated devices that incorporate robust graphic interfaces. Further enablement includes rich Linux or Android ecosystem with the real-time capability supported by FreeRTOS.Leveraging body biasing and moreNXP credits the design’s extreme low leakage and operating voltage (Vdd) scalability to that FD-SOI specialty: reverse and forward body biasing (RBB/FBB) of the transistors, and its smart power system architecture.In presenting the new i.MX 7ULP to the tech press, the company highlighted the following FD-SOI design advantages: Large dynamic gate and body biasing voltage range Domain and subsystem optimization with custom standard cell library with mixed voltages Low quiescent current (Iq) bias generators Enhanced ADC performance with unique FD-SOI attributes Fail Safe I/O for simplified low power system design To that, add a note about security. As the chip's fact sheet says, “The processors deliver hardware-enabled security features that enable secure e-commerce, digital rights management (DRM), information encryption secure boot, and tamper detection.” Those are just the sort of things that demand the bursts of high performance that dynamic forward body biasing delivers where and when it's needed.Samsung fabs, Verisilicon adds IPTwo other SOI Consortium members – Samsung and Verisilicon – are particularly pleased with NXP's results.“We are excited that NXP is the first to bring the benefits of FD-SOI (28FDS) technology to the general purpose market,” says Ryan Lee, VP of the Foundry Marketing Team at Samsung Electronics. “28FDS technology will satisfy a growing and critical need for ultra low power designs that require power-performance at very low voltages. We plan to evolve 28FDS technology to a differentiated low-power single platform by implementing RF and embedded Non-Volatile Memory (eNVM) solution for our customers’ success.”NXP’s processor design enables robust low power graphics for the IoT and wearable markets through two graphic processor units (GPU) from Vivante: the GC7000 NanoUltra 3D GPU with a low power single shader, and the GC320 Composition Processing Core (CPC) for 2D graphics. The 3D GPU plays a critical role in enabling rich 3D based user interfaces, while the CPC can accelerate both rich 3D and simpler 2D user interfaces. Processors based on the combination of the two GPUs enable efficient display systems which offload and significantly reduce system resources, in turn providing rich user interfaces at low power levels to extend the battery life of devices.“Our 3D GPU is a result of a joint collaboration between Vivante and NXP to deliver industry-leading 3D capabilities with the lowest power consumption,” said Wei-Jin Dai CEO at Vivante Corporation and Chief Strategy Officer and GM of the IP Division at Verisilicon. “The power savings from using the right GPU in an ultra low power processor is one of the major attributes and advantages of the architecture.”So, now shall we dig in a little deeper into the “why FD-SOI” question? Read on in Part 2 of this article.-- By Adele Hars, ASN Editor-in-Chief

By: Tamer Ragheb,Digital Design Methodology Technical Manager at GlobalFoundries and Josefina Hobbs, Senior Manager of Strategic Alliances, Synopsys It’s clear that getting an optimal balance of power and performance at the right cost is foremost in the minds of designers today. Designers who want either high performance or ultra low-power, or ideally both, have a choice to make when it comes to migrating to next generation nodes. For applications that push the envelope in performance, FinFET would be the optimal solution. For applications that require ultra low-power and more RF integration, FD-SOI is the right solution. The two technologies have different value propositions that need to be considered while designing for applications ranging from high-performance computing and server to high-end mobile and Internet of Things (IoT). GlobalFoundries 22FDX is the industry’s very first 22nm FD-SOI platform. The 22FDX technology is specifically designed to meet the ultra low-power requirements of the next generation of connected devices. The big advantage of this platform is its ability to provide software control at the transistor level through flexible body-biasing (Fig. 1). The ability to provide real-time trade-offs between power and performance via software-controlled body-biasing of the transistor creates new options for the designer. For example, imagine designing a processor for a Smartwatch that could match its power-performance tradeoff to your typical use and modify its performance based on how you’re using it that day. [caption id="attachment_9473" align="alignleft" width="610"] Figure 1: Benefits of 22FDX body-biasing[/caption] The full impact of the body bias capability of 22FDX becomes clear when compared to incumbent high-performance process technologies (Fig. 2). 22FDX compared to a 28nm high K metal gate (HKMG) technology can provide up to 50% less power at the same frequency, or 40% faster performance at the same total power than 28HKMG. In addition, 22FDX can be further optimized with forward body bias, shown on the blue curve, to further reduce the power or to further boost the speed in a turbo operation mode. [caption id="attachment_9474" align="alignleft" width="610"] Figure 2: 22FDX Body Bias Optimizes Performance and Power[/caption] In addition to the body bias, 22FDX offers capabilities for design flexibility and intelligent control that are not available in other technologies. These include: Improved electrostatic control of the transistor acts as a performance booster and enables lower VDD (i.e., lower power consumption) while reaching significant performance Low variability and body-biasing capability that can achieve 0.4 volt operation Complete RF enablement with ‘knobs’ to reduce RF power by up to 50 percent Manufacturing success is highly sensitive to specific physical design features, with advanced nodes requiring more complex design rules and more attention to manufacturability issues on the part of designers. However, there are essentially no additional manufacturing requirements to design in 22FDX beyond what is required for 28nm designs. There are four application optimized extensions available with 22FDX (Fig. 3). These are: 22FDX ULP- an ultra low-power extension that provides logic libraries and memory compilers that are optimized for 0.4 volt operation. 22 FDX ULL- an ultra low-leakage extension that brings in an expanded device suite capable of achieving one pico-amp per micron leakage. 22 FDX UHP- an ultra high-performance extension that leverages the overdrive capabilities and body-biasing features to maximize the performance of technologies in a turbo or a burst mode. It has high performance libraries and high speed interfaces and BEOL stacks optimized for competing architectures or applications. 22 FDX RFA- an RF and analog extension that brings in full characterization and enablement for RF applications, including optimized RF layouts and P cells, BEOL passives, and IP for Bluetooth LE and WIFI applications. [caption id="attachment_9475" align="alignleft" width="610"] Figure 3: 22FDX Platform and Extensions[/caption] GlobalFoundries reference flow for 22FDX has been optimized to support forward and reverse body bias (FBB/RBB), which provides the design flexibility to optimize the performance/power trade-offs. The reference flow supports implant-aware and continuous diffusion-aware placement, tap insertion and body bias network connectivity according to high voltage rules, double-patterning aware parasitic extraction (PEX), and design for manufacturing (DFM). This provides designers with the flexibility to manage power, performance and leakage targets for the next-generation chips used in mainstream mobile, IoT and networking applications. GlobalFoundries has been collaborating with Synopsys to enable and qualify their tools for the 22FDX Reference Flow. The recent qualification of Synopsys’ Galaxy™ Design Platform for the current version ofGlobalFoundries’ 22FDX technology allows the designer to manage power, performance and leakage and achieve optimal energy efficiency and cost effectiveness. Synopsys’ Galaxy Design Platform supports body biasing techniques throughout the design flow, including both forward and reverse body bias, enabling power/performance trade-offs to be made dynamically and delivering up to 50% power reduction. Key tools and features of the Galaxy Design Platform in the 22FDX reference flow include: Design Compiler® Graphical synthesis with IEEE 1801 (UPF) driven bias-aware multi-corner multi-mode (MCMM) optimization Formality® formal verification with bias-aware equivalence checking IC Compiler™ and IC Compiler II™ layout with physical implementation support for non-uniform library floorplanning, implant-aware placement, multi-rail routing, and advanced power mesh creation StarRC™ parasitic extraction for multi-rail signoff with support for multi-valued standard parasitic exchange format (SPEF) PrimeTime® timing analysis and signoff including distributed multi-scenario analysis (DMSA) static timing and noise analysis, using AOCV and POCV technology IC Validator In-Design physical verification The 22FDX technology leverages existing design tools such as the Galaxy Design Platform, manufacturing infrastructure and the broader design ecosystem. This speeds time to market and enables the creation of differentiated products.