Leti

The Compact Model Coalition (CMC) has selected Leti’s L-UTSOI as a standard model for FD-SOI in the industry. The CMC is a working group composed of the major semiconductor companies and is part of the Silicon Integration Initiative (Si2). The Si2 Compact Model Coalition announcement covers the approval and financial support of L-UTSOI. L-UTSOI is derived from the Leti-UTSOI compact model, which has been implemented in circuit-simulation software and used in industrial process design-kits for several years. Thierry Poiroux, head of CEA-Leti’s Simulation and Compact Model Laboratory, said the selection of L-UTSOI as a Si2-CMC standard model ensures that it will be supported as long CMC industry members use it. “This is of paramount importance for large chip makers who will use this model in the future,” he continued. “With a standard model, they are assured that a team of model developers is able to take care of the model improvements and/or bug fixes they need during the whole lifetime of their technology. It also positions CEA-Leti among the few compact-model developer teams able to develop and support a standard model.” The role of compact models Once a new or enhanced chip is designed, it must be simulated prior to entering the expensive manufacturing phase. This proof-of-concept step relies on compact models that are expressed through a set of equations implemented in a form ensuring accuracy, robustness and numerical efficiency. Such compact models are approved and supported by the standard-setting arm of Si2, the CMC, which is an international working group focused on standardizing SPICE device models. “As a member-driven organization, the CMC strives to provide value for its members and the semiconductor supply chain,” said Peter Lee, CMC chair. “With 15 models now available, CMC members have a distinct competitive advantage with early access to new features and bug fixes, and an 18-month lead on standard models released to the public. Adding L-UTSOI to the mix of models was a direct response to our customer requests for model support as we continue to add value to their membership.” Standard models are developed by the world’s leading SPICE-model experts. They are used by designers working at the most advanced fabless semiconductor companies, foundries, and IDMs. Implemented in the industry’s top versions of circuit-simulation software and duly qualified, standard models give designers the assurance that their integrated circuits will perform according to the design specifications. Industry proven L-UTSOI was extensively proven by the industry and its standardization will ensure long-term access and maintenance in EDA tools for FD-SOI designers. Available to coalition members now, it will soon be implemented in major versions of circuit-simulation software, and its source code will be released publicly in June 2021. “CEA-Leti’s compact model boasts physically based model parameters,” said Harrison Lee, chair of the L-UTSOI Working Group and principal engineer of the Foundry Design Enablement Team at Samsung Electronics. “We can utilize predictive analysis of a process technology to optimize a transistor’s design implementation for a specific end-use. With a capability to 10 nanometers and below and the ability to simulate a wide range of voltages and body biases, we can easily research a wide variety of analog and digital applications.” As noted in Leti’s announcement (read the whole thing here), the FD-SOI transistor’s back-gate allows tuning of the device in a low-leakage and low-power operating regime or higher-performance operating regime. This unique capability offered by FD-SOI enables the fabrication of smaller, faster and denser chips than standard bulk CMOS technology. FD-SOI devices are widely used in wearable electronics, automobiles and IoT. Leti pioneered FD-SOI in 1992. Here at ASN we’ve been covering their FD-SOI compact model work for over a decade.

It should really be called SOI photonics – not just silicon photonics, quipped Soitec CTO Christophe Maleville at the SOI Consortium Japan event last fall. You’ve got to have SOI for the waveguides. There are megatrends driving significant growth in photonics – and they were all covered at the event. This is the final post in our coverage of the SOI Consortium’s Japan event (thank you for your patience!). It covers the photonics-related presentations by Soitec, Leti, Cisco/Luxtera, GlobalFoundries, Cadence and TowerJazz. Most of these presentations are now posted on the SOI Consortium website – you can access them if your organization is a member of the consortium. By way of reminder, the Japan SOI Symposium was a great success, with both days well attended. In case you missed our previous posts about the event, you’ll want to go back and read them, too. The first post covered the 5G/RF-SOI presentations by ST, Toshiba, Incize, GF, Silvaco and Sitri – you can read it here. The second post on the event covered eight very informative presentations on SOI in IoT and automotive by NXP, Dolphin Design, Leti, Silvaco, Arm, I-fuse and Secure-IC – you can read that here. Note that you can click on any of the illustrations to see enlarged versions. And now without further ado, here are the summaries of the photonics presentations. SOI Enabling Photonics – Ecosystem and Market Outlook – by Aziz Alami-Idrissi, GM Specialty SOI, Soitec. [caption id="attachment_28773" align="alignleft" width="233"] (Courtesy: Soitec SOI Consortium)[/caption] The megatrends in SOI photonics are: 5G (for more bandwidth, HPC, edge quantum computing), data centers (for high data rate transceivers and high-switch bandwidth), sensors (lidar, gas/chemical and gyroscopes) and biosensors (especially for medical). These are driving big changes: the 44% CAGR means the market is growing from a current TAM of about 500M$ to over 4B$ in 2025. One thing that’s really interesting is the expansion of the photonics market into these new fields in the next few years. While in 2019 90% of the photonics market served data center applications (the other 10% is for long haul), in 2025 optical I/O’s will account for over a third of the photonics market TAM. The other applications making an impact include AI, quantum, lidar (which will move into high-volume manufacturing in 2024) and medical sensors (hitting high-volume in 2023). For its part, Soitec is strengthening its portfolio with 8” and 12” large product coverage, new product sampling engaged, and extended features including newer engineered layers and RF immunity. Advanced Silicon Photonic Solutions Leverage SOI Technology – Eleonore Hardy, Business Development Manager, Silicon Photonics, CEA-Leti [caption id="attachment_28769" align="alignright" width="358"] (Courtesy: Leti SOI Consortium)[/caption] Leti helps companies make photonics products they can bring to volume foundries, explained Hardy. (btw, they’re presenting 21 (!) papers – including 5 invited – at PhotonicsWest 2020. Read about that here). You want to do integrated photonics to bring down costs, reduce power consumption, and scale (for higher volumes and reduced footprint). There are essentially three substrate choices: InP, SiN or SOI. SOI uses CMOS processes, so it’s low-cost and can be used in high-density photonic integrated circuits. What about the laser? Leti has developed III-V on silicon bonding, so you can have the laser on 4” III-V with a 300mm CMOS process (this is what Intel’s doing). They’re moving to 300mm wafers, 3D and advanced packaging. While communications is the big application realm, Leti is also applying photonics in automotive, medical, environment and computing. In the computing realm she gave the example of the European QuantERA SQUARE (Silicon Photonics for Quantum Fibre Networks) project for which Leti is doing the quantum emitter for absolute security and computing, wherein the transceiver/receiver for quantum cryptography integrates a hybrid III-V on silicon pump laser. Other examples of their work include miniature, low-cost and agile lidar for automotive and industrial applications (they’re working on a beam-steering emitter for an optical phased array). GlobalFoundries Silicon Photonics Solutions for Wired Infrastructure – Anthony Yu, VP, GF [caption id="attachment_28770" align="alignleft" width="684"] (Courtesy: GlobalFoundries SOI Consortium)[/caption] GF is giving their photonics business a big push. Optical interconnects are the future, said Yu, so they’re putting a lot of money into it. With data streaming multiplying by 3x/year and a current foundry TAM of $63 billion, the opportunity is huge. Fab 10 in Fishkill runs their 90WG process on 300mm wafers. A new process, 45CLO (also on 300mm) for O and C bands is going into the Malta fab. A big focus here are optical transceivers that convert RF signals to light. They see RF on SOI in a monolithic solution is needed to serve 100Gbs applications. They’re also moving to co-packaging optics: the packing technology will surround it with photonic chiplets. Customers have indicated that pulling the signals off the chips is limited by power, so they’ve worked hard on the fiber attach with MEMS and packaging technology for co-packaging. GF relies on substrate providers for high-quality SOI, and they have a world-class development team, he concluded. Integrated Electro-Photonics Design Platform – A multi-physics, multi-fabrics system design solution – Scott Li, Sr. AE Manager of Custom IC Platform, Cadence [caption id="attachment_28771" align="alignright" width="374"] (Courtesy: Cadence SOI Consortium)[/caption] This talk focused on photonics design challenges and solutions – including the CurvyCore™-based PDK for waveguide creation modal properties calculation that Cadence will soon be announcing. It’s a math-based engine that generates complex curvy shapes to support photonics. The first design challenges, said Li, are at the circuit level: how to do the schematics. The detailing tools, timesteps management and circuit simulation need to give the user the best performance. Cadence is working in close collaboration with a company called Lumericable on this. The next set of design challenges come at layout – especially generating curvilinear layout for any shape so that there are no gaps in connections. This is where CurvyCore comes in, fully automating layout and making it easy to modify. This includes place route, DRC and LVS for curvy shapes. The final challenge is at the system level. There is work to do here, but Cadence is collaborating closely on solutions with key partners. The ultimate goal is for photonics layout and editing to be available with all the features designers get in electronics editing. Silicon Photonics for High Volume and High Performance Optical Interconnects Applications – Thierry Pinguet, Technical Leader Engineering, Cisco /Luxtera [caption id="attachment_28772" align="alignleft" width="396"] (Courtesy: Cisco/Luxtera SOI Consortium)[/caption] Over the last decade there’s been steady growth in optical high speed interconnect solutions, mainly driven by HPC, enterprise, and especially the hyperscale datacenter. The largest volumes are for intra datacenter interconnect (between servers). Now mobile applications for backhaul are also driving volume for high speed optical interconnect for 5G network implementation. ASICs and photonics are getting closer as the industry moves to put them in the same package. But everybody does silicon photonics differently (even within Cisco). Luxtera tries to use the same infrastructure as electronics, but patterning is still a challenge: it’s not 90o “Manhattan” style. The wafers are no problem – they work with leading wafer suppliers like Soitec and SEH. They have explored a “double SOI” substrate (like a mirror), which showed large insertion loss improvements in grating couplers . For the electronics and the laser (MEMS), they do a micropackage, although at one point they also did monolithic integration. For better performance, they’re moving to TSVs. A hot topic is ASIC and photonics co-packaging. You can use optical tiles, but then the light is remote, like a power supply. No matter how you do it, though, the bottom line is that silicon photonics is the only way forward for the data center. PH18: World’s First Open Commercial Silicon Photonics Process and PDK from TowerJazz – Masanobu Kumazaki, Engineer, TowerJazz. This presentation was given in Japanese without translation into English, and is not available on the consortium website. But the slides showed at the event indicated that their PH18 is the world’s first open commercial silicon photonics offering. For optical transceiver components, silicon photonics provides another opportunity for a specialty foundry. It is a high-growth market. The TowerJazz offering is 220nm SOI, and uses standard EDA tools from Synopsys, Cadence and Mentor for design flow.

Here is our second post about the SOI Consortium’s Japan Symposium this past fall. This will provide summaries of eight very informative presentations on SOI in IoT and automotive by NXP, Dolphin Design, Leti, Silvaco, Arm, I-fuse and Secure-IC. There’s a lot of content to summarize, so this post is about twice as long as those we usually do. But you’ll want to read right to the end, for sure! In case you missed our previous post on the 5G/RF-SOI presentations given at the Japan event, you can read it here. Our next and final post on the Japan event will cover photonics presentations by Cisco/Luxtera, TowerJazz, GlobalFoundries, Leti, Cadence and Soitec. By way of reminder, the Japan SOI Symposium was a great success, with both days well attended. If your company is a member of the SOI Consortium, you can now access most of these presentations on our website. You can also click on the illustrations in this post to see them in enlarged versions. [caption id="attachment_28106" align="alignleft" width="366"] (Courtesy: NXP SOI Consortium)[/caption] The IoT World Enabled Through SOI - Jon Cheek, NXP Sr. Director, Front-End Innovation For NXP, FD-SOI introduced the ability to easily add different functionalities to the technology node like ULP, eNVM, support for high-voltage and embedding RF. For them, said Cheek, it’s about the range, and with adaptive back bias, you can “get crazy”, so you can really achieve amazing things. In fact, they think they now have the lowest leakage SRAM in the industry, thanks to body biasing. The i.MX 7ULP is finding significant success in wearables. Their “crossover” chips are the latest beneficiaries of FD-SOI with body biasing. The “new normal”, they offer huge improvements for real-time operating systems – which is of course key for edge computing. (As you can imagine, the audience was intently taking notes throughout -- this was a really excellent talk!) It also is great for machine learning, as it is designed to unlock the potential of voice-assisted end nodes. The IP they needed is now available from multiple vendors, noted Cheek, such as Tensilica and VeriSilicon. Another key play will be in visuals for industrial computing. He concluded by observing that the automobile is the ultimate IoT machine, with 10x the amount of code now found in leading edge airplanes. That’s where the i.MX8 and 8X come in. [caption id="attachment_28104" align="alignright" width="323"] (Courtesy: NXP SOI Consortium)[/caption] High-Voltage SOI – Enabling Automotive- NXP Jon Cheek gave this presentation on the second day of the Japan event. Long-time followers of SOI will know that NXP has been excelling in high-voltage (HV) SOI for well over two decades now (including the pioneering work done by Philips, now part of NXP: their EZ-HV SOI patent dates back to 1993). It’s probably safe to say that NXP's SOI-based automotive chips are used by virtually every carmaker on the planet. HV follows well behind the leading edge – it’s currently mostly around 130nm (the limits are related to metalization). Reason #1 it’s on SOI? SOI-based technologies are incredibly reliable, especially in the automotive culture targeting the three zeros (0 emissions, 0 accidents and 0 time wasted). Today’s car manufacturer’s are going to a distributed environment, and SOI still provides a huge advantage, making parts that are smaller, lower power and more reliable – so it drives a lower BOM for automakers.In conclusion, said Cheek, NXP’s leadership through SOI innovation enables scalable solutions, high voltage analog integration, sensor integration, and reliable safe passenger experience. [caption id="attachment_28101" align="alignleft" width="432"] (Courtesy: Dolphin Design SOI Consortium)[/caption] Improving SoC Energy-Efficiency with Dolphin Design Platforms – Nicolaus Gaude, BizDev Product Marketing, Dolphin Design Dolphin has a series of platforms, techniques and IP for increasing speed and drastically improving energy efficiency in SoC design. Gaude introduced their Speed Platforms, which include a Power Management Platform and a Processing platform, both of which make dramatic improvements in energy efficiency. The Power Management Platform keeps control of power management from architecture to design, resulting in a 10x improvement in energy efficiency. The Processing Platform comprises configurable RTL clusters for best-in-class (100x) energy-efficiency. Gaude then turned to the Dolphin’s Adaptive-Body Bias (ABB) IP for breakthrough energy-efficiency with FD-SOI. This is real-time, “on-the-fly” body biasing: the IP does it all. It is silicon-proven on GlobalFoundries’ 22FDX with Arm cores and Invecus standards cells SRAM, with breakthrough energy efficiency. [caption id="attachment_28108" align="alignright" width="363"] (Courtesy: Silvaco SOI Consortium)[/caption] Platform Infrastructure for SOI-IP Ecosystem – Thomas Blaesi, VP of Global Marketing, Silvaco The massive use of IP is both an advantage and a challenge, began Blaesi. There are solutions out there, but they are disconnected. Typically SoC/IP designers, IP librarians and support folks use various systems, while procurement, finance and legal use others. This is a problem for both the providers and the consumers of IP. Silvaco has a new system called Xena that centrally organizes all IP data: it’s an IP repository for tracking accounts, products, contracts, devices, support, compliance and reporting. One of the first beneficiaries of Xena will be the SOI ecosystem, as providers of SOI IP are already signing on. Beyond the organizational advantages, Xena has patented “finger printing” and “DNA analysis”, so there is a digital representation of each IP on an SoC that can’t be reverse engineered. Each fingerprint contains list of unique signatures of each file in an IP or SoC. A file’s unique signature is created from the entire file content, and that signature is guaranteed to be unique to that content. It enhances support for all versions of common design files: hard IP, soft IP, and embedded software. Because it’s cloud or enterprise based, it will be particularly useful for large organizations. Fingerprinting and DNA analysis are vendor agnostic, universal, and easy-to-use tools and methodologies for IP lifecycle management, he concluded. [caption id="attachment_28103" align="alignleft" width="463"] (Courtesy: Leti SOI Consortium)[/caption] Ultra-low power, FD-SOI based IP, in the space of IoT, Health Care, Smart Connectivity 5G – Michael Tchagaspanian, EVP Industrial Partnerships, CEA-Leti This presentation began with a review of the explosion in devices with IoT and related investments, then connected all the ways in which innovations powerhouse Leti is contributing – from the SOI wafer level to the chip level – which is to say practically everywhere! Especially hot topics in FD-SOI included: the roadmap to sub-10nm; CoolCube monolithic 3D; new embedded memories; power amplifiers; Ultra-Wide Range DSP; smart sensing local processing (including haptics, imaging, infrared advanced processing); local processing with edge AI; and spike coding for deep neural networks. He showed information on two always-on/on-demand transmission 28nm FD-SOI IoT test chips that taped out in mid-2019: the Warrior and the Samurai. And finally, he covered silicon-proven IP that Leti has for FD-SOI including power management blocks, lots of RF IP (including low-power RF wake-up), sensor interfaces, clockless network-on-chip and new SRAM technologies. These and more will be covered at the next Leti Innovation Days in Grenoble (June 2020) – during which in parallel, btw, there will also be a European SOI Summit hosted by the SOI Consortium. [caption id="attachment_28099" align="alignright" width="475"] (Courtesy: Arm SOI Consortium)[/caption] FDSOI Enablement for a Total Compute Future – Manuj Rahor, Director Emerging Technologies Product Marketing, Arm Subtitled A perspective on system optimization with Arm FDSOI IP, this presentation reviewed how Arm is enabling system gains through optimization across IP boundaries. This is work happening in the Arm Artisan Physical Design Group (PDG), which provides logic, memory and POP (processor optimization package) IP as well as various products to help ease implementation challenges for advanced nodes. In this case the focus is on Total Compute enablers on Samsung 28nm FD-SOI (called 28FDS) – specifically three building blocks recently launched on FD-SOI. The first is the 128Mb Wide Capacity embedded MRAM (an eNVM to replace eFlash) compiler for storage delivered to Samsung in July `19. It was demonstrated in silicon in the Musca-S1 Smart IoT Device Demonstrator on 28FDS, an energy efficient IoT device with eMRAM secure boot on-chip storage. [Read our coverage from March 2019 here.] The second is a novel design developed with Spin Memory. It recently taped out on 28FDS and is slated for delivery in 2020. Adding an “Endurance Engine to the eMRAM that was delivered in 2019, the ARM-Spin innovation delivers RAM-like performance with increased speed and endurance. What’s at issue here is a change in use cases. Use cases served by eFlash were not written to that often; now with sensors (as in IoT) that continually gather and write data, eFlash endurance is not sufficient. The third is billed as an SRAM replacement compiler. Its MRAM as RAM in A-class systems, with significant energy and performance gains. Again, this is a use-case issue: retention is lower (this is for weeks months, whereas the other solutions are for 10 years). But you can get more RAM than SRAM into the same footprint, so you get a 60% reduction in DRAM traffic and increased performance. Delivery for this is marked as 2020+. [caption id="attachment_28100" align="alignleft" width="294"] (Courtesy: Attopsemi SOI Consortium)[/caption] I-fuse™: A Disruptive OTP Technology – Dr. Shine Chung, Chairman, Attopsemi I-fuse is a disruptive OTP (One-Time Programmable) technology without disrupting a fuse. The goal was a 100x increase in reliability at 1/100th of the cell size and 1/10th the power. It has now been demonstrated in GlobalFoundries’ 22FDX FD-SOI technology for energy harvesting applications. In the OTP IP technologies, explained Dr. Chung, they defied the conventional wisdom of breaking a fuse to maintain a permanent programmed state forever: Attopsemi’s I-fuse™ is actually a “non-breaking” fuse. “I don’t mind to break a fuse, but I do care about breaking a fuse by explosion”, said Dr. Chung. “The I-V curve of programming a fuse beyond the break point actually shows more like an explosion. The anti-fuse OTP also ruptures gate oxide by explosion. On the contrary, I-fuse™ is a disruptive OTP technology without disrupting a fuse.” He concluded, “By using MOS as switches to enable discharging two capacitors, through cell and reference cell respectively, and compare the discharge rates, the resistance in the cell can be determined higher or lower than the reference resistance so as to convert into logic data. The read energy consumed is only 1/100 of the conventional sensing, which is good for energy harvest IoT applications. Eventually most IoT devices will be battery-less.” [caption id="attachment_28107" align="alignright" width="398"] (Courtesy: Secure-IC SOI Consortium)[/caption] AIoT Embedded Security Using FD-SOI – Yan-Taro Clochard, Japan Sales Director, Secure-IC In addition to opportunities, the impact of AI on IoT (aka AIoT) adds new threats to edge devices. Design for security and in-depth security is required, down to the physical layer. For example in automotive, sensors gather data and AI analyzes it – but the enabler is security. The challenge of AI is the increase in data and connectivity with unsecured devices. FD-SOI is a key for Secure-IC’s Securyzer security module: it leveragesFD-SOI properties to secure the AIoT world. It is flexible, and tuned for each customer. Here, FD-SOI enables the creation of physically secure systems, with secure boot and firmware updates, cryptographic services, key management and secure storage.

The first day of the SOI Consortium’s recent China event – the 7th Shanghai FD-SOI Forum – was full to bursting in every way: the room, the networking, the level of expertise, the in-depth presentations and the overall energy. We covered the Samsung and GlobalFoundry keynotes in our previous post (if you missed it, read it here).This post will recap the rest of the presentations given during the day. (If your company or institution is a member of the SOI Consortium, you’ll be able to access the full presentations online.)International Business Strategies (IBS) – Impact of AI on Automotive and IoT, and Opportunities in China (Handel Jones, CEO) When it comes to deep insights on China + tech + analytics, and especially with a thorough understanding of FD-SOI markets, Handel Jones is arguably the world’s leading expert. Here are some of the observations he shared. Though the chip industry will see declines across the board in 2019 (he sees 13.5%), he sees a return to growth in 2020. By 2030, he sees it as a trillion dollar market, of which China will have half. AI is a key driver – and will become more prevalent at the edge. Major drivers will include preventative medicine, gaming, NB-IoT and 5G. At the chip level, FD-SOI has a lower cost/chip compared to bulk – you’ve got small chips and high yields. Sensors – especially image sensors – are a key area, and this is another place where FD-SOI is better than bulk. He sees chip shortages in the 2022-24 time frame (as opposed to the current oversupply), so now is the time that China should be establishing large FD-SOI capacity.NXP – Automotive, Industrial and IoT Solutions Leveraging FD-SOI (Ron Martino, VP GM) In terms of power consumption, computing is easy but data transmission is hard, Ron Martino reminded the audience at the onset. That’s why you need the edge. This is where FD-SOI comes in, and if you want to have leadership, you should be leveraging body biasing, he said. In terms of machine learning, a lot can happen at the edge on the smallest devices. NXP is now shipping a very wide range of products based on FD-SOI, including the i.Mx7 and 8 families and the new RT crossovers. The latest announcement is the i.Mx RT 1100 MCUs, a very low-cost processor solution for high volumes. The i.MX7 ULP is in mass production for wearables, with record low leakage and high performance. The i.Mx8 and 8x are going into a broad range of applications – from retail solutions for automated checkout to pasta makers, and automotive applications for full cockpits with vision detection, as well as things like parking, V2X and in-vehicle monitoring.Sony Semi – Low Power IoT Products with FD-SOI eMRAM Technology (Kenichi Nakano, GM) Chips built on FD-SOI with eMRAM are in production, said Kenichi Nakano. In GNSS/GPS, Sony is the #1 in lowest power consumption worldwide, thanks to FD-SOI, he continued. They’ve had 70 remarkable design wins, giving them over 50% market share in the sports and health watch markets, he said with a tip of the hat to the FD-SOI ecosystem and SOI Consortium. In GNSS, performance is very important – and now they can do it in water, which is huge. Development cycles are shorter than ever – for the latest chip it started in February 2018 and was in production by the spring of 2019, achieving decreases of 20% in power, 30% in area and 10% in cost. Integrating eMRAM was easy in terms of the design flow and manufacturing, with production yield of 97-100%. So with the GXD5605GF they’ve got the first GNSS chip with FD-SOI/eMRAM/RF in the world and it’s on 28FDS/eMRAM technology. It’s very reliable and very good, he concluded.Rockchip – Challenges of AIoT Chip (Feng Chen, SVP) At the beginning of this year Rockchip announced the launch of their RK1808, a low-power AIoT solution with built-in high performance (3TOPS) NPU fabbed in GlobalFoundries 22FDX, said Feng Chen. Their clients were very happy that Rockchip delivered the real power and performance numbers they’d promised. Because of the power/performance it delivers, FD-SOI (both 22 and 28nm) is very well suited for AIoT chips, he said. It’s very cost-effective in terms of NRE and die, and there’s room for further savings. While the ecosystem needs a unified push, FD-SOI is good for the market in China, and China has the volumes FD-SOI needs. Rockchip sees particular potential in retail and smartphones.Panel – Verticals Driving FD-SOI VeriSilicon CEO Wayne Dai moderated the first panel, asking first why China should adopt FD-SOI. Soitec CEO Paul Boudre said because it is a big, dynamic market (noting that Sony’s first FD-SOI GPS win was in China). Handel Jones said that at the wafer level, there was cost parity, but with FD-SOI chips are smaller and higher yield. The main reason it’s taken so long to get going was IP, but that’s changing now, he added. Dai’s next question was about the top application fields the panelists predicted for 2020. Sony’s Kenichi Nakano said wearables with connectivity, low power consumption, small size and high levels of integration; Rockchip’s Feng Chen agreed. NXP’s Ron Martino said FD-SOI for automotive, machine learning and edge computing was shipping now, with wearables ramping.VeriSilicon – Low Power IoT Connectivity IP Design Based on FD-SOI (Yi Zeng, Director, IoT Connectivity Platform) The “value” of IoT data is not yet being generated, noted Yi Zeng but AI can help here. The IoT industry needs innovation for both chips and networking. SiPaaS – which stands for Silicon Platform as a Service – as offered by VeriSilicon can help lower the barrier to entry. [In the SiPaaS model, VeriSilicon has its own IP-based core. Based on the company's advanced chip design capabilities and mass production service experience, it has created a variety of silicon-proven chip design platforms that can significantly reduce the customer's chip design cycle.] They have FD-SOI IP for NB-IoT, BLE, GNSS and sub-1 GHz. The BLE (Bluetooth) RF IP is a complete offering optimized for low power on GlobalFoundry’s 22FDX. The NB-IoT IP is also optimized on their 22FDX ZSPNano, an energy efficient general purpose MCU+DSP core on 22FDX. And they’ll have results of test chips for GNSS RF IP on 22FDX by the end of this year.Secure-IC – AIoT Embedded Security Using FD-SOI (Hassan Triqui, CEO) While AI enables products and services, it’s important to plan for security early in the design cycle, said Hassan Triqui. Software is not enough to protect edge-to-cloud. Secure-IC’s hardware security module, Securyzr, is an IP block that can be embedded into every device to answer security functionalities such as root-of-trust and key management. In sleep-mode/tunable cryptography, FD-SOI allows the creation of physically secure systems. (Note that designers are leveraging FD-SOI’s unique body biasing for ultra-low-power deep-sleep modes.) Because safety and privacy require a combined solution, Securyzer is particularly well-suited to IoT chips built on FD-SOI, he concluded, so that IoT adds value to AI, and not just the other way around.Soitec: FD-SOI – The 5th Gear for mm-Wave Radio (Michael Reiha, GM FD-SOI Business Unit) There are four key areas to 5G, explained Michael Reiha: coverage, number of antennas, frequency and traffic density. 5G mmW access architectures are currently inefficient in terms of power and performance, but FD-SOI is ready for 5G access as both an analog and hybrid beamformer. For MU-mMIMO (massive MIMO), the RF front-end modules (FEMs) and transceiver will fully exploit FD-SOI. Sensing, calibration and control enabling hybrid beamforming and multiple users is easy in FD-SOI. The adaptive body biasing on the horizon will reduce power of FEM mixed-signal circuitry, and be a disruptive technology.STMicroelectronics – Automotive MCUs in 28nm FD-SOI for ePCM NVM (Shan-Lin Liu, Automotive Marketing Manager) As a leader in the automotive market, ST has seen that increased data flows in automotive are driving demand for higher performance and bigger memory in automotive MCUs, said Shan-Lin Liu. ST has taken a unique approach to NVM with embedded PCM (phase change memory) on 28nm FD-SOI. This gives them energy-efficient, high-performance cores with larger NVM memories, and it’s already qualified up to auto grade-0. PCM (vs MRAM) is BEOL. It uses two cells, so it’s more reliable and is good at high temperatures, he said. With FD-SOI, they can go up to 165o, and it’s soldering compliant. The preliminary results of the first MCU chip are excellent. It’s now running in a car, replacing the previous generation 40nm eFlash product.Leti – Advanced FD-SOI for Edge AI (Emmanuel Sabonnadiere, CEO) To fully run artificial intelligence on the edge, research powerhouse Leti is working on an unsupervised learning neural network using advanced FD-SOI and a mix of other technologies. These include embedded non-volatile memory (NVM), 3D integration, and new design tools. Sabonnadière said this new approach is expected to exceed the performance levels of current digital deep learning with neural networks that are capable of handling time-domain signals, sound and speech—and may produce a first "killer app" for advanced SOI. AI will require compact and power-efficient circuits for the inference phase, when neural networks infer things based on new data they receive, close to the end user. The combination of FD-SOI, 3D integration, and NVM opens a path towards dedicated circuits with major performance improvement within the limited power budgets of distributed electronics. In Europe, he noted, privacy concerns are driving the move from the cloud to the edge. On the Leti roadmap, they’ve broken through the 10nm limit for FD-SOI, using strain and body biasing to compensate for transistor mismatch. Also of note: since 2016 Leti has had an ongoing collaboration with SITRI, the Shanghai Industrial μTechnology Research Institute, an international innovation center focused on globally accelerating the innovation and commercialization of More than Moore technologies to power IoT.GlobalFoundries – GF Fab 1 Dresden: Delivering Differentiation with FDX for the Future of Automotive (Thomas Morgenstern, SVP GM Fab 1) Dresden Fab 1, Thomas Morgenstern reminded the audience, is the biggest in Europe, where it is part of the Saxony ecosystem. GF is moving advanced mask-making to Dresden, which is the lead site and Center of Competence for FD-SOI. With the “pivot”, GF is providing platforms. Fab 1 is automotive certified for 22FDX (GF’s 22nm FD-SOI technology), with automotive tapeouts in 2019. “Automotive is a journey,” he said, of continuous improvement, and a mindset: it’s a zero defects culture. The ramp to volume production is well underway, with 26 tapeouts of 22FDX products this year – almost double that of last year. He showed high yield data of about a dozen products, adding that since the beginning of the year every tapeout was first-time right with decreased cycle time. The key specifications for 22FDX with eMRAM for Auto Grade-1 have all been demonstrated, and customer feedback has been excellent.Next: Shanghai International RF-SOI Workshop recap As you can see, it was a packed day for the FD-SOI part of the SOI Consortium’s Shanghai event. In fact the room was still packed at the very end of the day. Several hundred VIPs then headed out for the ever-popular and festive evening riverboat dinner cruise, where the non-stop networking continued.A big shout-out to our sponsors and supporters: VeriSilicon, Simgui, SIMIT, Soitec, Samsung, IBS Ion Implant, ShinEtsu, GlobalFoundries and NXP.The next day of the event was devoted to RF-SOI. That will be the subject of our next post.

ASN had a chance to talk to François Brunier of Soitec, who’s leading this important project.Advanced Substrate News (ASN): Can you tell us briefly about OCEAN12?Francois Brunier (FB): OCEAN12 stands for Opportunity to Carry European Autonomous driviNg further with FD-SOI technology up to the 12nm node.Francois Brunier, Partnership Program Manager, Soitec.OCEAN12 deals with “Ultra-low power computing solutions for automotive and aeronautics using all the range of FDSOI technologies”. This project with a budget of 103M€ brings together 27 partners from 7 different countries. The project received the ECSEL JU* label under the 2017 call. ECSEL is an EU-driven public-private partnership enabling the co-financing of innovation in electronic components and systems both by Member States and the European Union.ASN: Why is this project needed?FB: As of today a car has around 500 million transistors. These electronic components represent already an important vector of valorization and differentiation for the automotive industry and for the consumer. The increased autonomy of the vehicles will require a very strong build-up of computational capacities. 50 to 100 times more transistors could be required for a level 5 (fully autonomous car). Following this trend an autonomous car will require power consumption equivalent to 50 to 100 computers running continuously (without taking into account the car propulsion).The OCEAN12 partners.The power consumption of these components becomes a key element in the choice of technologies. We believe that our technologies on SOI present the best assets to meet this challenge.The FD-SOI substrates, technologies and designs developed in OCEAN12 offer a palate of different solutions to this challenge: increased performance for data processing (including Artificial Intelligence); much higher energetic efficiency; and smaller form factors to fit in embedded systems like autonomous cars with higher integration and reliability, and enabling safe connectivity.The OCEAN12 project will demonstrate that SOI technologies are able to meet these challenges through relevant demonstrators in the targeted fields.ASN: What are the project goals?FB: OCEAN12 will bring concrete solutions to the main challenges of smart connectivity and low power consumption in the automotive industry.As such, OCEAN12 will build awareness around the key enabling technologies in substrate development, transistor behavior, and the design and fabrication of integrated circuits up to the system and end-user application levels. We will show that the technology is advantageous for automotive and aerospace applications, which are strategic sectors for Europe. Having the whole supply chain in Europe means having trusted and secured components made in Europe.The OCEAN12 project goals stand on three pillars:First: Confirming the technology foundation. Ocean12 puts the FD-SOI substrate and device developers in direct contact with the full value chain of suppliers and end users. This gives the entire ecosystem visibility into current and future needs, and ensures that substrate and device solutions are both technically feasible and correctly aligned with actual system requirements.Second: Creating concrete, innovative demonstrators in automotive (Audi, Bosch) and aeronautics (Airbus, Thales). These demonstrators are a first step in defining the context and environment to prove the advantages of these technologies in real application cases, showing they are useful and as such prefigure a final system and a potential future product roadmap. Demonstrators should be as close as possible to the final application.Third: Broadening the design ecosystem, with the big companies, the small- and medium-sized companies (SMEs) and the research organizations (universities, RTOs). We have a critical mass of 16 design ecosystem partners focusing their efforts on FD-SOI. The project leverages that dynamic FD-SOI design ecosystem for IC product migration to FD-SOI and the creation of new IP. Inventing the future components in Europe is also key.ASN: Can you tell us more about the demonstrators? When will we see them?FB: There are four demonstrators. All these demonstrators will be delivered by the end of the project in 2021:Always-on wake-up systems (Audi, Bosch, Leti). With such a system we can imagine an application to monitor our car when it is parked in a parking lot for a long time. The sensors would remain aware of everything that goes on around the car. Based on sensor observations, the car can make decisions on further actions to take. This can be used in many future car applications like intrusion detection or vehicle access systems. But you will not have to worry about battery drain: even though all the sensors are always on, they go right back into a very low-power sleep mode thanks to FD-SOI technology.mm-Wave integrated radar SOCs (Bosch and Audi), which will benefit from all the innovations of FD-SOI thanks to its low consumption properties, but also the optimization of the sensors. The performance gain is made over the entire system with adaptations between analog and logic.High-performance video processor for aeronautics. (Airbus, Thales, Kalray). Kalray, a French SME working on Massively Parallel Processor Arrays (MPPA) aims to demonstrate an ultra-low power, low-cost, high-performance neural processor on FD-SOI technology. This demonstrator would be key for Airbus and drones with high-performance, low-power cameras. Airbus and Audi have partnered on air and ground mobility services.Microcontroller plug-and-play board. This demonstrator lead by ST will allow for the development of new solutions in the domain of GNSS/GPS.ASN: Can you tell us more about the partners?FB: The OCEAN12 consortium of 27 partners involves 8 large groups, 9 SMEs and 10 universities/RTOs. These partners come from 7 different European countries.The eight large groups include: Soitec, the world’s leading provider of FD-SOI substrates; EVG, a leading global equipment supplier; GlobalFoundries and STMicroelectronics, the two major European FD-SOI foundries; and Bosch, as a Tier 1 automotive supplier. At the top of the value chain, high-end European automotive manufacturer Audi, the avionics industrial giant Airbus, and Thales for security issues, will develop product demonstrations.Ten highest-level research institutes support the industrial consortium. They include CEA-Leti (FR), Fraunhofer(GE), IMS (FR), INP Grenoble (FR), TU Dresden (GE), U. Paderborn (GE), Bundeswehr U. Munich (GE), Eberhard Karls U. Tübingen (GE), Instituto de Telecomunicações (PT), and Warsaw UT (PL). They increase the competitiveness through technological innovation and transfer of technical know-how while gaining new expertise working with global leaders.In addition, OCEAN 12 has a very strong SME consortium covering the supply chain in the fields of new equipment, IP, system integration and fabless companies. They include: IBS, UnitySC (HSEB), MunEDA, Kalray, AED Engineering, ISD, EVOTEL, M3 Systems and Design Reuse.All these partners have longstanding experience of cooperation in various national and international frameworks and are specialists in their fields of activity. Their contributions are essential for the success of the project.ASN: What is the timetable?The OCEAN12 kick-off event at Soitec’s headquarters near Grenoble.FB: The project started on April 1st 2018. The kick off with all the partners was held at Soitec on 29 September 2018. It was a great success. The project runs through December 2021, by which point everything has to be demonstrated.ASN: Can you clarify the funding structure?FB: The budget is about €103.6M. If the project succeeds, we get European Commission funding. In that case, just over 20% of the eligible cost – about €23M – is subsidized at the European level. The seven countries with companies or organizations participating in the project will then roughly match the European subsidies, contributing about €27M. These ECSEL-type public-private projects are a tried and true model in Europe, maximizing synergy across ecosystems. To conclude, in the name of the consortium I’d like to thank the ECSEL JU, the European Commission and our National Funding Agencies from France (DGE), Germany, Portugal, Greece, Spain, Austria and Poland. Such a project would not exist without them.______*ECSEL JU: Electronic Components and Systems for European Leadership Joint Undertaking

2019 will be a busy fall for the SOI Consortium and our members.First off are the SOI Consortium events in Shanghai and Tokyo, which are very popular indeed. We now have the dates locations locked in, so you’ll want to mark your calendars:Shanghai: 16 17 September 2019, FD-SOI Forum / RF-SOI Workshop. Both days will be held at the Pudong Shangri-La Hotel in Shanghai. The first day will focus on FD-SOI. The second day is all about 5G and RF-SOI. These are huge events – to get an idea of the magnitude, you can read our coverage of the 2018 event. Tokyo: 30 31 October 2019, Japan SOI Design Workshops. This year both days of workshops will take place in the Yokohama Landmark tower. The first day will be devoted to FD-SOI; the second day turns to More-Than-Moore – especially photonics and MEMS. Last year’s workshops were packed with excellent presentations and panel discussions, which we covered here. The SOI Consortium and members will also be giving talks at Semicon Europa, which is being held 13 – 15 November 2019 in Munich, Germany. The programs are currently being finalized. As soon as they’re ready, we’ll be sure to let you know so you can register and/or share the news with your colleagues and clients. But in the meantime, make sure you save the dates.Would you like to check out the presentations given at Consortium events in previous years? If you hover your cursor over the Events tab at the top of our home page, you’ll get a drop-down menu of events for the last five years (we’re working on adding more – we’ve been doing these events for over a decade!). Click through to any past event and you’ll land on a page where you can download most of the presentations that were given there. Of if you’re looking for past presentations given by any particular company, use the search engine at the bottom of any page on our website. S3SYou’ll also find many of our members at the IEEE/EDS S3S Conference in San Jose, CA, October 14 – 19th. S3S (formerly known as The SOI Conference) has been running in various forms for over 30 years. They always have an excellent line-up of speakers, plus it’s a great opportunity for networking with researchers from across the worldwide SOI ecosystem. BTW, while the deadline for general paper selection has already closed, papers of exceptional merit are currently being accepted for their Late News Sessions. See the 2019 Call for Papers for more information – those Late News papers need to be received by 23 August 2019 for consideration. Also, IEEE S3S Conference will once again host a full-day short course and a half day tutorial. These are very popular. The short course this year will be on SOI Design and Technology for Analog and Mixed Signal. As of this writing, the program is still being finalized, but more will be announced in the next few weeks, so check back on their website soon for updated information.Member EventsAnd finally, don’t forget to learn more about the offerings from and in support of the SOI ecosystem at our members’ events around the globe, including: GlobalFoundries – GTC | Samsung Foundry – SFF | ST – Technology Tour | Synopsys – SNUG | Cadence – CDNLive | Silvaco – SURGE | Arm – TechCon | NXP – Tech Days | Leti – Events | imec -Events |

If you’re going to Semicon West this year, be sure to attend the SOI Consortium’s workshop on how IoT is driving the SOI supply chain. There’s a great line-up of speakers – see the program below. IoT means many things to many people but everyone agrees it’s here and growing quickly. IoT, including machine learning and movement to the edge, is fueling innovation as the high compute and ultra-low energy requirements are pushing technology to deliver on these needs. The well-known characteristics defining IoT of “Sense”, “Compute”, and “Act” put additional burden on technology to full these requirements across a variety of use cases and environments without sacrificing reliability or quality. All the various forms of SOI technology from FD-SOI to High-Voltage to RF-SOI, are uniquely situated to deliver on the promise of today’s as well as tomorrow’s IoT roadmap. The supply chain for all forms of SOI technology is in place. This workshop will discuss the current and future solutions from a supply chain perspective.Speakers include experts from SOI Consortium members Applied Materials, NXP, GlobalFoundries and Soitec.Entitled The Internet of Things, Driver of the SOI Supply Chain, the workshop will take place at the Moscone Center South, Wednesday July 10th in Room 301. It will run from 1 pm until 4:30 pm. Anyone and everyone who is registered for Semicon West is welcome. Here is the sign-up page.It’s a great program: 1:00pm - Welcome by Semi1:10pm - IoT/AI/Edge Market – Using SOI Through-out, Jon Cheek, Senior Director, NXP1:35pm - The SOI Opportunity, Manish Hemkar, Director, Semiconductor Products Group, Applied Materials2:00pm - The Foundry IP Ecosystem, Jamie Schaeffer, Sr. Director, GlobalFoundries2:25pm - Engineered Substrates - Enabling the IoT Revolutions, Eunseok Park, Director, Emerging Technology in Strategic Marketing, Soitec 2:50pm - Enabling the SOI Era, Thomas Uhrmann, Head of Business Development, EVG3:15pm - Panel: The Internet of Things, Driver of the SOI Supply Chain, Moderator: Carlos Mazure, Chairman, SOI Industry Consortium. Panelists include:Manish Hemkar, Director, AMATYoshio Kitahara, President Managing Director, Kokusai EuropeThomas Uhrmann, Head of Business Development, EVGJon Cheek, Sr. Director, NXPThomas Piliszczuk, EVP Strategy, SoitecJon Kretzschmar, Manager of Product Sales Marketing, TEL America4:05pm - Closing remarks, Carlos Mazure, Chairman, SOI Industry Consortium4:20pm - EndThis is a great chance to learn more about SOI and the SOI Consortium. Don’t miss it!And while you’re at West, you should also check out a related event. SOI Consortium member Leti will be teaming up with Fraunhofer for a workshop entitled New Paradigms in Microelectronics–Providing R D for the 21st Century. That happens at the nearby W Hotel in San Francisco on Tuesday, July 9th at 5:00pm. Click here for more information on that.

The SOI Consortium and member companies had a significant presence at two important events in China recently: the World Semiconductor Congress (WCS) in Nanjing and the SOI Academy, including an FD-SOI Training Day in Shanghai. Nanjing is especially known as a leading RF chip design hub in China, but WCS went well beyond RF. The three-day 2019 event was held at the Nanjing International Expo Center. It attracted over 30,000 visitors, 5000 of whom attended the various summit forums. Presenting at WCS '19 in Nanjing (clockwise from top left): Wayne Dai, CEO/Founder, VeriSilicon; Carlos Mazure, Executive Director, SOI Consortium; Giorgio Cesana, Director, STMicroelectronics; Christophe Tretz, Design Expert, SOI Consortium. (Photos courtesy: WCS)The SOI Consortium organized the SOI Forum, which was part of an afternoon Innovation Summit. Presentations were given by members of the SOI Consortium team, and by leaders from our membership, including Simgui, NXP, Incize, ST, IBM, Cadence and Xpeedic. Some of those presentations are now available from our website -- click here to get them.Earlier in the day, SOI Consortium member VeriSilicon participated in a morning session on AI and IoT Wireless Communications. They presented their low-power Bluetooth design platform for GlobalFoundries 22FDX, and CEO Wayne Dai moderated a lively round-table discussion.Following hard on the heels of the Nanjing event, the SOI Consortium team and members headed to Shanghai for the SOI Academy 2019, hosted for the second year in a row by member SIMIT (Shanghai Institute of Microsystem and IT under the Chinese Academy of Sciences). The two-day event attracted more than 250 professionals from more than 100 domestic and foreign IC companies and research institutes. Keynotes by SOI Consortium Executive Director Carlos Mazure, SITRI CEO Mark Ding and Jean-Eric Michallet, Head of the Microelectronics Components Department at Leti and bizdev director for the SOI Consortium focused on the SOI ecosystem. The SITRI and Leti talks also gave updates on their research and industrialization alliance. Further talks were given by leaders from Soitec, GlobalFoundries, VeriSilicon, IBM and Xpeedic. These addressed the growing FD-SOI ecosystem, applications in automotive electronics, 22 nm and 10 nm FD-SOI devices, advanced SOI substrate technology, China’s FD-SOI development, the FD-SOI manufacturing process, product design, EDA tools and all aspects of industry’s software and modeling value chain.Several speakers noted that more and more local Chinese customers are actively adopting FD-SOI for low-power, high-performance chips. SOI Academy, Shanghai, 2019, FD-SOI Training Day attendees.(Photo credit: SIMIT)The second day was devoted to hands-on professional training, given by experts from Leti using an actual PDK and punctuated by in-depth discussions. This helped the IC designers to fully understand the advantages and flexibility of FD-SOI in low-power logic, analog/mixed-signal and RF. All in all, “It was a great success,” concluded Jean-Eric MICHALLET, Head of the Microelectronics Components Department at Leti and bizdev director for the SOI Consortium. Plans for the next SOI Academy are already underway, with plans to extend the topics to include more on photonics, RF, power and MEMS.

Why FD-SOI? What can you do with it that you couldn’t do before? That was the big question from IHS Markit’s Matthew Short that kicked off the first panel discussion at the SOI Consortium’s Silicon Valley Symposium. And there were some great answers.VeriSilicon, Analog Bits and Silicon Catalyst were among the consortium members with stands at the SOI Symposium, Silicon Valley 2019.Here in this final part of our coverage of the event, we’ll detail who said what in the two panel discussions, as well as the presentations by Leti, Intento Design the SOI Consortium’s IP/EDA roundup.If you missed the previous two installments of our coverage, you can catch up on the rest of the presentations in part 1 (NXP, Samsung more) here and part 2 here (Synaptics, GlobalFoundries more). Almost all of the presentations are now freely available under "events" on the consortium website - or just click here to get them.How FD-SOI Changes What You Can DoThe presentation by Matthew Short, Sr. Director of IoT Technology at IHS Markit, was not specific to SOI, but it sure did lay out out the market opportunities. Entitled IoT, 5G, ADAS and AI Market, it’s available on our website. Matt spent most of his career in chip design at NXP/Freescale, so he really has an engineer’s perspective on where this all is going. At IHS Markit, they define IoT as anything with an IP address. Over the past year more than 10 billion devices were shipped, and there were more “things” than cellular handsets, so the world has really changed. He outlined the growth drivers, suggested that 5G won’t be a “wow” thing for consumers, and noted there is a lot of debate raging regarding how smart sensors should be (the Tier 1’s want smart).He was then joined on the stage by the participants in the first panel discussion, which looked at product and application drivers. That included: NXP Fellow Rob Cosaro; Tim Dry, Director of Edge Endpoints Marketing at Samsung Foundry; ST biz dev director Roger Forchhammer; CoreAVI biz dev VP Lee Melatti; Nokia VP Michael Reiha; and Analog Bits EVP Mahesh Tirupattur.First Short asked why customers wanted more integrated solutions. For CoreAvi, it’s about safety, for ST in automotive it’s about security, for Analog Bits, it’s about integrating more analog, for Nokia it’s just a necessity.Then he asked Why FD-SOI? What can you do that you couldn’t do before? For ST, which is doing MCUs for automotive, it’s about energy efficiency, speed, the density of non-volatile memory and the robustness of the technology. For NXP, it’s back biasing, low voltage and power numbers never seen before. “FD-SOI really makes a difference in the products we can bring to market,” said Cosaro. For CoreAVI, it’s the long-term power impact. And for Analog Bits, “Customers see huge benefits,” said Tirupattur, for cost sensitive applications. He has customers selling their technology in high volumes in FD-SOI. What about edge vs. cloud? For Nokia, it’s monolithic integration for best-in-class RF, advanced memory, biasing and voltage regulation adding a layer of intelligence. Samsung sees edge as distributed cloud, and CoreAVI sees safety in the edge, because you can’t completely rely on the cloud.Where are the weak points in the FD-SOI ecosystem? For Samsung, more people need to use back biasing. “People need to use the knobs,” said Dry. For Analog Bits, the next step is innovation around back biasing, as many in logic don’t understand the benefits, so the ecosystem needs to promote the value proposition. ST suggests that with more products out there, customers will see the benefits. NXP did “a lot of the heavy lifting” at 28nm – now you need more people using these nodes, not just the cellphone nodes.How will the architecture change? For NXP, it’s all about memory bandwidth. For Samsung, it’s the promise of analog and interconnect. Nokia sees the back-end and heterogeneous integration with FD-SOI and RF enablement. Analog Bits’ Tirupattur said he’s pushing his engineers for even lower power in a still smaller form factor, noting that most analog engineers had been more focused on performance than power, but now that’s changed. For ST, it’s AI/ML throughout automotive, and FD-SOI is beneficial there.Leti the Connected Car Leti's slide 27, SOI Symposium, Silicon Valley 2019Research giant Leti’s presentation was entitled Applications Around the Connected Car. 85% of Leti’s €315M budget comes from R D contracts with its 350 industrial partners. Truly a driving force in FD-SOI, Leti is involved in a dizzying array of projects. For the connected car, they cover (much of it on SOI): high precision smart sensing, embedded processing fusion, new computing paradigms and deep learning, ultra-low power computing nodes framework, ultra-low power connectivity for IoT, energy management and scavenging, and security. They do vision at the edge, 3D technology for smart imagers, and ways to dramatically reduce power. They’ve got a Qbits platform on FD-SOI for AI at the edge, a super low power neural network accelerator, and ULP connectivity. Check out the presentation for lots of details.EDA/IP OverviewSlide 9 from SOI EDA/IP Overview.SOI Consortium Executive Co-Director Jon Cheek gave a quick round-up presentation aggregating various IP and EDA offerings entitled , SOI EDA/IP Overview. It is taken from recent member presentations including Cadence, Silvaco, VeriSilicon, Synopsys and GlobalFoundries, giving you an idea of how dynamic the ecosystem has become.Automating Analog While the logic side of the design equation has long had robust automation tools, some consider the analog side as sort of black magic. New consortium member Intento Design aims to fix that. Here at ASN we covered their work with ST briefly a few months ago here. At the SOI Symposium, the company’s CEO Dr. Ramy ISKANDER presented their solution in ID-XploreTM: A Disruptive EDA for Emerging FDSOI Applications. Intento, a partner in GlobalFoundries FDXcelerator program, has cognitive software for first-time right analog design. It determines the appropriate static and dynamic body biasing ranges to meet PVTB (Process/Voltage/Temperature/Body Bias), and is fully integrated into the Cadence Environment. They produced multiple correct-by-construction FD-SOI designs, and the total time spent to generate eight candidates FD-SOI designs took less than a day. The Tools Are in the BoxThe last panel discussion, entitled Are the Tools in the Box? was moderated by the Consortium’s Jon Cheek. Participants included: VeriSilicon SVP David Jarmon; Arm PDG Marketing VP Kelvin Low; NXP’s Stefano Pietri, Technical Director of the company’s Microcontrollers Analog Design Team; Jamie Schaeffer, who’s GF’s Sr. Product Offering Manager for 22FDX and 12FDX; and Cadence Strategic Alliances Director Jonathan Smith. 2nd panel discussion, SOI Symposium, Silicon Valley 2019Yes, the tools are in the box. Smith of Cadence said they’re providing them, and NXP’s Pietro said that they’re very well positioned in his specialty, analog. VeriSilicon has IP, and anything they don’t have in house they’ll license. So why be afraid of body biasing? NXP has proof by example – they see such huge cost advantages that they try to leverage it as much as possible. GF’s doing training, since each area (automotive, IoT, etc.) has different needs. Some VeriSilicon customers already see such substantial benefits from FD-SOI that they’re not bothering to do biasing. Cadence points out that the Arm POP announcement is huge, and Arm’s Low wondered if the SOI Consortium could do an IP portal? “Our sales departments need to explain the advantages to our customers!” said NXP’s Pietro.From the audience, NXP VP longtime FD-SOI proponent Ron Martino (who, btw, wrote some great articles for ASN when they first got into FD-SOI – read them here), asked why designers think FD-SOI means a lot of corners? How do we convince the industry that FD-SOI simplifies design? Cadence is working with GF, responded Smith, and will have some big new at Arm’s TechCon this fall. “We need more training and marketing to show it’s not scary," he added. For GF, the corners don’t get more complicated, and they’re working with Dolphin Integration on getting them covered early in the planning. Ease of access to IP will help, per Arm. And in a great concluding remark, VeriSilicon’s Jarmon said, “The craft is being automated. The more we work together, the greater success of FD-SOI.”