wafers

With the CAGR for switches in cell-phone RF front-end modules running at 9% for the next five years, new players want to get in on the action, and established players want to up the ante. The specialists at Incize help wafer suppliers, foundries and fabless companies maximize switch performance starting at the substrate level. CEO Mostafa Emam explains how.SOI News (SN): Can you tell us about the role Incize plays in the RF-SOI ecosystem? [caption id="attachment_32519" align="alignright" width="140"] Incize CEO Mostafa Emam. (Photo courtesy: Incize)[/caption] Mostafa Emam (ME): Our clients are wafer suppliers, foundries and fabless companies. The services we offer are testing and modeling of substrates, with the vision of what will happen in the value chain. Based on what the customer will do with the substrates, we do testing and modeling to improve the technology and tune their processes. Although the big players have teams devoted to this, we can add a layer of characterization that they have no expertise in. Some of our customers are foundries that have been using bulk silicon, but now see opportunities in RF-SOI. But they’re starting from scratch and we help them to adopt the technology. We help them understand the physics behind the technology so they can migrate from bulk to SOI. We help them develop test structures and evaluate their technology. Then we create models for both fully-depleted and partially-depleted SOI with PD-SOI 130 nm or 60 nm technology dominating the RF front-end module market. We believe RF is an art and you need to see the whole picture. SN: Can you tell us a bit about the history of Incize? ME: The RF-SOI story started in the 1990s. Then came trap-rich RF-SOI wafers from Jean-Pierre Raskin’s team at UC Louvain, industrialized by Soitec. Our lab at UC Louvain became known for our expertise in RF-SOI, and in 2011 we created Incize as a spin-off. [Editor's note: for more background, see this SOI Consortium article about the birth of trap-rich substrates and the company’s founding.] At first our characterization services were very diverse, but by 2014 we focused mostly on RF-SOI because of the big demand. In 2015 we started doing radiation hardness tests for space applications and a new business unit was created. In 2016 we started our modeling and PDK activity, followed the next year by work on GaN on Si. In 2018, we started offering full support to RF-SOI newcomers, who were starting from scratch, usually smaller players in the RF market. It takes about two years to fully train the engineers, support the technology enhancements, design test vehicles, measure them and finally do the modeling and PDK. So some of these players are now fully established in the RF-SOI market and have contracts in place with big customers. SN: In your presentations, you often say there is room for all. What do you mean by that? ME: There is a big market for RF-SOI in the coming years. It can offer the low-power, the low-cost and the high performance. RF-SOI is the only mature technology that combines all of this today. It successfully competes with traditional III-V technology. More foundries want to employ RF-SOI. We show to them that it’s not black magic – you just need to know how it works. [bctt tweet="There is a big market for RF-SOI in the coming years. More foundries want to employ #RFSOI. We show them that it’s not black magic – you just need to know how it works. - Incize CEO Mostafa Emam #5G #semiconductors" username="@soiconsortium"] On our side, we have the knowledge and the infrastructure. Our added value is that we can do advanced tests the customers can’t do. So the foundry says there’s opportunities in switches, we’ll do this and develop it all with optimization for specific Ron and Coff [the figure of merit for RF switches]. The foundry develops an RF switch and aiming at certain performance (RonCoff). We help our customers during this development phase. Once the performance target is reached we start developing a model and a PDK. There is enough demand for RF-SOI, as even entry-level cell phones have SOI chips. Some opt for a fast and low-cost solution. Many target “good enough”, although some target to compete against the big players – it’s a question of their business strategy. And this is where our added value comes in. SN: Can you provide some more insight into how you see the RF market? ME: The Front End Module (FEM) is a fast growing market, with increasing demand in terms of volume and performance. This includes antenna switches, LNAs, tuners, filters, etc. Historically, III-V materials have been used for their high performance and high power handling. However, RF-SOI has become the material of choice, and the biggest driver is integration of the RF switch and LNAs in one chip. It’s not easy to integrate the power amplifiers (PAs) on the same chip (still being on III-V substrates). But as it decreases footprint and cost, there are those who’ll do it. There is no viable competition for SOI – nothing will replace it in the short term. There are other technologies, but they are long term. It’s a stable market with high demand. SN: For those of us who are not RF experts, can you help us understand the technology? ME: The switch is sort of the traffic light of the FEM, receiving and transmitting. The simplest RF switch can be composed of only four transistors. Transistors leak power so you need to determine your Ron Coff performance. [Editor's note: Resistance on vs. Capacitance off, the RF switch figure of merit, is measured in femtoseconds and should be as low as possible. Psemi has a good video explaining it.] When the Coff capacitance is small, the switch is really off. When the On resistance Ron is small, it means low losses, and the switch is turned On. Ron and Coff is a compromise. And as there are many frequency bands and antennas, the FEM becomes very complex. Another issue is power handling, since the switch is the first stage behind the antenna. And finally, there is the question of switch linearity. Trap rich SOI wafers suppress harmonics so you have less distortion originating in the substrate. You have to model this – the designer needs to know. In addition to single tone harmonics you also get intermodulation, where, two or more high power signals at two different frequencies create distortion at other frequencies. The danger is that these parasitic signals can be so close that the filter can’t reject them and the useful signals get distorted. This was a killer for the switch created on the bulk substrate. Trap-rich RF-SOI fixed this. So now 100% of switches are on trap-rich SOI substrates. While it’s still a niche market, there is demand from customers for increasing the number of bands – that’s driving this market. SN: And what happens as we move to 5G? ME: There’s more and more pressure on the specs. It’s an art when anything changes. Moving from 3G to 4G required complete upgrade of the [foundry’s] models. With 4G, the specs are severe and the FEM must be built on trap-rich substrates. But 5G is not well defined, so the RF industry is taking their best shot. What is clear: the performance requirements get more challenging. Once the technology is understood, it can be implemented. But the foundries and the fabless need our help to do it fast and do it well. We create more value working together. SN: How do you see things evolving? ME: The number of foundries today doing switches on RF-SOI is increasing, and this will continue for the next few years. We saw this opportunity and invested in it. Our company is just ten people, and we are self-funded. We are swimming in business, but we have fun. And we’re getting recognition. Any company with CMOS in place could adopt RF-SOI. But it’s a different mindset. We help with the transition. ~ ~ ~Click here to read more feature articles in SOI News.

It should really be called SOI photonics – not just silicon photonics, quipped Soitec CTO Christophe Maleville at the SOI Consortium Japan event last fall. You’ve got to have SOI for the waveguides. There are megatrends driving significant growth in photonics – and they were all covered at the event. This is the final post in our coverage of the SOI Consortium’s Japan event (thank you for your patience!). It covers the photonics-related presentations by Soitec, Leti, Cisco/Luxtera, GlobalFoundries, Cadence and TowerJazz. Most of these presentations are now posted on the SOI Consortium website – you can access them if your organization is a member of the consortium. By way of reminder, the Japan SOI Symposium was a great success, with both days well attended. In case you missed our previous posts about the event, you’ll want to go back and read them, too. The first post covered the 5G/RF-SOI presentations by ST, Toshiba, Incize, GF, Silvaco and Sitri – you can read it here. The second post on the event covered eight very informative presentations on SOI in IoT and automotive by NXP, Dolphin Design, Leti, Silvaco, Arm, I-fuse and Secure-IC – you can read that here. Note that you can click on any of the illustrations to see enlarged versions. And now without further ado, here are the summaries of the photonics presentations. SOI Enabling Photonics – Ecosystem and Market Outlook – by Aziz Alami-Idrissi, GM Specialty SOI, Soitec. [caption id="attachment_28773" align="alignleft" width="233"] (Courtesy: Soitec SOI Consortium)[/caption] The megatrends in SOI photonics are: 5G (for more bandwidth, HPC, edge quantum computing), data centers (for high data rate transceivers and high-switch bandwidth), sensors (lidar, gas/chemical and gyroscopes) and biosensors (especially for medical). These are driving big changes: the 44% CAGR means the market is growing from a current TAM of about 500M$ to over 4B$ in 2025. One thing that’s really interesting is the expansion of the photonics market into these new fields in the next few years. While in 2019 90% of the photonics market served data center applications (the other 10% is for long haul), in 2025 optical I/O’s will account for over a third of the photonics market TAM. The other applications making an impact include AI, quantum, lidar (which will move into high-volume manufacturing in 2024) and medical sensors (hitting high-volume in 2023). For its part, Soitec is strengthening its portfolio with 8” and 12” large product coverage, new product sampling engaged, and extended features including newer engineered layers and RF immunity. Advanced Silicon Photonic Solutions Leverage SOI Technology – Eleonore Hardy, Business Development Manager, Silicon Photonics, CEA-Leti [caption id="attachment_28769" align="alignright" width="358"] (Courtesy: Leti SOI Consortium)[/caption] Leti helps companies make photonics products they can bring to volume foundries, explained Hardy. (btw, they’re presenting 21 (!) papers – including 5 invited – at PhotonicsWest 2020. Read about that here). You want to do integrated photonics to bring down costs, reduce power consumption, and scale (for higher volumes and reduced footprint). There are essentially three substrate choices: InP, SiN or SOI. SOI uses CMOS processes, so it’s low-cost and can be used in high-density photonic integrated circuits. What about the laser? Leti has developed III-V on silicon bonding, so you can have the laser on 4” III-V with a 300mm CMOS process (this is what Intel’s doing). They’re moving to 300mm wafers, 3D and advanced packaging. While communications is the big application realm, Leti is also applying photonics in automotive, medical, environment and computing. In the computing realm she gave the example of the European QuantERA SQUARE (Silicon Photonics for Quantum Fibre Networks) project for which Leti is doing the quantum emitter for absolute security and computing, wherein the transceiver/receiver for quantum cryptography integrates a hybrid III-V on silicon pump laser. Other examples of their work include miniature, low-cost and agile lidar for automotive and industrial applications (they’re working on a beam-steering emitter for an optical phased array). GlobalFoundries Silicon Photonics Solutions for Wired Infrastructure – Anthony Yu, VP, GF [caption id="attachment_28770" align="alignleft" width="684"] (Courtesy: GlobalFoundries SOI Consortium)[/caption] GF is giving their photonics business a big push. Optical interconnects are the future, said Yu, so they’re putting a lot of money into it. With data streaming multiplying by 3x/year and a current foundry TAM of $63 billion, the opportunity is huge. Fab 10 in Fishkill runs their 90WG process on 300mm wafers. A new process, 45CLO (also on 300mm) for O and C bands is going into the Malta fab. A big focus here are optical transceivers that convert RF signals to light. They see RF on SOI in a monolithic solution is needed to serve 100Gbs applications. They’re also moving to co-packaging optics: the packing technology will surround it with photonic chiplets. Customers have indicated that pulling the signals off the chips is limited by power, so they’ve worked hard on the fiber attach with MEMS and packaging technology for co-packaging. GF relies on substrate providers for high-quality SOI, and they have a world-class development team, he concluded. Integrated Electro-Photonics Design Platform – A multi-physics, multi-fabrics system design solution – Scott Li, Sr. AE Manager of Custom IC Platform, Cadence [caption id="attachment_28771" align="alignright" width="374"] (Courtesy: Cadence SOI Consortium)[/caption] This talk focused on photonics design challenges and solutions – including the CurvyCore™-based PDK for waveguide creation modal properties calculation that Cadence will soon be announcing. It’s a math-based engine that generates complex curvy shapes to support photonics. The first design challenges, said Li, are at the circuit level: how to do the schematics. The detailing tools, timesteps management and circuit simulation need to give the user the best performance. Cadence is working in close collaboration with a company called Lumericable on this. The next set of design challenges come at layout – especially generating curvilinear layout for any shape so that there are no gaps in connections. This is where CurvyCore comes in, fully automating layout and making it easy to modify. This includes place route, DRC and LVS for curvy shapes. The final challenge is at the system level. There is work to do here, but Cadence is collaborating closely on solutions with key partners. The ultimate goal is for photonics layout and editing to be available with all the features designers get in electronics editing. Silicon Photonics for High Volume and High Performance Optical Interconnects Applications – Thierry Pinguet, Technical Leader Engineering, Cisco /Luxtera [caption id="attachment_28772" align="alignleft" width="396"] (Courtesy: Cisco/Luxtera SOI Consortium)[/caption] Over the last decade there’s been steady growth in optical high speed interconnect solutions, mainly driven by HPC, enterprise, and especially the hyperscale datacenter. The largest volumes are for intra datacenter interconnect (between servers). Now mobile applications for backhaul are also driving volume for high speed optical interconnect for 5G network implementation. ASICs and photonics are getting closer as the industry moves to put them in the same package. But everybody does silicon photonics differently (even within Cisco). Luxtera tries to use the same infrastructure as electronics, but patterning is still a challenge: it’s not 90o “Manhattan” style. The wafers are no problem – they work with leading wafer suppliers like Soitec and SEH. They have explored a “double SOI” substrate (like a mirror), which showed large insertion loss improvements in grating couplers . For the electronics and the laser (MEMS), they do a micropackage, although at one point they also did monolithic integration. For better performance, they’re moving to TSVs. A hot topic is ASIC and photonics co-packaging. You can use optical tiles, but then the light is remote, like a power supply. No matter how you do it, though, the bottom line is that silicon photonics is the only way forward for the data center. PH18: World’s First Open Commercial Silicon Photonics Process and PDK from TowerJazz – Masanobu Kumazaki, Engineer, TowerJazz. This presentation was given in Japanese without translation into English, and is not available on the consortium website. But the slides showed at the event indicated that their PH18 is the world’s first open commercial silicon photonics offering. For optical transceiver components, silicon photonics provides another opportunity for a specialty foundry. It is a high-growth market. The TowerJazz offering is 220nm SOI, and uses standard EDA tools from Synopsys, Cadence and Mentor for design flow.

Digitimes Research is predicting a doubling of the global SOI market between 2019 and 2024, "...thanks to significant expansion in applications to mobile devices, communication infrastructure, IoT devices and automotive electronics in the 5G era...". (Read the full article in Digitimes here.) Beyond the continued enormous success of SOI in front-end modules (FEMs) for RF (aka RF-SOI, which as we know is found in every smartphone on the planet), the report cites high growth specialty areas such as imaging chips for smartphones and photonics in data centers. They also predict that FD-SOI will be "massively applied" in 5G, with applications in base stations and data centers. And of course, low voltage and low power consumption will be the big drivers in IoT and wearables. All this is driving Soitec, the major SOI wafer manufacturer, to expand capacity at its facilities in France and Singapore in 2020, says the report. This is happening in strategic cooperation with Shanghai-based Simgui. As noted in ASN about a year ago, Soitec and China’s SOI wafer leader Simgui announced an enhanced partnership and increased production capacity of 200mm SOI wafers in China, securing future growth. At that time the two companies redefined their manufacturing and licensing relationship to better serve the growing global market for RF-SOI in mobile and Power-SOI in automotive and consumer electronics. Separately, Okmetic of Finland, which specializes in SOI wafers for MEMS, sensors and RF, is also doubling its capacity (we covered their 2019 Shanghai presentation here.) (Image courtesy: Soitec)

Join us! In partnership with our members, the SOI Consortium is co-organizing and participating in two key SOI events coming up in China over the next few weeks. On May 18th, we’ve put together an SOI Forum at the World Semiconductor Congress (WCS) in Nanjing. And on May 23rd 24th, we’ve teamed up with our members SIMIT, Sitri and Leti for another in our series of SOI Academies, including an FD-SOI Training Day. (The last one this past winter was a terrific success – read about that here if you missed our coverage at the time.) QR code for WCS, Nanjing '19At WCS, the SOI Forum (sub-forum #8) is part of the afternoon Innovation Summit. We’ll cover the broader SOI ecosystem, including both RF-SOI and FD-SOI – from wafers to design through manufacturing. Presentations will be given by members of the SOI Consortium team, and by leaders from our membership, including Simgui, NXP, Incize, ST, IBM, Cadence and Xpeedic. Click here or scan the QR code for the full program and registration information. Also at WCS, SOI Consortium member VeriSilicon will be participating in a morning session on AI and IoT Wireless Communications (sub-forum #4). They’ll be giving a presentation on their low-power Bluetooth design platform for GlobalFoundries 22FDX, and their CEO Wayne Dai will be moderating a round-table discussion. You can get more information on that (in Chinese only, tho) here, or follow VeriSilicon on WeChat. QR code for SOI Academy and FD-SOI Training, Shanghaid 2019The SOI Academy in Shanghai is an opportunity for experienced designers to gain solid expertise in FD-SOI. The event begins in the afternoon of May 23rd with a series of informative plenary talks by members of the SOI Consortium team, and by experts from our members Leti, Soitec, VeriSilicon, GlobalFoundries and NXP. The FD-SOI Training starts the next morning, on May 24th.. This is a hands-on event lead by top experts from Leti. The morning is devoted to digital design in FD-SOI, and the afternoon to RF design (including for 5G) in FD-SOI. Attendees will get a comprehensive understanding of design techniques for low-power chips leveraging the multiple benefits and flexibility of FD-SOI technology. Get more information here, or from the WeChat QR code.We've got a busy schedule! To keep up to date with where we and our members will be promoting the SOI ecosystem, be sure to check our Events page regularly.

[caption id="attachment_12150" align="alignright" width="252"] Manuel Sellier, Product Marketing Manager at Soitec[/caption] Manuel Sellier, Product Marketing Manager at Soitec for the FD-SOI (and some other) SOI product lines has written an absolutely terrific primer entitled FD-SOI: A technology setting new standards for IoT, automotive and mobile connectivity applications. It's in the August edition of the GSA Forum (the GSA is the Global Semiconductor Alliance). If you know anyone who needs to quickly glean an understanding of FD-SOI that is both in-depth and broad, you'll want to share this piece with them right away. Before joining Soitec, Sellier was a chip designer at ST, where he gained deep experience designing FD-SOI chips. What's more, he holds a Ph.D. in the modeling and circuit simulation of advanced MOS transistors, including FD-SOI and FinFETs. So, he really knows his stuff. But don't worry that this might be too technical: Sellier's writing is thoroughly accessible (and engaging!) for anyone in the industry. He starts with the wafer history, then quickly moves on to the features from the designer's standpoint. And he puts it all in a business perspective. I can't recommend this piece enough – even if you think you know everything already yourself, you're sure to learn something new.

Specialty foundry TowerJazz is ramping a 65nm version of its RF-SOI process on 300mm wafers at Fab 7 in Uozu, Japan. To support the ramp, the company has signed a contract with long-term partner, Soitec, guaranteeing a supply of tens of thousands of 300mm SOI silicon wafers, securing wafer prices for the next years and ensuring supply to its customers, despite a tight SOI wafer market. [caption id="attachment_12108" align="alignright" width="300"] The 300mm 65nm RF-SOI process will be offered at the Uozu, Japan fab, which is operated by the TowerJazz Panasonic Semiconductor Company (TPSCo). (Photo courtesy: TowerJazz)[/caption] Five of TJ's seven fabs do RF-SOI. LNA (low-noise amplifers) are a big market driver, and with RF-SOI they can integrate the LNA with the switch, CEO Russell Ellwanter said in his lead keynote at the SOI Consortium’s 5th International RF-SOI Workshop in Shanghai (spring, 2018). BTW, that was in fact a very inspirational talk about Value Creation, and the importance of treating your suppliers with respect. He credited his company’s close relationship with RF-SOI wafer-supplier Soitec for TJ’s claim to the world’s best linearity. “We are delighted to see the strong adoption of 300mm RF SOI through this large capacity and supply agreement with TowerJazz to augment our already significant 200mm RF-SOI partnership,” said Soitec CEO Paul Boudre. “TowerJazz was the first foundry to ramp our RFeSI products to high volume production in 200mm and continues as one of the industry leaders in innovation in this exciting RF market with advanced and differentiated offerings.” According to the TJ press release (you can read it here), with its best in class metrics the TowerJazz 65nm RF-SOI process enables the combination of low insertion loss and high power handling RF switches with options for high-performance low-noise amplifiers as well as digital integration. The process can reduce losses in an RF switch improving battery life and boosting data rates in handsets and IoT terminals. It's a high-growth market, to be sure. Market researchers Mobile Experts predict that the mobile RF front-end market will reach $22 billion in 2022 from an estimated $16 billion in 2018. TowerJazz says its breakthrough RF SOI technology continues to support this high-growth market and is well-poised to take advantage of next-generation 5G standards, which will boost data rates and provide further content growth opportunities in the coming years. Customers are already getting into position. For example, Maxscend (WuXi, China), a provider of RF components and IoT integrated circuits, is ramping in this new technology. “We chose TowerJazz for its advanced technology capabilities and its ability to deliver in high volume while continuously innovating with a strong roadmap. We specifically selected its 300mm 65nm RF SOI platform for our next-generation product line due to its superior performance, enabling low insertion loss and high power handling,” said Maxscend CEO Zhihan Xu. As longtime ASN readers will know, we've been covering the evolutions of TJ's RF-SOI platforms since the beginning of the decade. It's worth noting, too, that beyond RF, TowerJazz also offers foundry customers other SOI-based processes, such as the new 0.18μm BCD SOI, a 200V SOI technology platform (announced in 2017, press release here) for motor drivers, industrial tools, electric vehicles and more. The previous generation 0.18μm SOI for automotive power management also offers exceptional area savings and is well-suited for high temperature operation. Back in 2014, here at ASN we did a great interview with TJ SVP Dr. Marco Racanelli about when and why they use SOI – and while processes have advanced, the basic drivers are still there, so it's a still a good read. And finally, designers will want to know that the TJ Multi-Project Wafer (MPW) Shuttle Program offers the 65nm RF-SOI process, as well as other SOI-based processes. See the website for scheduling and details.

Leti and Soitec have announced a new collaboration and five-year partnership agreement to drive the R D of advanced engineered substrates, including SOI and beyond. This agreement brings the traditional Leti-Soitec partnership to a whole new dimension and includes the launch of a world-class prototyping hub associating equipment partners to pioneer with new materials, The Substrate Innovation Center will feature access to shared Leti-Soitec expertise around a focused pilot line. Key benefits for partners include access to early exploratory sampling and prototyping, collaborative analysis, and early learning at the substrate level, eventually leading to streamlined product viability and roadmap planning at the system level. [caption id="attachment_12066" align="aligncenter" width="644"] CEOs Emmanuel Sabonnadière (Leti) and Paul Boudre (Soitec) announcing the new Substrate Innovation Center during Semicon West '18. (Image courtesy: Leti)[/caption] Leading chip makers and foundries worldwide use Soitec products to manufacture chips for consumer applications targeting performance, connectivity, and efficiency with extremely low energy consumption. Applications include smart phones, data centers, automotive, imagers, and medical and industrial equipment, but this list is always growing, along with the need for flexibility to explore new applications starting at the substrate level. At the Substrate Innovation Center, located on Leti’s campus, Leti and Soitec engineers will explore and develop innovative substrate features, expanding to new fields and applications with a special focus on 4G/5G connectivity, artificial intelligence, sensors and display, automotive, photonics, and edge computing. “Material innovation and substrate engineering make entire new horizons possible. The Substrate Innovation Center will unleash the power of substrate R D collaboration beyond the typical product road maps, beyond the typical constraints,” said Paul Boudre, Soitec CEO. “The Substrate Innovation Center is a one-of-a-kind opportunity open to all industry partners within the semiconductor value chain.” Whereas a typical manufacturing facility has limited flexibility to try new solutions and cannot afford to take risks with prototyping, the mission of the Substrate Innovation Center is to become the world’s preferred hub for evaluating and designing engineered substrate solutions to address the future needs of the industry, inclusive of all the key players, from compound suppliers to product designers. Using state of the art, quality-controlled clean room facilities, and the latest industry-grade equipment and materials, Leti and Soitec engineers will conduct testing and evaluation at all levels of advanced substrate R D. “Leti and Soitec’s collaboration on SOI and differentiated materials, which extends back to Soitec’s launch in 1992, has produced innovative technologies that are vital to a wide range of consumer and industrial products and components,” said Emmanuel Sabonnadière, Leti CEO. “This new common hub at Leti’s campus marks the next step in this ongoing partnership. By jointly working with foundries, fabless, and system companies, we provide our partners with a strong edge for their future products."

RF-SOI innovators Jean-Pierre Raskin of UCL and Bernard Aspar of Soitec changed the course for key RF chips. The industry has long recognized their contributions: their solution for “trap-rich” RF-SOI wafers is now the starting point to virtually every FEM in every smart phone on the planet (really!). And of course here at ASN we've been following their work for over a decade. Now more accolades are coming in. The latest is the 2017 European SEMI Award, which was given at ISS Europe 2018 for “...their seminal work with radio frequency silicon-on-insulator (RF-SOI) substrates” (read the press release here). As SEMI notes, the “...award winners’ pioneering research and collaboration with academia and industry led to major advances in RF switches and ushered RF-SOI technology from concept to worldwide adoption.” Aspar and Raskin were nominated and selected by their peers within the international semiconductor community. [caption id="attachment_11677" align="alignleft" width="150"] Bernard Aspar, Executive Vice President, Communication Power BU at Soitec Aspar founded CEA-Leti spinoff Tracit Technologies in 2003. He was appointed senior vice president of the Tracit Division (now the Communication Power business unit) when Soitec acquired Tracit in 2006. He has more than 15 years of experience in direct wafer-bonding and layer transfer. Aspar has filed more than 35 patents and co-authored some 100 scientific articles. He holds engineering and Ph.D. degrees in materials sciences and a master’s degree in microelectronics from the University of Montpellier, France.[/caption] [caption id="attachment_11678" align="alignleft" width="150"] Jean-Pierre Raskin, professor, Université catholique de Louvain (UCL) Raskin contributed to pioneering scientific studies demonstrating that silicon-based MOS technology could enable affordable, high-quality mobile devices. His findings led to the advent of RF-SOI technology and today impact the global microelectronics industry. He is an IEEE Senior Member, EuMA Associate Member and Member of the Research Center in Micro and Nanoscopic Materials and Electronic Devices of the Université catholique de Louvain, where he has been a full professor since 2007. He is author or co-author of more than 350 scientific articles.[/caption] Their advanced RF-SOI technology is now behind a wide range of applications and systems in areas including mobile devices, satellite communications, IoT, automotive radar and aerospace. If you want to better understand all this, a few years ago UCL and Soitec teams contributed an excellent article to ASN. It clearly explains how and why these new substrates came to be. You can still read it here. (Or if you're still a little confused about RF-SOI vs. RF on FD-SOI, here's a piece we did back in 2015 that explains the basics.)

China Mobile is the world's largest* telco. So when Danni Song, one of the company's high-level project managers presented at the SOI Consortium's 5th International RF-SOI Workshop in Shanghai, you can bet people listened. With each new slide, a glowing sea of cell phone cameras rose over the heads of the audience in the huge, packed ballroom. [caption id="attachment_11612" align="alignleft" width="300"] (Photo courtesy: SOI Consortium, Simgui)[/caption] Over the last month, there's been a lot more coverage of 5G in the press (especially after the recent Mobile World Congress (MWC) – check out Junko Yoshida's EETimes piece for example). For ASN readers who want to know more about 5G and RF-SOI in China, here's a reminder that Song's presentation, and many of the others given by leading companies at the RF-SOI Workshop last fall, are now posted on and freely available the Consortium website Events page. Click here for the listing and links.The theme of the workshop was IoT, mobile, 5G connectivity, and mmW. As Dr. Xi Wang, Director General of SIMIT/CAS (the Shanghai Institute of Microsystem Information Technology in the Chinese Academy of Sciences), said in his opening keynote, China is strong in RF-SOI. RF-SOI will be growing at a CAGR of over 15% for the next five years, and China has production, design, wafer manufacturing and good momentum. “We will make a great contribution to the whole IC industry,” he predicted.Of note, too, Russell Ellwanter, CEO of TowerJazz, gave what turned out to be a very inspirational keynote about Value Creation, and the importance of treating your suppliers with respect. He credits his company's close relationship with RF-SOI wafer-supplier Soitec for TJ's claim to the world's best linearity. Five of their seven fabs do RF-SOI. LNA (low-noise amplifers) are a big market driver, and with RF-SOI they can integrate the LNA with the switch.Here are some more highlights from the day – but by all means check out the presentations for details. (You can click on the illustrations to see them in full screen.)China MobileIn her presentation, Embrace a Brand New Cooperation in 5G Era, Song asked where RF-SOI could help in her wish list. Could it increase integration and decrease cost and power consumption? Can it help improve NB-IoT device performance? The supply chain needs to come back around into a circle, so that the telcos are connected to and get insights from the wafer substrate providers, she said. [caption id="attachment_11608" align="alignright" width="300"] (Courtesy: China Mobile, SOI Consortium)[/caption] China Mobile has a 5G Innovation Center, and has established test labs in 8 cities. And the government has announced a 5G launch in 2020, with pre-commercial trials now going into 20 cities. So she was at the RF-SOI Workshop as much to listen and learn as to share China Mobile's vision.Sony [caption id="attachment_11613" align="alignleft" width="300"] (Courtesy: SOI Consortium and Sony)[/caption] The presentation by Kidetoshi Kawasaki, GM of Sony Semiconductor Solutions, focused on antenna tuning, which he said is one of the fastest growing things in cell phones. Antenna Tuning Progress SOI Single Chip Integration for 4G/5G UE (note that UE = user equipment) looks at antenna aggregation, and why it is important for carrier aggregation (CA) and MIMO. Sony has developed an SOI-based next-gen process for 5G integrating passive components. That's why RF-SOI is important and will be continued to be used in the mobile market, he said.GlobalFoundriesGF has developed demo vehicles to help customers, said Sr. Director of the RF Business Unit, Peter Rabbeni. (Over the years they've shipped over 32 billion RF-SOI devices, btw.) In his presentation, RF-SOI: Delivering Performance Integration for the Next Generation of Mobile,he noted that RF is becoming more complex than digital. As a result there is a need to integrate to help reduce cost: this is a direct correlation to the standards that are driving complexity. At the same time, performance requirements are increasing, so the challenge is driving increased performance at the same or lower cost than previous generations of products. [caption id="attachment_11609" align="alignright" width="300"] (Courtesy: GlobalFoundries and SOI Consortium)[/caption] To meet 4G/LTE and 5G's evolving performance demands, GF has recently introduced two new RF-SOI platforms, which he detailed in the presentation. 8SW enables increased integration of front-end modules (FEMs), while 45RFSOI is for mmWave FEMs. (In a separate presentation, IDDO-IC CEO Denis Masliah presented a Differential Complementary Millimeter Wave Power Amplifier for 5G using 45RFSOI process, which is currently being fabbed by GF.)RF-SOI Wafer SuppliersThe two leading RF-SOI wafer suppliers, Soitec and partner Simgui, both gave excellent presentations. Though Soitec EVP Bernard Aspar's presentation Engineered Substrates as Foundation of Innovation in RF is not posted, he made some important points. Up til now, RF-SOI has mainly been about switches and tuners, he said, but there are other opportunities that offer the potential for huge growth. The full supply chain needs to be prepared, he said, and suppliers need to understand each other. Each technology requires the right substrate – and even as we move into sub-6GHz 5G, there is still work to be done in 4G. In fact Soitec is now offering services to help customers better understand new substrate options. [caption id="attachment_11611" align="alignright" width="300"] (Courtesy: Simgui, SOI Consortium)[/caption] Soitec's partner in China, Simgui, now uses Soitec's Smart CutTM technology for RF-SOI wafer production. Together the two are now producing over a million 200mm RF-SOI wafers/year, said Simgui Sr. Director, Kerui Wang. His presentation, RF-SOI – a Secured Substrate Supply Chain, looked at their strategic partnership with Soitec, wherein they use the same tools and processes to deliver the same products meeting the same specs.Fabs and FablessTwo leading fabless companies – RDA Microelectronics (which was acquired by Spreadtrum) and SmarterMicro also presented their RF-SOI activities. Although their ppts are not posted, here are a few highlights.Longtime ASN readers will recall that RDA has been shipping high-volume, RF-SOI based chips to Samsung and others for over five years. In the presentation, RF-SOI in Current and Future RFFE Solutions, Engineering AVP Joseph Jia said that over last two years alone they've released almost 50 RFFE (front end) chips on RF-SOI. They see RF-SOI as the right match for switches, tuners and NB-IoT because of the low-voltage and tunability advantages.SmarterMicro's CTO, Peter Li, sees RF-SOI as a cornerstone of 5G. In his presentation, Reconfigurable RFFE in 5G, he said the goal is smart systems on fewer dies to decrease size and cost.Jeff Zhu, assistant director at SMIC, presented SMIC, 0.13um RF-SOI Platform Updates. Mainland China's largest foundry has recently moved its RF-SOI process from 180 to 130um, and he walked us through some chip designs.Throughout the day, presenters noted that RF is a great opportunity for China to take a leadership position. As one panelist at the end of the day noted, RF depends more on expertise and talent than digital, which depends more on manpower.Nanjing: A China RF CapitalJust before the Shanghai events, there was a 2-day event sponsored by the City of Nanjing, co-organized by SOI Industry Consortium and the City of Nanjing. Over 200 participants attended the workshop and tutorials on SOI applications, SoC development and manufacturing, EDA IP ecosystem, as well as a design tutorial for More than Moore SOI ecosystem. Almost all of those presentations are now posted on the Consortium – click here to get them.Some of the participants in the SOI Consortium's delegation also had the opportunity to visit the enormous Nanjing Sofware Park. Nanjing, we learned, is often considered China's “RF capital”. The list of the world's major RF players working in partnership there is certainly an international who's who.So, lots of good RF-SOI/5G info on the SOI Consortium website – check it out!~ ~ ~*in terms of market value and subscribers.

12nm FD-SOI has now officially joined the GlobalFoundries’ roadmap, targeting intelligent, connected systems and beating 14/16nm FinFET on performance, power consumption (by 50%!) and cost (see press release here). Customer product tape-outs are expected to begin in the first half of 2019. GloFo also announced FDXcelerator™, an ecosystem designed to give 22FDX™ SoC design a boost and reduce time-to-market for its customers (press release here). [caption id="attachment_9874" align="aligncenter" width="610"] (Courtesy: GlobalFoundries and SOI Consortium Shanghai FD-SOI Forum 2016)[/caption] The news turned heads worldwide (hundreds of publications immediately picked up the news) – and especially in China. "We are excited about the GlobalFoundries 12FDX offering and the value it can provide to customers in China," said Dr. Xi Wang, Director General, Academician of Chinese Academy of Sciences, Shanghai Institute of Microsystem and Information Technology. “Extending the FD-SOI roadmap will enable customers in markets such as mobile, IoT, and automotive to leverage the power efficiency and performance benefits of the FDX technologies to create competitive products." Wayne Dai, CEO of VeriSilicon (headquartered in Shanghai but designing for the world’s biggest names in the chip biz), added, “We look forward to extending our collaboration with GlobalFoundries on their 12FDX offering and providing high-quality, low-power and cost-effective solutions to our customers for the China market. The unique benefits of FD-SOI technologies enable us to differentiate in the automotive, IoT, mobility, and consumer market segments.” The ultra-thin FD-SOI wafers are where it all starts, and they’re ready to go in high volume, says Paul Boudre, CEO of SOI wafer leader Soitec. “We are very pleased to see a strong momentum and a very solid adoption from fabless customers in 22FDX offering,” he adds. “Now this new 12FDX offering will further expand FD-SOI market adoption. This is an amazing opportunity for our industry just in time to support a big wave of new mobile and connected applications.” All About 12GloFo’s 12FDXTM platform, which builds on the success of its 22FDXTM offering, is designed to enable the intelligent systems of tomorrow across a range of applications, from mobile computing and 5G connectivity to artificial intelligence and autonomous vehicles. Increased integration of intelligent components including wireless (RF) connectivity, non-volatile memory, and power management—all while driving ultra-low power consumption—are key 12FDX selling points that FinFETs can’t touch. The technology also provides the industry’s widest range of dynamic voltage scaling and unmatched design flexibility via software-controlled transistors—capable of delivering peak performance when and where it is needed, while balancing static and dynamic power for the ultimate in energy efficiency. [caption id="attachment_9873" align="aligncenter" width="610"] (Courtesy: GlobalFoundries and SOI Consortium Shanghai FD-SOI Forum 2016)[/caption] “Some applications require the unsurpassed performance of FinFET transistors, but the vast majority of connected devices need high levels of integration and more flexibility for performance and power consumption, at costs FinFET cannot achieve,” said GLOBALFOUNDRIES CEO Sanjay Jha. “Our 22FDX and 12FDX technologies fill a gap in the industry’s roadmap by providing an alternative path for the next generation of connected intelligent systems. And with our FDX platforms, the cost of design is significantly lower, reopening the door for advanced node migration and spurring increased innovation across the ecosystem.” Kudos came in from G. Dan Hutcheson, CEO of VLSI Research, IBS CEO Handel Jones, Linley Group Founder Linley Gwennap, Dasaradha Gude, CEO of IP/design specialists INVECAS, Leti CEO Marie Semeria and NXP VP Ron Martino (they’ve already started on 28nm FD-SOI for their i.MX line – read his superb explanations in ASN here). 22 Design Plug ‘n PlaySimultaneously to the 12FDX announcement, GloFo announced the FDXcelerator Partner Program. It creates an open framework under which selected Partners can integrate their products or services into a validated, plug and play catalog of design solutions. This level of integration allows customers to create high performance designs while minimizing development costs through access to a broad set of quality offerings, specific to 22FDX technology. The Partner ecosystem positions members and customers to take advantage of the broad adoption and accelerating growth of the FDX market.Initial partners of the FDXcelerator Partner Program are: Synopsys (EDA), Cadence (EDA), INVECAS (IP and Design Solutions), VeriSilicon (ASIC), CEA Leti (services), Dreamchip (reference solutions) and Encore Semi (services). These companies have already initiated work to deliver advanced 22FDX SoC solutions and services. Initial FDXcelerator Partners have committed a set of key offerings to the program, including: tools (EDA) that complement industry leading design flows by adding specific modules to easily leverage FDSOI body-bias differentiated features, a comprehensive library of design elements (IP), including foundation IP, interfaces and complex IP to enable foundry customers to start their designs from validated IP elements, platforms (ASIC), which allow a customer to build a complete ASIC offering on 22FDX, reference solutions (reference designs, system IP), whereby the Partner brings system level expertise in Emerging application areas, enabling customers to speed-up time to market, resources (design consultation, services), whereby Partners have trained dedicated resources to support 22FDX technology; and product packaging and test (OSAT) solutions. Additional FDXcelerator members will be announced in the following months.