Standards

With microelectronics manufacturing increasing in complexity and facing more cybersecurity threats, the SEMI International Standards Program has made crucial progress on efforts to address these challenges and others, in the first quarter of 2025. MEMS manufacturing readiness and cybersecurity came into sharp focus with the introduction of SEMI Standard MS15 - Guide to MEMS Manufacturing Readiness Levels. In addition, this quarter saw the opening of the public commentary period for a SEMI-led semiconductor manufacturing cybersecurity profile, developed for the National Institute of Standards and Technology’s (NIST) Cybersecurity Framework (CSF) 2.0. Through collaborative efforts, we held a successful North America Standards Winter Meeting in February, co-hosted a MEMS webinar, and published over 15 new and revised standards in areas such as equipment automation software, facilities, materials, and more.With exciting developments still to come, we’re looking forward to a wonderful year ahead.MEMS Manufacturing Readiness This March, SEMI unveiled its new standard, SEMI MS15 – Guide to MEMS Manufacturing Readiness Levels. This standard offers readiness level definitions, processes, and practices for creating MEMS products that meet targeted specification performance, quality, cost, and time-to-market. This standard is broken into eight distinct levels that cover basic research, all the way through high-volume production. Prior to the official release of SEMI MS15, we held a webinar that previewed how MEMS Manufacturing Readiness Levels will facilitate efficient MEMS development. Led by co-chair, Michelle Bourke of Lam Research, the SEMI MEMS Sensors Industry Group (MSIG) hosted a webinar featuring MEMS experts from SoftMEMS, HP, Teledyne MEMS, and Polar Semiconductor. Speakers shared insight into creating a structured and balanced MEMS manufacturing approach to drive successful products to commercialization. Cybersecurity Resilience Like 2024, cybersecurity remains pertinent in 2025. Last October, SEMI introduced SEMI Standard E191 and its subordinate standard, SEMI E191.1 to help define cybersecurity status information reporting. SEMI E191 and E191.1 join SEMI’s existing cybersecurity standards, SEMI E187 and E188. Last year also saw the development of the NIST CSF 2.0 Semiconductor Manufacturing Profile under SEMI’s Semiconductor Manufacturing Cybersecurity Consortium (SMCC). In partnership with NIST, SMCC advanced a community profile for CSF 2.0 that will serve as a cybersecurity framework specific to semiconductor manufacturing. The profile opened for public commentary between February 27 and May 30, with the final version slated for official release in Q3 of this year.As the semiconductor industry becomes increasingly reliant on digital technologies, we will continue to prioritize cybersecurity standards and initiatives essential for safeguarding the global supply chain.North America SEMI Standards Winter MeetingsFrom February 24 to 27 at SEMI’s headquarters, leaders from 11 committees and over 40 task forces collaborated on new and revised standards and safety guidelines for environmental, health, and safety, equipment automation and software, liquid chemicals, traceability, and more. Three SEMI Standard draft documents that were reviewed at the North America SEMI Standards Fall Meetings last November have also been approved and published. In addition to SEMI MS15, SEMI F122 – Guide for Facilities Data Package for Manufacturing Equipment Installation and Building Information Modeling, and SEMI E193 – Specification for 300 mm Film Frame FOUP (FFF), have also been approved and published. SEMI F122 suggests formats for reporting facilities data required to plan, prepare, model, and optimize a facility for the installation of manufacturing equipment by fab owners and manufacturing equipment customers. SEMI E193 drives consistent implementation of interfaces for film frame carriers that are compact and work with existing 300 mm FOUP standards and BOLTS interfaces. These standards are now available for purchase. The North America SEMI Standards Summer Meetings will take place from June 2-5 at SEMI’s Milpitas, California headquarters. Some technical committees and task forces may meet virtually outside of this meeting set – check the SEMI Standards calendar of events for updates!Standards Introduced in Q1 2025New and revised standards released in Q1. January 2025 standards: https://store-us.semi.org/collections/standards/lang-english+stdpbc-0125February 2025 standards: https://store-us.semi.org/collections/standards/lang-english+stdpbc-0225March 2025 standards: https://store-us.semi.org/collections/standards/lang-english+stdpbc-0325TestimonialsHear from Doug Suerich, Director of Marketing at PEER Group, how his work is helping shape smart manufacturing standards and global cybersecurity policies through our powerful collaborative platform. Get InvolvedSEMI Standards development activities take place throughout the year in all major manufacturing regions. To participate, join the SEMI International Standards Program.SEMI Standards are available through Individual Download purchases or online via SEMIViews. Sign up for a 30-day SEMIViews trial.For more information, please visit the Standards website and events page. For any questions regarding SEMI Standards activities, please contact your local SEMI Standards staff. Paul Trio is Director of Standards at SEMI.

Electronic Design Automation (EDA) is essential for the entire semiconductor design-to-manufacturing process. EDA tools streamline the design process, speed up development cycles, and ensure higher precision in chip design. Accellera Systems Initiative, an independent standards body, focuses on standards for system-level design, modeling and verification used extensively in the EDA ecosystem. These standards facilitate industry-wide collaboration and accelerate innovation, working closely with many members of the Electronic System Design (ESD) Alliance.Bob Smith, Executive Director of the ESD Alliance, recently talked with Lu Dai, Senior Director of Technical Standards at Qualcomm and Chair of Accellera Systems Initiative about Accellera’s new and future standards, and its successful global Design Verification Conference (DVCon) events.Smith: What’s new in Accellera’s standards effort since we last spoke?Dai: We are working on two new initiatives. The first and biggest initiative is our recently formed Federated Simulation User Group. Our members requested an end-to-end simulation environment or models that can be plugged into a system-level simulation environment. This challenge triggered industry-wide discussions among Qualcomm, NXP and many other semiconductor companies, especially those from Europe tied to auto and avionics industries.The need for this new standard effort is being driven by industries such as automotive where tiny microcontroller chips are traditionally used. The automotive industry has some existing simulation standards that include physical devices. With autonomous vehicles, systems on chips (SoCs) are replacing microcontrollers and handling system-level features that require rigorous system-level simulation. The user group is tasked with reviewing current automotive industry simulators and discovering how our traditional register transfer level (RTL) code- or emulation-based simulations could work with them via an interface.This effort has attracted new companies outside of the traditional EDA world. Ford, for example, is now an Accellera member and has a seat on our board. It’s exciting to see this collaboration.Functional safety is another initiative that we started a few years ago, also driven by the advancements in autonomous vehicles. Accellera’s focus is to define functional safety as a format that can be carried through the design stages from intellectual property (IP) to SoC, and from front-end design to back-end. Across the different stages of design and verification, an engineer can then confirm that the functional safety goal is maintained. We’ve published resources including whitepapers and are currently working on developing the language format. Smith: Where do you see Accellera’s next standards efforts?Dai: We have a mixed-signal standard coming out soon. It adds a mixed-signal interface to the SystemVerilog standard, currently under IEEE management because Accellera donated it to IEEE.A common question we’re asked is, “What are you doing with AI?” Accellera is a heavily EDA-centric standards body, and EDA tools are increasingly incorporating AI. AI consumes and outputs large amounts of data. A challenge is how to ensure the AI work output from one vendor’s EDA tool can propagate to another EDA tool. Accellera may look at defining an AI data format for EDA. It comes with a unique challenge because AI data is highly proprietary, both from the vendor’s and customer’s perspectives, so a robust security solution is needed. We may need to consider an interface standard, because companies may not be willing to share data, even with other groups that are in the same company. among their partners. They might need to hide the data and have a special interface to extract the data that they are willing to share. Accellera could investigate how to make AI deployment cross-vendor while allowing vendors and customers to protect their IP. Another area for potential new standards is around supply chain security challenges. This is a global issue driven in part by the COVID experience and geopolitical concerns. One possible approach is to use tagging. When a chip comes out of the fab, it would have a tag designating where it was designed and manufactured, and where the tooling is from. The tag would also include data about the regions or countries the design traveled through during the entire flow from design to manufacturing. Smith: Is Accellera looking into any standards or addressing any open-source design and verification flows?Lu: Accellera has been in the open-source domain for quite some time. Accellera has a language reference manual, user guides and reference implementations. Because many Accellera standards are related to language, we often work on libraries when a new language comes out and reference implementations to help our community deploy that standard. Reference implementation libraries are open source, as is our SystemC material. We have an active open-source SystemC community.Smith: I hear that the DVCon conferences are expanding globally. What’s driving that?Dai: Engineers enjoy attending conferences in person where they can reconnect with peers, build new connections and foster collaboration. We have regional DVCon events to bring information to our community and make Accellera more accessible to them. We now host several DVCon conferences in North America, Europe and Asia. Our next DVCon will be held in San Jose, Calif., from Feb. 24-27.Smith: How can readers of this blog post get more information about Accellera?Dai: For up-to-date information about Accellera’s activities, please visit our website: https://accellera.org/. Lu Dai is Senior Director of Technical Standards at Qualcomm and is a leader in semiconductor standards and industry organizations including Accellera. Dai holds a Master of Science degree in Electrical Engineering from Cornell, and a Bachelor of Science degree in Electrical Engineering and Computer Science from UC Berkeley.Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community.