imec

New pilot lines offer European innovators access to the most advanced semiconductor technologies for product development and validation.The global semiconductor landscape has undergone significant transformation in recent years. With disruptions such as the semiconductor supply chain crisis and the challenges it posed to the automotive sector, Europe’s dependence on external fabrication facilities, particularly in Taiwan, has become a pressing concern. In response, the European Union (EU) introduced the EU Chips Act, a comprehensive framework designed to reduce this reliance and boost Europe’s share of the global semiconductor market. ITF Chip into the Future, hosted by imec at SEMICON Europa 2024, was a pivotal event that brought together industry leaders, policymakers, and experts to explore the implementation of the EU Chips Act and the future of Europe’s semiconductor ecosystem. Jari Kinaret, Executive Director of the Chips Joint Undertaking (Chips JU)—the body overseeing the EU’s semiconductor investments—explained, “The Chips JU is about capacity building to drive semiconductor innovation in Europe. We will continue to be dependent on the rest of the world, but we want to make sure that the rest of the world depends on us as well.” Jari Kinaret, Executive Director, Chips JUEuropean research is driving progress towards sub-nanometer fabricationOne of the pilot lines, located at imec’s research center in Belgium, is focused on advancing methods that push Moore’s Law forward by achieving smaller and more efficient circuit features. As Luc Van den hove, President and CEO of imec, explained, “imec is now powering innovation for tomorrow’s chip designs, including stacked layers of chips, with each layer containing specific functionality implemented on chip processes optimized for each function. This allows us to scale much further than if all functionality had to be implemented on a single monolithic layer.”Luc Van den hove, President and CEO, imec Another pilot line, based in France and operated by CEA-Leti, is focused on pushing the limits of technology across multiple dimensions. CEA-Leti CEO, Sébastien Dauvé, explained that the goal of the FAMES pilot line is to advance “not only FD-SOI at 10nm and 7nm nodes, but also novel non-volatile memory technologies, RF components, 3D integration, and the development of small inductors for DC-DC converters.” Sébastien Dauvé, CEO, CEA-LetiAdvancements in 3D integration and chiplet technologies are closely tied to innovation in chip packaging. Christoph Kutter, Executive Director of Fraunhofer EMS, described how the Advanced Packaging and Heterogeneous Integration for Electronic Components and Systems (APECS) pilot line in Germany is designed to meet the needs of industrial customers’ growing demand for advanced packaging solutions. Kutter noted “Customers told us that they needed to integrate logic and power, sensors and logic, and other combinations of functions. We have built the APECS pilot line to provide what they asked for.”Christoph Kutter, Executive Director, Fraunhofer EMSThe EU Chips Act is spurring investments not only in chip fabrication but also in the underlying technologies which support chipmaking. Emmanuel Sabonnadière, EVP at Soitec, highlighted how fabrication of advanced silicon carbide (SiC) power devices “is enabled by SmartSiC™ technology from Soitec – part of a built-in-Europe solution for silicon carbide.” Sabonnadière explained that SmartSiC technology “creates very thin layers of SiC material which make really differentiated substrates supporting the production of high-performance SiC devices.” Emmanuel Sabonnadière, EVP, SoitecInnovation in materials emerged as an important theme at ITF Chip into the Future. Julien Arcamone, Vice President of Corporate R D at ASM, described the critical role of materials for atomic layer deposition (ALD) in the advancing 3D semiconductor integration. Arcamone emphasized the importance of collaboration across the semiconductor value chain, describing ASM’s partnership with imec as part of “a win-win ecosystem.” Julien Arcamone, Vice President of Corporate R D, ASMDeveloping the skills to implement advanced semiconductor technologiesWhile the EU Chips Act is subsidizing the construction of new facilities including pilot lines needed for the hardware of the semiconductor industry’s expansion – the ITF speakers underlined the equally important “software” element of the semiconductor industry ecosystem: the knowledge and expertise of the people working in the industry. One of the biggest challenges in implementing the EU Chips Act is addressing Europe’s talent gap. Katrien Marent, Executive Vice President and Chief Marketing and Communications Officer at imec, said that the gap is in part “because students who graduate in STEM subjects are not trained in advanced semiconductor technologies.” From left to right: Katrien Marent, Executive Vice President and Chief Marketing and Communications Officer, imec; Julien Arcamone, Vice President of Corporate R D, ASM; Thomas Heurung, CEO, Siemens EDA; Frédérique Le Grevès, President STMicroelectronics France and Executive Vice President, Europe France Public Affairs, STMicroelectronics; Romano Hoofman, Director imec.IC-link, imec; and Christophe Frey, Vice-President of EU engagements Managing Director, ARM.Thomas Heurung, CEO of Siemens EDA, highlighted the need for educational reform in the electronics industry. He suggested that “we might not have the right degree-level curriculum for changing times in the electronics industry. We need to change the way that we train students at university, and we need more scope for early or mid-career training on specialist micro-curriculums aimed at a particular skill or knowledge set.”The industry also struggles to attract individuals. Frédérique Le Grevès, President of STMicroelectronics France and Executive Vice President, Europe France Public Affairs of STMicroelectronics, emphasizes the importance of rebranding the industry to attract new talent. She remarked, “The word ‘semiconductor’ itself isn't very exciting—it’s even off-putting to some. By simply changing the name of educational programs, we’ve seen significant increases in enrollment. This demonstrates the power of language in shaping perceptions and interest.”Thomas Heurung of Siemens EDA also called for a stronger emphasis on entrepreneurship, noting “there is a big contrast between Europe and the US, particularly Silicon Valley.” He explained how his company’s Cre8Ventures unit had been set up to help start-ups through the key stages of creating a successful new company, including product development, attracting funding, and bringing the product to market. Thomas Fleischmann, Program Manager at Robert Bosch, explained how the EU Chips Act has accelerated the formation of the European Semiconductor Manufacturing Company (ESMC) joint venture, in which Bosch is a key stakeholder. ESMC is building a new semiconductor fabrication plant in Dresden, dedicated to producing chips for the automotive and industrial sectors. Fleischmann emphasized that ESMC will play a crucial role in helping Europe “scale advanced technologies to high volumes at a competitive cost.”In addition, the EU Chips Act also provides a broader platform for the expansion of Europe’s deep tech capacity. This includes the creation of five pilot lines, which will offer European companies access to manufacturing capacity for prototyping at the most advanced semiconductor technology nodes.Thomas Fleischmann, Program Manager, Robert BoschITF Chip into the Future at SEMICON Europa 2024 highlighted the broad scope of the EU Chips Act – not only supporting the building of advanced fabs but also providing the foundations for technology development, production, and marketing – all aimed at supporting semiconductor innovation in Europe. SEMI ContactMaria Daniela Perez, Communications ManagerEmail: [email protected]

2019 will be a busy fall for the SOI Consortium and our members.First off are the SOI Consortium events in Shanghai and Tokyo, which are very popular indeed. We now have the dates locations locked in, so you’ll want to mark your calendars:Shanghai: 16 17 September 2019, FD-SOI Forum / RF-SOI Workshop. Both days will be held at the Pudong Shangri-La Hotel in Shanghai. The first day will focus on FD-SOI. The second day is all about 5G and RF-SOI. These are huge events – to get an idea of the magnitude, you can read our coverage of the 2018 event. Tokyo: 30 31 October 2019, Japan SOI Design Workshops. This year both days of workshops will take place in the Yokohama Landmark tower. The first day will be devoted to FD-SOI; the second day turns to More-Than-Moore – especially photonics and MEMS. Last year’s workshops were packed with excellent presentations and panel discussions, which we covered here. The SOI Consortium and members will also be giving talks at Semicon Europa, which is being held 13 – 15 November 2019 in Munich, Germany. The programs are currently being finalized. As soon as they’re ready, we’ll be sure to let you know so you can register and/or share the news with your colleagues and clients. But in the meantime, make sure you save the dates.Would you like to check out the presentations given at Consortium events in previous years? If you hover your cursor over the Events tab at the top of our home page, you’ll get a drop-down menu of events for the last five years (we’re working on adding more – we’ve been doing these events for over a decade!). Click through to any past event and you’ll land on a page where you can download most of the presentations that were given there. Of if you’re looking for past presentations given by any particular company, use the search engine at the bottom of any page on our website. S3SYou’ll also find many of our members at the IEEE/EDS S3S Conference in San Jose, CA, October 14 – 19th. S3S (formerly known as The SOI Conference) has been running in various forms for over 30 years. They always have an excellent line-up of speakers, plus it’s a great opportunity for networking with researchers from across the worldwide SOI ecosystem. BTW, while the deadline for general paper selection has already closed, papers of exceptional merit are currently being accepted for their Late News Sessions. See the 2019 Call for Papers for more information – those Late News papers need to be received by 23 August 2019 for consideration. Also, IEEE S3S Conference will once again host a full-day short course and a half day tutorial. These are very popular. The short course this year will be on SOI Design and Technology for Analog and Mixed Signal. As of this writing, the program is still being finalized, but more will be announced in the next few weeks, so check back on their website soon for updated information.Member EventsAnd finally, don’t forget to learn more about the offerings from and in support of the SOI ecosystem at our members’ events around the globe, including: GlobalFoundries – GTC | Samsung Foundry – SFF | ST – Technology Tour | Synopsys – SNUG | Cadence – CDNLive | Silvaco – SURGE | Arm – TechCon | NXP – Tech Days | Leti – Events | imec -Events |

SEMI met with Gerald Beyer, program manager at imec, to discuss the co-existence of various 3D interconnect technologies and their need for new materials and integration solutions. The two talked in the runup to his presentation at the Advanced Packaging Conference at SEMICON Europa 2018, 13-16, November 2018, in Munich, Germany. To register for the event, click here. SEMI: Can you confirm this trend towards heterogeneous integration and do you think it will be a long-term development trend?Beyer: We consider heterogeneous integration as a scaling booster for functional partitioning and as a fashion method to create systems, which would not be possible or economical on such as a single chip. As you can apply it to numerous systems, we expect it to stay for the long term.SEMI: What are the new critical challenges for the combination of different technologies into one package?Beyer: When you create a complex system, there is usually more than just one challenge. On one side, you need to be able to design such a system. If you disintegrate a large chip, you need to decide how to reconstruct it, i.e. which function goes into which strata. You would like to do that not manually but with a set of tools supporting the designer. Only recently EDA (Electronic Design Automation) and design houses have started to support this idea.On the technology side, interconnections between some strata of such a reconstructed chip will require small pitch interconnects of the order of 1µm pitch and less. Today, wafer-to-wafer bonding technologies have sufficient overlay margins for 1µm pitch. Wafer-to-wafer bonding technologies, however, have a number of constraints such as equal die size and the necessity to realize chip stacking rather in a fab environment than in a traditional packaging house. Die-to-wafer assembly technologies still need to bridge the gap to deep sub 10µm pitch in terms of alignment and cleanliness.SEMI: What kind of new materials or integration solutions do you expect to be developed? Are you working on it already?Beyer: As explained above, die partitioning requires sub 1µm pitch interconnects. We are investigating fine pitch wafer-to-wafer and die-to-wafer (direct) bonding. For the latter, not only new alignment capabilities but also die cleaning and thin die handling technologies need to be developed. To build a complete system with data processing, memories etc., novel integration schemes such as Flip Chip – Fan Out Wafer Level Packaging with high density 2D and 3D interconnect capabilities are being investigated. These new systems differentiate from current ones by high density Through Package Vias (TPV), Si bridges and sub 2µm line/spacing RDL. The new integration approaches push the materials such Temporary Bond Materials (TBM), Wafer Level UnderFill’s (WLUF), photo patternable polymers for fine Line/Spacings to name a few, to the limits. Hence, development of new materials is a key aspect.SEMI: What trends and developments do you expect in the near future and why would you recommend attending the Advanced Packaging Conference?Beyer: The development and commercialization of products using heterogeneous integration is a big effort drawing on resources from EDA vendors, materials and packaging tool suppliers, OSATs, foundries, memory suppliers and IEDMs and academia alike. The agenda of the Advanced Packaging Conference at SEMICON Europa reflects this diversity and I am looking forward to interesting discussions with all participants. Gerald Beyer has been working in the field of 3D Technologies since 2012 as the technology program manager of the 3D System Integration Program of imec. Prior to this role, he was the interconnect program manager and group leader of BEOL integration. He received a PhD in materials science from Imperial College, London and a MSc from Thames Polytechnic, London.Serena Brischetto is a marketing and communications manager at SEMI Europe.

RF-SOI is in every smart phone out there, and with 5G, there are lots more applications on the horizon. If you’d like to learn more about designing in RF-SOI, there’s a great short course coming up the day before and in conjunction with the EuroSOI-ULIS Conference in Granada, Spain.The title of this short course is RFSOI: from basics to practical use of wireless technology. Program and registration details can be found here. The course runs for the full day on Sunday, 18 March 2018.The talks, which are being given by a stellar line-up of experts, include: RF SOI, fabrication, materials and eco-system - Ionut Radu Director of Advanced R D, Soitec Fundamentals of RF SOI technology - Jean-Pierre Raskin, Professor, UCL 22nm FDSOI Technology optimized for RF/mmWave Applications - David L. Harame, RF CTO Development and Enablement, GlobalFoundries RF SOI technology and components for 5G connectivity - Christine Raynaud, Program Manager (Business Development – Technology to Design), CEA-Leti Analog and RF design on SOI - Barend van Liempd, Senior Researcher, imec Techniques and tricks for RF measurements on SOI - Andrej Rumiantsev, Director RF Technologies, MPI Corporation FOSS TCAD/EDA tools for advanced SOI-device modeling - Wladek Grabinski, R D CM Manager, MOS-AK RF design flow for SOI - Ian Dennison, Design Systems Senior Group Director, Cadence The course is being organized by SOI Consortium members Incize and Soitec. BTW, this year marks the 4th joint EUROSOI – ULIS Conference. The EuroSOI Conference, which has been ongoing for decades, is well paired with the ULtimate Integration on Silicon Conference. The joint conference provides an interactive forum for scientists and engineers working in the field of SOI technology and advanced nanoscale devices. One of the key objectives is to promote collaboration and partnership between different players from academia, research and industry. As such, it covers technical topics, industry trends and updates from pertinent European programs. EuroSOI-ULIS will take place 19–21 March 2018 at the University of Granada in Spain. For information on the program and how to register, see the website. Following the conference, the papers will be available at the IEEE Xplore® digital library, and the best papers will be published in a special issue of Solid-State Electronics.