semiconductor design

A change is underway in the manufacturing sector as the use of curvilinear shapes on photomasks grows, leading to the real possibility of curvilinear shapes in designs. It may just be the start of a revolution away from Manhattan or rectangular shapes to curvilinear shapes. Changing the physical design infrastructure to be curvilinear seems too daunting a task. Are curvilinear shapes in designs a real possibility? I turned to Aki Fujimura, CEO of D2S, a member of the ESD Alliance, a SEMI Technology Community, to further explain the shape of the future. Smith: What is the difference between Manhattan and curvilinear shapes? Fujimura: Manufactured masks and wafers are all curvilinear, even if the input CAD geometries are rectilinear (shown in Figure 1). It’s always been true that nature can’t make 90-degree turns, so sharp corners were always a matter of how closely you looked. These days, at the leading-edge nodes and their required resolutions, wafers and even masks are all visibly curvilinear as you can see in the graphic on the left in Figure 2. Since the 1980s, both chip design and chip manufacturing systems have used axis-aligned rectangles, or “Manhattan” geometries, because 1) that was sufficient to design transistors and interconnect for the most part, and 2) CPU-based computer algorithms can be made much more efficient for Manhattan geometries. Curvilinear shapes can be piecewise linear polygons of some resolution, or spline-like formats that are curvilinear at any resolution, or specific curved patterns like circles and ovals. Figure 1: All shapes on masks and wafers are curvilinear, even if the input geometries are Manhattan. Source: D2S Smith: What are the benefits of curvilinear masks? Fujimura: The manufacturing side of the semiconductor community knows that the best possible process window for wafer lithography is obtained by using curvilinear correction of mask shapes instead of Manhattan shapes. There have been numerous studies on the topic over several decades. The technique to generate purely curvilinear mask shapes is known as inverse lithography technology or ILT and is an advanced form of optical proximity correction (OPC). At a February 2020 eBeam Initiative event, Micron Technology presented a study showing process window improvement up to 85% for advanced memory designs as a result of using curvilinear ILT (shown in Figure 2). Additionally, Ryan Pearman from D2S presented a study at Photomask Japan 2019 showing that it is preferable to move toward a completely curvilinear paradigm, not only because ILT is better, but because the mask manufactured will have reduced variability. Figure 2: Micron Technology explained the benefits of curvilinear mask shapes for advanced memory at the eBeam Initiative event during 2020 SPIE Advanced Lithography Conference. Source: Micron Technology Smith: If the benefits have been known for decades, why is it happening only now? Fujimura: Several things happened at the same time. Multi-beam mask writing is now available. GPU acceleration for general computing has become mainstream. And wafer process window (resilience to manufacturing variation) is increasingly a problem for the leading-edge nodes as we are in the 5nm node, going to 3nm. Curvilinear ILT is needed much more now than before, will soon be needed for EUV lithography too, and is now possible because of multi-beam mask writing and GPU acceleration. Smith: Curvilinear mask shapes enable curvilinear design shapes too? Fujimura: Adoption of curvilinear mask shapes is the first step in targeting curvilinear shapes on wafers. Without curvilinear masks, it is difficult to target and reliably manufacture curvilinear designs. Curvilinear ILT works in the pixel-space to output the desired mask shape to maximize the process window for wafer lithography. A side effect of curvilinear ILT is that it can also take curvilinear targets as input. ILT, most likely GPU-accelerated ILT, works with rasterized input data, so the ILT algorithm itself is not affected even in runtime by having any amount of curvilinear design data. The resulting mask shapes are written in multi-beam mask writers, which write pixels with doses. They too will write curvilinear masks at the same speed as Manhattan masks. Suddenly now, curvilinear designs can be handled by chip manufacturing equally well for the first time in about 30 years. Smith: But curvilinear designs would be hard, right? There are a lot of tools that depend on the Manhattan assumption. Fujimura: Yes, you’re right. We’re not going to suddenly see chips that have curvilinear routing all over the place, or curvilinear intra-connect in standard cells or memory cells. The entire physical design infrastructure that includes place and route, timing, custom layout, parasitic extraction and design rule checking moving to curvilinear design all at once is extremely unlikely. Could portions of these problems be tackled for specific cases over time as “hot spot” solutions? With GPU-accelerated SPICE being available now, as an example, if GPU acceleration is adopted for design, the same transformation that happened in manufacturing can (gradually) happen in design too. The key question is whether it’s worth the trouble. Smith: Is it worth the trouble? Fujimura: I don’t know if it’s worth the trouble for the entire infrastructure. For hot spots, “hot” for various reasons, there are certainly benefits. Jogging a 32-bit bus by one grid is certainly much more economical space-wise with curvilinear shapes. Inside standard cells or memory cells, there are certain types of features that pack better with curvilinear designs. In general, interconnect is the limiter to chip size of course, but there are always critical areas that could use help to shrink. There are manufacturability benefits as well. In general, when something changes so drastically as this for the first time in 30 years, there’s bound to be some innovation that takes advantage of the discontinuity. Let’s see what the combined capitalistic power of the entire community might be able to come up with. The first thing is to let everyone know that curvilinear designs will be manufacturable today. Hear insights from other leading electronic system design industry CEOs at the SEMI ESD Alliance CEO Outlook on May 18, 2021, 2:00pm-3:00pm PDT. Panelists will discuss the state of the industry along with their views of the outlook for the coming years. Registration is free for SEMI members. About Bob Smith Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community. He is responsible for the management and operations of the ESD Alliance, an international association of companies providing goods and services throughout the semiconductor design ecosystem.

Electric mobility, renewable energy and other technology innovations like IoT, 5G, smart manufacturing and robotics all require reliability, efficiency, and compact power systems, fueling the adoption of Silicon Carbide (SiC) and Gallium Nitride (GaN) to support lower voltages in significantly smaller devices. But chip designers must overcome the technological and economical challenges of integrating the two semiconductor materials into power systems.SEMI spoke with Elisabeth Brandl, Business Development Manager at EV Group about trends and new developments within the power electronics industry and the devices' application in smart mobility. Brandl shared her views ahead of her presentation at the SEMI SMART Mobility Forum, 18 February, as part of the SEMI Technology Unites Global Summit, 15-19 February 2021, online event. Join us to meet experts from EV Group and other key industry influencers. Registration is open. SEMI: What is driving new developments in power electronics?Brandl: Globally there are significant changes in infrastructure requirements for communication, automotive and power conversion. We need to look no further than the rising adoption of 5G, electric and hybrid vehicles, and renewable energy as examples of drivers of these changes. The device level, particularly in the field of power electronics, figures prominently in these shifts.The power electronics industry faces a growing number of scenarios where conventional silicon power devices are no longer suitable and are easily outperformed by new architectures mainly based on wide bandgap semiconductor materials like Silicon Carbide (SiC) and Gallium Nitride (GaN).SEMI: What industry challenges is power electronics innovation aiming to solve? Brandl: Power conversion efficiency is very important and needs further improvement as the related losses significantly contribute to the overall power consumption. For green power and a better environmental footprint, renewable energy is crucial, but so is overall power-consumption efficiency, yet the role of power devices is often underestimated. High-frequency and high-power applications, such as data center applications and inverters for renewable energy, where silicon power electronics are reaching their limits, are also important areas in power electronics.SEMI: How will the transition from silicon to compound semiconductor materials help?Brandl: The superior material properties of several compound semiconductors can tackle the need for lower losses in power conversion or better high-frequency behavior. Today, we mainly talk about GaN and SiC power devices as they are materials well-suited to address these needs. However, other materials like diamond and gallium oxide are in development for these applications. Material properties of SiC that enable thinner materials with lower power losses and better thermal behavior address power conversion efficiency as well as form factor challenges. GaN, especially in a high electron mobility transistor (HEMT), can be used for high-frequency applications.SEMI: What enables a better and more cost-effective manufacturability of SiC and GaN power devices?Brandl: For the end customer, a typical figure of merit regarding the cost effectiveness is $ per Ampere or Watt. While this seems simple, the reality is of course more complex. It is important to understand the main cost contributors within the manufacturing area. For SiC, this is clearly the substrate cost. In my presentation, I will show a way to reduce this cost via wafer bonding. For GaN, epitaxy – a method for growing or depositing mono crystalline films on a substrate – is the critical parameter. And of course, yield has a very big impact on cost effectiveness too, which means that good process control including metrology is very important.SEMI: Many semiconductor companies are already transitioning to silicon carbide and gallium nitride. Can you give us an example of a success story?Brandl: All the big power device manufacturers have either acquired or developed their SiC and/or GaN power device technology, so they also see a bright future for these wide bandgap semiconductors in the power device market. The most prominent success story is STMicroelectronics with its SiC MOSFET power devices, which have been implemented by Tesla in its Model 3 vehicles since 2018.SEMI: What is coming next?Brandl: New materials for power devices are being explored, such as diamond and gallium oxide. For SiC, the trend is moving toward 8-inch substrates, which is the focus of the funded EU project REACTION under the coordination of STMicroelectronics. Cost reduction and substrate availability also play a big role. All major power device manufacturers have contracts to secure the supply chain for SiC substrates because material availability is the main uncertainty at this time. Finally, collaborations along the supply chain are crucial and generally beneficial for all parties, as development requirements are better communicated and prioritized.Elisabeth Brandl is Business Development Manager at EV Group. She received her master in technical physics from the Johannes Kepler University Linz, Austria in Semiconductor and Solid State Physics. Since 2014, she has been responsible for Product Marketing Management for temporary bonding and compound semiconductors at EVG. The SMART Mobility Forum is the digital platform of SEMI Europe’s Global Automotive Advisory Council (GAAC) for industry stakeholders along the automotive and electronics value chains, from Design, Semiconductor Equipment and Materials Suppliers to Automotive OEMs.Smart Mobility is one of four SEMI initiatives focused on building communities, content, and activities around critical and emerging electronics markets. Read more about our Regional Chapters.Serena Brischetto is senior manager of Marketing and Communications at SEMI Europe.

Even though microchips continue to get smarter, vital security gaps continue to be exposed through such hack attacks as Meltdown, Spectre, and in recent weeks, Plundervolt. Researchers continue to discover open doors in chip architectures for malicious players to steal increasingly sensitive data, hide the identity of counterfeits, or tamper with electronics systems most anywhere along the global microelectronics supply chain. Today, it’s impossible to have full visibility of the distributed chip making process – from design and fabrication to packaging, testing and delivery. That’s why our industry’s future hinges to a large degree on establishing a hardware root of trust throughout the silicon’s operational lifecycle. Trust but verify! It’s easy to say, but how do we do it?To gain insights, SEMI interviewed Dr. Mark Tehranipoor, currently the Intel Charles E. Young Preeminence Endowed Chair Professor in Cybersecurity at the University of Florida’s Electrical and Computer Engineering Department. A foremost authority on microelectronics security and trust, counterfeit electronics detection, and supply chain risk management, Dr. Tehranipoor will be a keynote speaker at the SEMICON Taiwan Security on Chip Summit, Friday, September 25, where a full program of industry leaders will address key security challenges and solutions involving IoT, systems on a chip (SoCs), integrated circuits, physical unclonable function (PUF) technology, future design, certifications, managed services, and more.For additional insights and to hear Dr. Tehranipoor’s full presentation, register for SEMICON Taiwan 2020, which SEMI is holding as a hybrid event with both a virtual format and an in-show program September 23-25.SEMI: What are the major uncertainties in providing the hardware root of trust within the cyber domain?Tehranipoor: One of the most critical issues we’re dealing with now is loss of control over the process of designing and fabricating integrated circuits and systems. This has happened along with globalization and the movement of supply chain operations overseas to lower costs of nearly all goods, including electronics products and semiconductors. As skill sets, talent, design and fabrication have all shifted offshore, concerns have also risen about security controls across the many different segments of the microelectronics supply chain.For example, when you think about the security of military, space, transportation, power grids, financial or other networks, it becomes a major concern if you cannot trust the underlying electronics system that runs them. New SoCs are also holding more sensitive data around encryption keys, biometrics, personal information or banking data. And as reports escalate about cybersecurity gaps at the electronics part level, it’s increasingly important to establish a hardware root of trust. Today, it’s not enough for a buyer to just call up the design house and verify the electronic ID of an asset. The ID might match, but the device could have been tampered with or replaced with a counterfeit somewhere along its end-to-end journey. Unlike software or networks where problems can be automatically identified, upgraded and fixed, verifying electronic hardware is a costly and time-consuming process, especially when they’re as complex as microchips. It can take months to deconstruct, reverse engineer, inspect, and authenticate a chip. By then, discovery of any security breaches is too late.When addressing the security of electronics systems, there are three important features to keep in mind. First, there’s confidentiality. The device shouldn’t leak information to an unauthorized user. Second, there’s integrity. Unauthorized users should not be able to manipulate an SoC’s sensitive data. The third feature is availability, which can be a result of Denial of Service (DoS) attacks. If the device is under attack and can’t access your online service or network, you must still have security measures for your electronics system to be available in a safe mode while you simultaneously identify the problem, recover from it, and return to normal functions.SEMI: What framework should be followed to establish greater trust and confidence across the entire microelectronics supply chain?Tehranipoor: In the United States, we recognize it may not be possible to bring all manufacturing, design, and delivery teams back to this country and have them certified by the U.S. Department of Defense. You could do some of it, but it would be very costly and complex to bring back all the design, fab, testing, and packaging operations involved with electronics systems and still have complete control.The most practical approach is to make sure we design electronic systems with security and trust in mind from the start. We need to provide security features up front throughout the extended supply chain – into the design flow, fab flow, and out into the field to make it easier and faster for anyone at any point to verify the authenticity of an electronic system as well as identify and mitigate a problem. Finally, we have to remember that we are all in this together – designers, developers, packaging facilities and fabs. We can’t just blame semiconductor manufacturers or any other single entity. As a result, we must be cooperative and collaborative by focusing on this issue as a consortium. Everyone in this ecosystem must come to the table, share best practices, establish standards, and initiate best practices for device to system authentication.SEMI: How can SEMI and the SEMI Electronic System Design (ESD) Alliance help the industry meet these challenges?Tehranipoor: It’s certainly of utmost importance for members of organizations like SEMI and its ESD Alliance committees to jointly develop and adhere to standards or guidelines that establish hardware root of trust across all participants in the global supply chain. At the same time, such alliances should make it a high priority to protect each company’s intellectual property (IP). Collectively, we need resolutions that allow us to develop unique IPs and more easily trace, identify, and verify the authenticity of electronics systems as they flow throughout the end-to-end electronic supply chain. Great efforts are under way and progress is being made. But it’s not enough. Clearly, more needs to be done to establish root of trust standards at the chip level.I can’t emphasize enough the importance of consortia like the SEMI ESD Alliance to create an environment where industry, government, and academia can come together, share best practices and even case studies on how they handled security vulnerabilities and breaches. We understand that not everyone wants to share their security problems, vulnerabilities, or attack surfaces, but learning from each other’s experiences can have a tremendous impact on industrywide progress. If you don’t know what you need to address, you won’t be able to address it when it happens.I also encourage organizations like SEMI to create standards or guidelines that reduce the complexity of microchip designs for security purposes. Realtors often say there are three things to consider in finding a home that will appreciate in value: Location, location, location. To build more secure electronics systems, my mantra is: Automation, automation, automation. Complexity is the enemy of security. By using automation to simplify security mechanisms and detect inconsistencies, it will be easier to find and fix security problems, not to mention lower costs at the same time. SEMI: What will an attendee take away from your talk at SEMICON Taiwan?Tehranipoor: I have a large team of researchers who day and night spot vulnerabilities by attacking and assessing data from different electronic systems set up in our labs. Attendees will see real-world examples and lab animations that show how electronics systems can be hacked most anywhere across the supply chain. They will also learn about step-by-step security solutions we have developed at the microchip level. We need to do a better job of protecting the security of our semiconductor assets and the electronic solutions or services they power. My call to action will be that we need to invest more in research and foster an environment of more open trust and cooperation. We can do this by bringing together different countries, companies, and organizations in the microelectronics ecosystem to overcome this major challenge.Dr. Mark Tehranipoor is currently the Intel Charles E. Young Preeminence Endowed Chair Professor in Cybersecurity at the ECE Department, University of Florida. He is currently serving as Director for Florida Institute for Cybersecurity Research (FICS), National Microelectronics Security Training Center (MEST), CYAN Center of Excellence, and ECI Transition Center. He also serves as Program Director of Cybersecurity for UF Herbert Wertheim College of Engineering. His current research interests include IoT security, hardware security and trust, and reliable circuit design.Samer Bahou is senior manager of corporate communications at SEMI.

The microelectronics industry is entering the era of Cloud Engineering Simulation to slash the costs and risks of new technology development and speed time-to-market in spaces like semiconductors, MEMS sensors, RF front ends, biomedical and driverless cars. In the run-up to SEMICON Europa, 12-15 November, 2019, in Munich, Germany, SEMI spoke with Ian Campbell, CEO of OnScale, about the new paradigm of Cloud Engineering Simulation. Campbell shared his views ahead of the SMART Design Forum, 14 November, 2019, 14:30 to 17:00, in Hall B1, TechARENA 1 at SEMICON Europa. Registration is open. Join the forum to meet experts from OnScale and other key industry influencers. Attendance is free of charge for all SEMICON Europa visitors.SEMI: How did your adventure with OnScale start?Campbell: I’m an engineer. When I was still in high school, I took a night class at Nashville Tech to learn AutoCAD R14, and I’ve been designing and engineering things ever since. I was introduced to Desktop Simulation in my bachelors of mechanical engineering program and used many types of simulation tools for massive design studies at the Aerospace Systems Design Lab at Georgia Tech. I’m a simulation junkie.I started my first Silicon Valley high-tech company, NextInput, in 2012 with Dr. Ryan Diestelhorst (now VP of Strategy at OnScale), to commercialize new ForceTouch and 3D Touch technologies based on our patented MEMS force sensors. At NextInput, we bought hundreds of thousands of dollars of engineering software, but were always frustrated by slow, inaccurate engineering simulation results. We dreamed about running massive simulations on Cloud Supercomputers and creating true Digital Prototypes that could replace costly, time-consuming, and risky physical prototypes.When I got the chance to join the team that became OnScale in 2017, I jumped at the opportunity. At OnScale, we took engineering simulation solvers that had been developed for the U.S. military to run on U.S. Department of Defense and DARPA supercomputers and built a cloud supercomputer platform on Amazon Web Services to run the solvers. The net-net is the world’s first on-demand, infinitely scalable Cloud Engineering Simulation platform. Now, we routinely run massive multi-billion degree of freedom simulations for Fortune 100 companies, including many from the semiconductor and MEMS industries. Since our business model is to charge per core-hour for simulations, the incredible capability we built is cost-effective and available to small startups as well. SEMI: How is the semiconductor design ecosystem evolving? How is Cloud Engineering Simulation applied to semiconductor and design industries?Campbell: The entire industry is experiencing a massive acceleration in product launch cycles and increased competition. New markets like IoT and 5G are reducing semi/MEMS product cycles from years to months. That, in turn, puts enormous pressure on semiconductor and MEMS designers. Missing a key product introduction like a flagship smartphone launch can literally make or break a company.A reliance on traditional engineering methods – schematic capture and layout of a chip, taping out (physically prototyping the chip), performing engineering validation on an e-bench, qualifying the chip (or not qualifying it and going back to the drawing board), and finally launching mass production – is no longer sustainable from a competitive perspective.Instead, market-leading firms are turning to Cloud Engineering Simulation and Digital Prototypes to explore massive design spaces, find optimum designs that beat the competition in every KPI (size, power, performance), and digitally qualify designs before ever cutting silicon, ensuring that designs are robust over their intended operating environments and performance envelopes. Large thermal analysis of a chip on a circuit board executed quickly on the OnScale Cloud Simulation Platform SEMI: Can you give us an example? Campbell: A great example is thermal analysis. Thermal effects have always had huge impacts on MEMS device performance and, more recently, they are beginning to impact performance of next-gen semiconductors, especially GaN power electronics for electric vehicles (EVs).Conducting a full system-level thermal analysis of something like an EV power management system – a power IC in a package, on a board, in an enclosure, under various loading conditions – has been a challenge from a simulation complexity perspective (degrees of freedom) and from a parametric sweep perspective (running hundreds or thousands of simulations to optimize chip placement, routing, etc.). To run these sets of simulations using legacy desktop simulation would take weeks, perhaps even a month or more. To run these massive simulations in parallel on cloud supercomputers using OnScale takes days or even hours.Our customers routinely run very large simulation studies on OnScale Cloud for thermal simulations, RF filter simulations, MEMS simulations, packaging simulations (what we call Digital Qualification), and many more use cases.SEMI: What’s one of your strategic objectives for 2020? Campbell: For 2020, we’re doubling down on MEMS and semi simulation capabilities. We will be launching additional solver capabilities like EM that will be critical in our strategic markets like 5G. We will also be launching a Cloud API so that engineers can integrate OnScale directly into their existing engineering workflows (e.g. MATLAB or EDA/CAD tools) with just a few Python commands.SEMI: Can you share one prediction for the future of semiconductor design solutions? share?Campbell: I think we will continue to see MEMS and semi designers push the envelope and bring smaller, more performant, more cost-effective solutions to market. I’d like to see more highly cost-effective flexible semi/MEMS designs come to market to enable next-gen IoT and IIoT applications. I’d also like to see more biomedical applications – biomems, microfluidics, and labs on a chip for all sorts of life-enhancing applications.SEMI: What are your expectations regarding the SMART Design Forum at SEMICON Europa 2019 in Munich? Campbell: I’m looking forward to getting back to my roots in MEMS/semi design and chatting with other designers about the future of engineering and the future of semi! Ian Campbell is a twice venture-backed Silicon Valley CEO and expert in MEMS sensors, semiconductor technology, and engineering software. Most recently, Ian co-founded OnScale, a Cloud Engineering Simulation startup backed by Intel Capital and Google’s Gradient Ventures. OnScale is revolutionizing engineering by combining world-class multiphysics solvers with Cloud supercomputers, machine learning, and artificial intelligence. Prior to co-founding OnScale, Campbell served as founder and CEO of NextInput, where he led the startup through multiple rounds of funding – totaling $12 million and an additional $4 million in research contracts with government and industry partners – and built a world-class team of engineers and scientists who developed 3D Touch and ForceTouch technologies for smartphones, wearables, industrial, and automotive interface applications. He also secured the first major smartphone OEM design wins in Asia. Campbell earned his B.S. in mechanical engineering from Middle Tennessee State University, and his MSAE in aerospace engineering and MBA from Georgia Institute of Technology.Serena Brischetto is senior manager, marketing and communications, at SEMI Europe.

New SEMI Taiwan Testing Committee to strengthen the last line of defense to ensure the reliability of advanced semiconductor applications.Mobile, high-performance computing (HPC), automotive, and IoT – the four future growth drivers of semiconductor industry, plus the additional boost from artificial intelligence (AI) and 5G – will spur exponential demand for multi-function and high-performance chips. Today, a 3D IC semiconductor structure is beginning to integrate multiple chips to extend functionality and performance, making heterogeneous integration an irreversible trend. As the number of chips integrated in a single package increases, the structural complexity also rises. Not only will this make identifying chip defects harder, but the compatibility and interconnection between components will also introduce uncertainties that can undermine the reliability of the final ICs. Add to these challenges the need for tight cost control and a faster time to market, and it’s clear that semiconductor testing requires disruptive, innovative change. Traditional final-product testing focusing on finished components is now giving way to wafer- and system-level testing.In addition, the traditional notion of design for testing, an approach that enhances testing controllability and observability, is now coupled with the imperative to test for design, which emphasizes drawing analytics insights from collected test data to help reduce design errors and shorten development cycles. Going forward, the relationship among design, manufacturing, packaging, and testing will no longer be un-directional. Instead, it will be a cycle of continuous improvement.This paradigm shift in semiconductor testing, however, will also create a need for new industry standards and regulations, elevate visibility and security levels for shared data, require the optimization of testing time and costs, and lead to a shortage of testing professionals. Solving all these issues will require a joint effort by the industry and academia. "With leading technologies and $4.7 billion in market value, Taiwan still holds the top spot in global semiconductor testing market," said Terry Tsao, President of SEMI Taiwan. "When testing extends beyond the manufacturing process, it can play a critical role in ensuring quality throughout the entire life cycle from design and manufacturing to system integration while maintaining effective controls on development costs and schedules. Taiwan's semiconductor industry is in dire need of a common testing platform to enable the cross-disciplinary collaboration necessary for technical breakthroughs."The SEMI Taiwan Testing Committee was formed to meet that need, gathering testing experts and academics from MediaTek, Intel, NXP Semiconductors, TSMC, UMC, ASE Technology, SPIL, KYEC, Teradyne, Advantest, FormFactor, MJC, Synopsys, Cadence, Mentor, and National Tsing Hua University to collaborate in building a complete testing ecosystem. The committee addresses common technical challenges faced by the industry and cultivates next-generation testing professionals to enable Taiwan to maintain its global leadership in semiconductor testing.The SEMI Taiwan Testing Platform spans communities, expositions, programs, events, networking, business matching, advocacy, and market and technology insights. For more information about the SEMI Taiwan Testing platform, please contact Elaine Lee ([email protected]) or Ana Li ([email protected]). Emmy Yi is a marketing specialist at SEMI Taiwan.