SiC

Silicon carbide (SiC), with its wide band gap and high thermal conductivity, is increasingly favored for semiconductor power applications across several fast-growing industries. Its ability to operate at higher voltages and frequencies enables significant efficiency gains, particularly in e-mobility, where SiC offers key advantages in size, weight, and speed compared to traditional silicon-based power devices.However, as promising as SiC is, the industry still faces critical challenges in scaling to meet growing demand. Key barriers include cost, reliability, and manufacturing capacity, all of which must be addressed for SiC to fully mature.SEMI spoke with Entegris Senior Director - Advanced Technology Engagements, Office of the CTO Mark Puttock, Ph.D., to discuss the challenges of scaling SiC power chip manufacturing from a material supplier’s perspective. Puttock shared insights ahead of his presentation at the Entegris session, Cultivating a Thriving SiC Market: Tackling Key Challenges Across the Value Chain, taking place on November 14, 2024, at SEMICON Europa in Munich, Germany. Don’t miss the opportunity to engage with experts from Entegris and other industry leaders. Registration is now open. SEMI: Global megatrends like environmental crises and AI drive the necessity for SiC power semiconductors. What is the current status? Puttock: The increasing demand for efficient power electronics — fueled by global megatrends such as vehicle electrification, environmental de-carbonization, and the rise of power-hungry AI chips — drives the necessity of wide bandgap semiconductors. SiC offers advantages of weight, size, and speed over traditional silicon (Si) solutions, which are particularly vital in automotive applications 600V and above. However, SiC chip manufacturing has not reached the maturity of silicon-based processing. Greater maturity will help reduce costs, which will accelerate adoption in the market.SEMI: What are the main challenges in scaling SiC?Puttock: Challenges in scaling SiC power chip manufacturing to high volumes are not surprising. That’s because high volume producers have not been operating long enough to resolve early-stage issues. From a material perspective, SiC is more challenging to manage compared to Si. The challenges we identify include:Chemical Mechanical Planarization (CMP): SiC is nearly as hard as diamond and significantly harder than Si, making it challenging to achieve a high removal rate while maintaining both planarity and low defectivity. This step is crucial toward the end of the wafering process and before the epitaxial growth of device layers.Handling: SiC is more brittle than Si, making it more susceptible to damage or breakage.Implantation: SiC is more difficult to implant than Si, requiring higher temperatures and the use of aluminum instead of boron as a P-type implant species. Additionally, it is a significant challenge to achieve a reliable aluminum source with a long and stable lifetime.Thermal Processing for Wafer Growth and Epitaxy Processes: SiC processes run hotter than Si ( 2000° C for wafering, 1500° C for epitaxial growth), demanding resilient chamber parts to achieve good lifetimes.Sustainability: Because SiC is extremely hard, the CMP process requires significant amounts of slurry. Improving slurry recycling and wastewater management continues to be a challenge.On October 29, we will address these issues in our webinar, “Challenges in Scaling SiC Power Chip Manufacturing: A Material Supplier's Perspective” This session will provide valuable insights and considerations for advancing maturity in high-volume SiC power chip manufacturing. SEMI: Can you elaborate on the challenges associated with CMP for SiC wafers? Puttock: SiC wafers are challenging to process, requiring specialized materials and methods compared to traditional silicon. Defects in the SiC wafer crystal during non-optimized CMP processing can propagate into the device epitaxial layers. This leads to yield loss, increased electrical resistance, reduced performance, and wasted power.SiC wafers must be cut, ground, lapped, and polished to create the necessary surface properties before depositing active layers. As the demand for these devices grows, optimizing the CMP process is essential to ensure the desired surface quality and planarity required for device fabrication. For a deeper understanding of these challenges, we recommend downloading our latest white paper, “Solving CMP Challenges in High-Volume SiC Production,” which covers:Achieving maximum smoothness with high removal ratesReducing the total cost of ownership Optimizing CMP slurry and pads for the unique wafer chemistry and topology of SiC wafersSEMI: What do you mean by optimizing slurry for SiC CMP?Puttock: CMP slurry typically consists of abrasive nanoparticle powder dispersed in a chemically reactive solution. The objective is to achieve a smooth, defect-free surface (less than 1 A Ra) with a high removal rate (greater than 7 µm/m).Traditionally, achieving high removal rates and smooth surfaces required two separate slurries. This approach sometimes forced SiC wafer manufacturers to choose a defect-free surface over a faster, more efficient CMP process, depending on their fab capabilities. Today, optimization allows SiC wafer manufacturers to achieve both high polishing capacity and good final surface quality using a single slurry.Additionally, while the slurry is the most critical part of the CMP process, the pad must be compatible with the application. This ensures the desired planarity while also preventing scratches or contamination of the SiC wafer surface. Research shows that optimized thermoplastic polyurethane CMP pads outperform traditional thermoset polyurethane pads. The optimized pads minimize surface damage and enhance removal rates due to their bulk hardness.SEMI: What are the future challenges for SiC devices? Puttock: SiC devices are increasingly favored for their superior energy efficiency and reduced environmental impact. However, the SiC manufacturing process presents challenges due to its high-temperature operations, which consumes significant amounts of energy and shortens the lifespan of chamber components. To address this, improving efficiency in these processes will be crucial in the coming years.Recycling is another important challenge. For example, CMP slurries present an opportunity for water recycling and conservation. At Entegris, we are committed to this issue and are actively collaborating with key industry players to enhance material circularity and prioritize sustainability in our new product development.SEMI: How is Entegris contributing to advancements in SiC technology, and what initiatives or partnerships do you have planned for the near future? Puttock: Entegris is an active member of the SEMI Global Automotive Advisory Council (GAAC) and participates in a working group focused on SiC with key industry leaders such as Volkswagen, BMW, Porsche Consulting, onsemi, Infineon, STMicroelectronics, and others. Our engagement spans the entire semiconductor supply chain, collaborating with integrated device manufacturers and original equipment manufacturers in fabs worldwide. Additionally, we recently announced our latest long-term agreement with onsemi, which underscores our commitment to advancing SiC technology.SEMI: What are your expectations regarding your participation at SEMICON Europa? Puttock: SEMICON Europa is a unique platform to connect with the semiconductor and automotive ecosystems. Last year, we organized a highly successful SiC session in collaboration with SEMI at both SEMICON West and SEMICON Europa, focusing on “Connecting the Automotive Ecosystem Towards More Mature SiC Manufacturing.”This year, we will continue the discussion with industry leaders during our session, “Cultivating a Thriving SiC Market: Tackling Key Challenges Across the Value Chain.” Our goal is to provide insights and propose solutions that will enable SiC power chips to achieve their anticipated role in future technology ecosystems.We will present alongside Porsche Consulting, and the talks will be followed by a panel discussion that will explore the current state and future prospects of SiC technology in power electronics. We invite visitors to join us at the Executive Forum on Thursday, November 14, from 1:40 – 3:00 p.m. and to visit us at Silicon Saxony booth 219 in Hall C1.About Mark PuttockMark Puttock, Ph.D., is the senior director of advanced technology engagements in the office of the CTO at Entegris. He has worked in the semiconductor industry for over 30 years with a background in physics and plasma processing. As a team member of the Entegris CTO office since 2014, Mark has followed technology trends and collaborated with Entegris’ global product development teams to develop timely and differentiated new materials, chemistries, and components for all the world’s semiconductor manufacturers. Maria Daniela Perez is Communications Manager at SEMI Europe.

Electric mobility, renewable energy and other technology innovations like IoT, 5G, smart manufacturing and robotics all require reliability, efficiency, and compact power systems, fueling the adoption of Silicon Carbide (SiC) and Gallium Nitride (GaN) to support lower voltages in significantly smaller devices. But chip designers must overcome the technological and economical challenges of integrating the two semiconductor materials into power systems.SEMI spoke with Elisabeth Brandl, Business Development Manager at EV Group about trends and new developments within the power electronics industry and the devices' application in smart mobility. Brandl shared her views ahead of her presentation at the SEMI SMART Mobility Forum, 18 February, as part of the SEMI Technology Unites Global Summit, 15-19 February 2021, online event. Join us to meet experts from EV Group and other key industry influencers. Registration is open. SEMI: What is driving new developments in power electronics?Brandl: Globally there are significant changes in infrastructure requirements for communication, automotive and power conversion. We need to look no further than the rising adoption of 5G, electric and hybrid vehicles, and renewable energy as examples of drivers of these changes. The device level, particularly in the field of power electronics, figures prominently in these shifts.The power electronics industry faces a growing number of scenarios where conventional silicon power devices are no longer suitable and are easily outperformed by new architectures mainly based on wide bandgap semiconductor materials like Silicon Carbide (SiC) and Gallium Nitride (GaN).SEMI: What industry challenges is power electronics innovation aiming to solve? Brandl: Power conversion efficiency is very important and needs further improvement as the related losses significantly contribute to the overall power consumption. For green power and a better environmental footprint, renewable energy is crucial, but so is overall power-consumption efficiency, yet the role of power devices is often underestimated. High-frequency and high-power applications, such as data center applications and inverters for renewable energy, where silicon power electronics are reaching their limits, are also important areas in power electronics.SEMI: How will the transition from silicon to compound semiconductor materials help?Brandl: The superior material properties of several compound semiconductors can tackle the need for lower losses in power conversion or better high-frequency behavior. Today, we mainly talk about GaN and SiC power devices as they are materials well-suited to address these needs. However, other materials like diamond and gallium oxide are in development for these applications. Material properties of SiC that enable thinner materials with lower power losses and better thermal behavior address power conversion efficiency as well as form factor challenges. GaN, especially in a high electron mobility transistor (HEMT), can be used for high-frequency applications.SEMI: What enables a better and more cost-effective manufacturability of SiC and GaN power devices?Brandl: For the end customer, a typical figure of merit regarding the cost effectiveness is $ per Ampere or Watt. While this seems simple, the reality is of course more complex. It is important to understand the main cost contributors within the manufacturing area. For SiC, this is clearly the substrate cost. In my presentation, I will show a way to reduce this cost via wafer bonding. For GaN, epitaxy – a method for growing or depositing mono crystalline films on a substrate – is the critical parameter. And of course, yield has a very big impact on cost effectiveness too, which means that good process control including metrology is very important.SEMI: Many semiconductor companies are already transitioning to silicon carbide and gallium nitride. Can you give us an example of a success story?Brandl: All the big power device manufacturers have either acquired or developed their SiC and/or GaN power device technology, so they also see a bright future for these wide bandgap semiconductors in the power device market. The most prominent success story is STMicroelectronics with its SiC MOSFET power devices, which have been implemented by Tesla in its Model 3 vehicles since 2018.SEMI: What is coming next?Brandl: New materials for power devices are being explored, such as diamond and gallium oxide. For SiC, the trend is moving toward 8-inch substrates, which is the focus of the funded EU project REACTION under the coordination of STMicroelectronics. Cost reduction and substrate availability also play a big role. All major power device manufacturers have contracts to secure the supply chain for SiC substrates because material availability is the main uncertainty at this time. Finally, collaborations along the supply chain are crucial and generally beneficial for all parties, as development requirements are better communicated and prioritized.Elisabeth Brandl is Business Development Manager at EV Group. She received her master in technical physics from the Johannes Kepler University Linz, Austria in Semiconductor and Solid State Physics. Since 2014, she has been responsible for Product Marketing Management for temporary bonding and compound semiconductors at EVG. The SMART Mobility Forum is the digital platform of SEMI Europe’s Global Automotive Advisory Council (GAAC) for industry stakeholders along the automotive and electronics value chains, from Design, Semiconductor Equipment and Materials Suppliers to Automotive OEMs.Smart Mobility is one of four SEMI initiatives focused on building communities, content, and activities around critical and emerging electronics markets. Read more about our Regional Chapters.Serena Brischetto is senior manager of Marketing and Communications at SEMI Europe.

Imagine a world where there are chips in about everything we touch on a daily basis. It is not hard to do with semiconductors already at the core of many leading-edge electronic devices. These sophisticated chips are hidden from sight, but their functions are vitally significant to our daily lives.Manufactured in multibillion-dollar facilities, the production process of chips is one of the riskiest, costliest, and most technically complex feats in business. Consider the difficulties of managing contaminants during device manufacturing: A single speck of dust on a lens could cause the entire output of the plant to be scrapped.For years, these exotic fabrication facilities, called fabs, have been packing more efficiency into ever smaller chips. As new technologies continue to emerge, chip manufacturers face constant pressure to continually refine and improve their operations to meet the challenge of rising device performance and yield goals. Fab managers must optimize tool performance, improve fabrication techniques, safely handle toxic materials and design better integration flows. Layer on top of those requirements customer demand for greater innovation and quality of service, it can be difficult for manufacturers to handle everything on their own while consistently meeting necessary requirements.Align for CollaborationWith the help of the Fab Owners Alliance (FOA), a SEMI technology community, manufacturers and their suppliers don’t have to travel this road alone. Membership in this international group allows semiconductor and MEMS fab managers and industry suppliers to come together to solve common non-competitive manufacturing issues and improve business results.Founded in 2004, the group consists of 25+ device manufacturers (DMs) with over 120 semiconductor manufacturing facilities and 60+ solution providers (SPs) who supply equipment and services. Through quarterly meetings, study teams, benchmarking surveys, case studies and online forums, FOA successfully provides a collaborative, non-competitive platform to the fab management and operations community. FOA members enjoying an engaging discussion and networking event during the recent Q1 2019 Collaborative Forum at the Double Tree Resort in Scottsdale, Arizona One of the most popular FOA platforms is the annual Collaborative Forum early in the year. The goal is to bring together DMs and SPs from around the world for an open dialogue under one roof. For two days, they share success stories and discuss issues facing their fabs and the industry in general and develop collective strategies to address them.The success stories are particularly engaging as they accentuate the value and benefits of FOA membership. Presented as case studies, these stories outline how the DMs and SPs work together to improve fab efficiency and increase yields. Often, the ideas for the case studies are conceived during networking events, fab tours and programs organized by the FOA.The case studies shared at the 2019 Collaborative Forum, held at the Double Tree Resort in Scottsdale, Arizona, February 13-14, 2019, illustrate the power of collaboration within the FOA. Following are a few examples.Scheduling System Implementation Broadcom was facing a steep ramp when it decided to engage with FPS, an INFICON product line. In addition, the manual decision making, and limited real-time visibility of factory data was negatively impacting their production in its 150mm and 200mm environment. By deploying an integrated Smart Manufacturing software solution and its digital twin, FPS was able to retrofit Broadcom’s manual factory with automated decision-making capabilities.This solution offered many benefits. Constraint tool utilization increased by more than 15 percent. The automated WIP management system also eliminated many manual wafer handling issues such as lost lots, WIP storage constraints, building transfers, and time spent looking for lots. Pushing Tool Performance BoundariesAs tools in the 200mm space are hard to find, GLOBALFOUNDRIES is always looking to squeeze every wafer out of its existing resources. To drive continuous improvement and increase equipment throughput, GLOBALFOUNDRIES leveraged MAX’s knowledge with Machine Rate Models. Together, they were able to employ a modelling technique that helped them model key toolsets and develop actions to increase intrinsic machine rate performance.Based on this knowledge, 10 capacity constraints were selected, and speed models were developed for all of them. This win-win collaboration allowed GLOBALFOUNDRIES to find some real opportunities that translated into CAPEX and cost savings. On average, the companies identified a 12 percent potential improvement opportunity per toolset and created engineering task force teams to prioritize and drive the improvements.Simplifying the Chamber Matching Process Using Trace AnalyticsThe collaboration between NXP and BISTel resulted from a shared vision of achieving Smart Manufacturing using analytic solutions enabled by artificial intelligence and other advanced technologies. Chamber matching is critical in identifying process variation to ensure manufacturing quality. Traditional tools like Fault Detection Classification (FDC) often do not provide clear enough insights to pinpoint the issues and require extensive time to collect data from each chamber.Through several use cases, NXP and BISTel successfully illustrated the effectiveness of using a trace analytic solution to quickly and accurately quantify and monitor chamber-to-chamber mismatches as well as changes within a chamber over time. The full trace analyses of all parameters allowed NXP to generate better FDC models to more quickly detect similar issues in the future. In addition, NXP was able to identify the cause of a parametric shift by comparing performance of the same chamber between two different time periods. All in all, the trace analytics solution brought together and analyzed the process data efficiently, thereby reducing analysis time from days to minutes.Eagleview Inspection of SiC and Transparent Wafers X-FAB challenged Microtronic to develop a new capability for its high-throughput recipe-less macro defect inspection systems. Microtronic’s EagleView machine vision macro defect inspection system is well known for its versatility in the semiconductor industry due to its wide deployment as well as its recognition as winner of the 2017 Best of West Award at SEMICON West. But X-FAB’s requirements to inspect and image transparent wafer substrates were novel. After working closely to understand X-FAB’s needs, Microtronic made extensive hardware and software enhancements to enable high-throughput macro inspection of Silicon Carbide (SiC) and other transparent wafer substrates.Get InvolvedThe FOA meetings are held at device manufacturing sites twice a year. The next meeting will be graciously hosted by MACOM in Lowell, Massachusetts, May 22-23, 2019. The DMs and SPs will meet again at SEMICON West at the Moscone Center in San Francisco on July 11, 2019.To attend these meeting and be part of this high-impact group, please email us at [email protected]. For more information about FOA, please visit our website.Nishita Rao is a marketing manager at SEMI.

Device manufacturers continue to invest. Spending in cloud data center (compute, networking and storage), automotive (content per car increases), industrial (on content, factory automation, and positive macro trends), and consumer (gaming) end-markets is particularly strong. We see capital expenditure growth in 2018 and early indications pointing to sustainable spending into 2019. We also expect 14 percent increase (YoY) for fab equipment spending in 2018, up from the February forecast of 9 percent, and expect 9 percent increase in 2019, adjusted from the February forecast of 5 percent. 92 future facilities/lines with various probabilities are scheduled to start production in 2018 or later. Fab investment is just one indicator of how growing demand in areas such as from Artificial Intelligence (AI), cloud/data storage, automotive and Internet of Things (IoT) is driving unprecedented spending in the semiconductor industry. Below are a few highlights* of recent SEMI FabView insights. Details of each project can be found in FabView online 24/7 or World Fab Forecast report (Excel format). Infineon’s new 300mm Fab in Austria - Infineon is planning a new 300mm thin wafer Fab for Power Devices in Villach, Austria. Rumors on Toshiba’s new Fab plans - More 3D NAND fabs in the future at Toshiba are feasible. The timing will depend on market conditions, and our forecast will adjust accordingly. Vanguard's possible 300mm foundry fab - Vanguard's management said it might buy or build a 300mm fab in the near future as all 200mm fabs are essentially full. Powerchip plans to build new memory fab in Taiwan - Powerchip is investing more in expansions since Memory pricing is holding up. Rohm announced to build a new SiC fab in Fukuoka Japan - Rohm announced its plans to build a new SiC fab. Micron is building a new fab in Singapore - Micron broke ground in a ceremony for a new fab in Singapore on April 4, 2018. Bosch had groundbreaking ceremony of their 300mm fab in Dresden end April 2018 - Investment of 1 billion Euro. This is the biggest single investment in Bosch’s 130-year history. SEMI FabView, a mobile-friendly, interactive version of SEMI’s popular World Fab Forecast, delivers on-demand fab information such as fab spending and capacity for over 1,100 facilities, including over 82 planned facilities worldwide, across a wide range of product segments including Power, GPU, Memory, Foundry, MEMS and Sensors fabs. Fab data include region, start of construction, operation, construction and equipment spending, capacity, wafer sizes, product types and geometries. SEMI FabView subscribers receive forecast model updates through SEMI’s World Fab Database. Click here for a trial to experience SEMI FabView first hand. *Actual updates provide more detail Christian G. Dieseldorff and Clark Tseng, Industry Research Statistics Group, SEMI.