ESD Alliance

Alameda, Calif.-based Verific Design Automation, a member of the ESD Alliance, made its name in the electronic system design and semiconductor industry supporting companies ranging from startups to billion-dollar industry leaders such as Synopsys, Cadence, Siemens EDA, Xilinx, Microchip, NVidia, Infineon, Qualcomm, Renesas and Samsung. Its software is used as the front end to design automation tools such as synthesis, simulation, debug, and formal verification. I spoke with Verific president and COO Michiel Ligthart about homegrown and open-source EDA tools and other recent trends in chip design. Smith: What trends are you seeing in chip design? Ligthart: Semiconductor companies are starting to build a portfolio of intellectual property, including homegrown electronic design automation (EDA) tools, that they want to keep secure and differentiated from their competitors. The increased interest in internally developed and supported EDA tools is a trend we started to see about two years ago. It’s not simulation, synthesis or place and route (P R). Instead, it’s pieces of a chip design flow optimized for a company’s specific needs. In the past, a semiconductor company would either standardize on one EDA company’s chip design flow or mix and match best-in-class tools from different vendors. The common denominator was that they used off-the-shelf products. If they had a specific requirement, they went to the EDA provider for assistance. In today’s competitive landscape, semiconductor companies are figuring out ways to diversify themselves and their design flow became a way to do so. They may not build their own P R tool, but they will look at building their own power domain approach, for example. Is this a widespread trend? It could be. We hear about it within end-user applications ranging from 5G and AI to data center processors and there are probably others we don’t hear about. Power optimization is an example of the kind of specific internal need being addressed. Smith: What are your thoughts about open-source EDA tools? Ligthart: Our industry supports open source already with language reference manuals (LRMs) for VHDL, SystemVerilog, Unified Power Format (UPF) and the RISC-V Instruction Set. The LRMs and the instruction set are free. Moving to the development of actual tools becomes a question of who will implement, support and maintain the tools. Implementation is expensive. The Big Three (Cadence, Siemens EDA and Synopsys) invest about 35 to 40% of top-line revenue into R D. For smaller EDA companies, this number is even higher. The industry may come up with a business model that will have open-source components as well as a way to fairly reimburse companies that make these tools freely available. I have not seen it yet. Smith: Business Insider reports that Verilog HDL is among the top 10 tech skills that companies are desperate for their employees to learn right. Does Verific get asked about Verilog training? Ligthart: No. Our customers are experienced users. Nonetheless, it was great to read that article and it suggests the semiconductor industry is healthy, growing and hiring talented engineers. Smith: If an entrepreneur asked you for advice about starting an EDA or IP company, what advice would you provide? Ligthart: I would tell the entrepreneur to focus on the problem the startup is solving. Stick to the company’s core competency and try not to build in-house what can be purchased from a reputable supplier. In the end, it will save time and jump-start the development effort, and the engineering budget can be allocated to the startup’s core competency. The external supplier presumably has years of product validation, which brings a major QA gain. About Michiel Ligthart Michiel Ligthart, president and COO of Verific Design Automation, has an extensive background in engineering, product marketing and general management. Prior to joining Verific, Ligthart was vice president and general manager of West Coast operations for Theseus Logic, a startup in asynchronous logic. Before that, he spent eight years with Exemplar Logic in engineering and marketing roles. Ligthart started his career with Philips Research Labs in California and was a visiting scholar at the Center for Integrated Systems at Stanford University. He has a Master of Science degree in Electrical Engineering from Delft University of Technology, the Netherlands. Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community.

Spend any time with Ansys’ John Lee, Rich Goldman or Marc Swinnen and you’ll hear plenty of optimism about the semiconductor industry even though they tick off a long list of looming design challenges. The need for reliable and effective electronic systems, they emphasize, is great and runs through high tech, aerospace and defense, automotive, IoT and 5G with communications being a common denominator. The three are especially bullish these days on changing market dynamics brought on by systems companies building company-specific bespoke, or custom, silicon. These systems companies are building chips with a different perspective and a fresh look at silicon design, a move away from the more traditional segment-specific silicon due to much more complexity. Ansys, a member of the ESD Alliance, a SEMI Technology Community, is a 4,100-employee company with a comprehensive portfolio of multiphysics engineering simulation software for product design, testing and operation products and services. John, Rich, Marc and I focused on Ansys’ semiconductor and electronics segment for our conversation. Smith: When did you notice the move by systems companies to build their own chips? What drives this trend? Lee: The inflection point was about three years ago when hyperscale data center and system companies recognized they needed an enterprise system design platform. They are designing bespoke silicon, driven to do this for cost efficiencies and to avoid relying on outside suppliers. They also want differentiation based on their specific platform needs so they can optimize compute power to their specific needs. Smith: What is driving the trend for multiphysics experience to ensure effective and reliable electronic systems? Lee: The increasing need for multiphysics analysis is acute. The physics of 3D IC, for example, brings in mechanical engineering with the convergence of mechanical and electrical as 3D emerges at the intersection of IC and System. As a result, physics becomes a necessity to analyze the stability of the chip in the package. Goldman: As well, the move to stacked chips, 3D IC and wafer-on-wafer requires thermal, electromagnetic and mechanical analysis in addition to the traditional analysis for function, performance and power. They all need to be analyzed together, not serially. It becomes multiphysics, not multiple physics. Smith: Two distinctly different disciplines – multiple physics and multiphysics – are needed for semiconductor design. How are they different? Why the need now? Swinnen: Multiple physics refers to the sheer breadth of physics that is now needed to analyze from the IC up to the largest system whereas multiphysics refers to the capability to analyze several physical effects concurrently, accounting for their impact on the design and interactions between various physics. Multiphysics are necessary to analyze the full context of the system environment – from nanometers to kilometers – for multi-chip packaging, chip-to-package-to-silicon and systems with multi-domain guidance. Goldman: A self-driving car, as an illustration, includes AI systems-on-chip, solid-state sensors, infotainment systems and radar/lidar detectors that must all work in the rain, the heat and the bitter cold. Smith: Why are design groups being reorganized to include expertise in mechanical and electromagnetic issues? Swinnen: Complexity has exploded, driven by a long list of technical requirements and, perhaps, mischaracterization. Goldman: Just consider the system on chip, mischaracterized by the semiconductor industry. The chip is never a system by itself. Rather, it is a complex component in a larger system and must be analyzed in that context. 3D IC is where this comes together and forces a recognition of physics outside the traditional scope of SoC design. 3D IC chips are much closer together on the board and it takes multiphysics embedded into the workflow of semiconductor design, packaging, system design and 3D IC to ensure they work reliably and efficiently. Smith: What is the solution? Goldman: It’s clear a specialized digital thread is necessary to move disparate groups with expertise in systems, physics and silicon together. Today, these groups or disciplines might not exist in the same company, whether it be a foundry, fabless or outsourced semiconductor assembly and test (OSAT) company. Lee: In order to unify the entire system design environment, a cloud-based, open and extensible heterogenous enterprise compute platform is required. It is similar to the SaaS-based business model and known as Simulation-as-a-Service (also SaaS). While vertical integration of design groups is already taking place at leading system design houses, there have also been advances in electronic design tools. These are starting to offer more comprehensive multiphysics capabilities including thermal, fluid dynamics (CFD), mechanical stress and reliability analysis in a single analysis cockpit. Today’s system designers face two platform challenges: First, they need an environment that is open enough to accept analysis results from multiple sources so that they can be overlapped and cross-analyzed. Second, the design platform must have the capacity to handle the enormous amounts of data generated by the latest 3-nanometer chips and 3D IC systems, and this implies an intimate coupling to elastic cloud computing. The days of an engineer writing Perl scripts and handing it off to someone else are gone. We believe that the industry is responding to this challenge with a new generation of design platforms that a cloud-native, open and extensible to allow heterogenous enterprise design. We are definitely at an inflection point in electronic design today, but the electronic industry has faced these before an we are confident it will master these challenges as well. About Rich Goldman Rich Goldman is director of marketing for the Electronics and Semiconductor Business Unit of Ansys. He holds a Bachelor of Science degree from Syracuse University and an MBA and Master of Science degree in Engineering Management. Moscow Institute of Electronic Technology (MIET)’s first honorary professor, he is also the recipient of honorary PhD degrees from Russian-Armenian (Slavnoic) University and State Engineering University of Armenia for contributions to the advancement of Armenia’s high-tech education and economic ecosystem. Rich served on EDAC’s board of directors. About John Lee John Lee is general manager and vice president of the Ansys Electronics and Semiconductor Business Unit. Lee co-founded and served as CEO of Gear Design Solutions (now Ansys), developer of the first purpose-built big data platform for integrated circuit design. He cofounded two other startups (Mojave Design and Performance Signal Integrity), which successfully exited into companies now part of Synopsys. He holds undergraduate and graduate degrees from Carnegie Mellon University. About Marc Swinnen Marc Swinnen is director of product marketing for the Electronics and Semiconductor Division of Ansys. He holds Master degrees in Electronic Engineering and Industrial Management from KU Leuven, Belgium, as well as an MBA from San Jose State University. About Bob Smith Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community. He is responsible for the management and operations of the ESD Alliance, an international association of companies providing goods and services throughout the semiconductor design ecosystem.

In the span of a few short months earlier this year, Mentor Graphics became Siemens EDA and introduced a suite of integrated hardware-assisted verification tools, the first product launch under the new Siemens EDA brand. Jean-Marie Brunet, senior director of marketing, product management and product engineering at Siemens EDA, orchestrated the launch and connected with me for a discussion about the chip design verification space. As he pointed out, verification and validation of systems is a fast-growing and important market segment to the electronic system design ecosystem. Smith: What trends do you see in chip design? What is driving these trends? Brunet: Chip verification costs continue to grow faster than design costs because of factors such as increasing design complexity, rising computing power, surging I/O traffic activity, increasing energy consumption and the widespread use of peripherals. These dynamics are being driven by new data center networking, communications/5G, autonomous driving, artificial intelligence (AI) and machine learning (ML), and storage applications. These trends also indicate the need for more powerful verification tools and expanded verification objectives that include power and performance analysis. Hardware-assisted verification tools are perfect for meeting these demands. Smith: Chip design verification consumes the most time in a project cycle. Why is this so? Brunet: The verification of designs reaching multi-billion gates and supported by voluminous software stacks is fraught with challenges. To exhaustively check every possible state in a billion-gate design with simulation alone would require up to trillions of verification cycles. That’s why hardware-assisted verification is one of the fastest-growing technologies in EDA. Given the complexity of today’s SoC design, it’s no surprise that verification is the largest undertaking in the entire project design cycle, consuming more than 50% of it. It also has the greatest impact on quality, cost and schedule because it prevents designs from failing at first silicon. While a respin of a large design taped out at a node below 10 nanometers could cost more than $10 million, delaying delivery of a new product for a few months in a highly competitive market may cost hundreds of millions of dollars. Smith: What other challenges do engineers face trying to verify a chip design will work as intended? Brunet: Verifying an SoC design is a massive undertaking and, in parallel, verification teams are trying to streamline and optimize verification cycles. SoC design groups are tasked with completing full system-level verification prior to creating production masks by thoroughly vetting all hardware blocks, interactions between those blocks, and the software developed for the end application before the chip is built. To alleviate this enormous pressure, they are starting to adopt a shift-left methodology for early functional verification as soon as individual blocks of a SoC design become available. It helps jump-start embedded software validation before full system validation is completed to save time and allow engineers to work in parallel, not serially. While it is an effective approach, it creates the need for a complete and integrated suite of hardware-assisted verification tools to verify and validate a design’s hardware and software components. Smith: How do you define hardware-assisted verification and how does it help solve these challenges? Brunet: A typical definition of hardware-assisted verification is special purpose hardware to accelerate verification. In other words, hardware emulation and FPGA prototyping. Hardware-assisted verification is a mandatory investment as single-die or multi-die chips get larger with more complexity and more interfaces, making hardware and software code integration critical early in the design cycle. Because software performance defines a chip’s success, the need to perform software workload-based analysis is acute, not just analysis of chip functionality, but also accurate performance and power consumption in the context of real-world applications. Hardware-assisted verification is the only option when hardware and software meet. By combining emulation, desktop FPGA prototyping boards and enterprise FPGA prototyping platforms to work on the same SoC design, a verification group can assemble a complete hardware-assisted verification system for thorough and exhaustive verification and validation. Smith: Where are the big opportunities for hardware-assisted verification? Brunet: New end-user applications are coming from computing and storage, AI/ML, 5G, networking and automotive. Recently released market data from the ESD Alliance shows that in 2020, hardware-assisted verification revenues exceeded $700 million. It is reasonable to assume that revenues of $1 billion will be within reach in the next few years given the amount of chip design activity at advanced nodes below 10nm. Smith: With the design/verification and manufacturing phases of the semiconductor supply chain more closely aligning, what role does hardware-assisted verification play? Brunet: Semiconductor manufacturing and the supply chain that supports it benefits greatly from the continued innovation in verification and validation tools and methodologies. With this innovation, designs are delivered to the manufacturing flow with a much greater chance of passing first silicon with success. This reduces friction in the semiconductor supply chain since IP and chips are available when anticipated. Hardware-assisted verification is a quick-moving, highly leveraged resource that helps a design and verification team to ensure chips are manufacturable and meet the functionality, power and performance requirements for the end-product application. Jean-Marie Brunet is the senior director of product management and engineering for the Scalable Verification Solutions Division at Siemens EDA. He has served for over 20 years in application engineering, marketing, and management roles in the EDA industry, and has held IC design and design management positions at STMicroelectronics, Cadence, and Micron, among other companies. Jean-Marie holds a Master's degree in Electrical Engineering from I.S.E.N Electronic Engineering School in Lille, France. Jean-Marie Brunet can be reached at [email protected]. About Bob Smith Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community. He is responsible for the management and operations of the ESD Alliance, an international association of companies providing goods and services throughout the semiconductor design ecosystem.

Adnan Hamid, CEO, founder and visionary of Breker Verification Systems, an ESD Alliance member based in San Jose, Calif., once described his job in chip design verification at AMD as “breaking things.” When it came to naming his startup, Breaker was a natural choice. After some consideration, the “a” was dropped and the company became Breker. Now Hamid is breaking the most complex semiconductor designs and Breker, moving from a startup to a scale-up company, is a noted part of the functional verification space. Smith: Why does verification continue to take the most amount of time in a project cycle? Hamid: The project cycle for semiconductor design has changed. Design abstraction has been raised to a much higher level than the days when developers were connecting logic gates. Today’s developers are typing functions that don’t include lower-level implementation details. Designs incorporate more blocks of reusable IP. Both reduce design time. Meanwhile, designs are getting bigger with more blocks of IP stitched together, all in need of testing. As design complexity grows, the amount of testing and verification increases as a square of design effort. One block requires one functional verification effort. Four blocks of IP mean up to 16 functional interactions require verification. While design is moving up the abstraction level, that’s not the case for verification, where plenty of detail must be reimplemented. Verification has certainly evolved, but engineers still think at the level of independent stimulus, response and coverage, driving the need to allocate so much time for verification. Smith: Are chips targeting artificial intelligence and machine learning applications more difficult to verify? If so, why? Hamid: Yes, absolutely and it’s an interesting challenge, especially given that machine learning is based on massively connected processing element arrays. Attempting to verify the individual processing elements and the critical interconnects is complex. AI device arrays and, interestingly, verification test content operation may both be thought of as a mathematical graph of processing elements and interconnect. Their operation involves walking through the graph form to generate a result. Finding the optimum path through these arrays is key. To understand how these systems may be effectively verified, it is worth investigating planning algorithms. Originally proposed by IBM, these hold the key to this type of verification process. The AI- style algorithm starts backward at the end of the processing element array and tracks down the most optimal and likely paths through it. At Breker, we have used these planning algorithms extensively to drive our graph-based test content synthesis process. Smith: Does system integration require verification? Hamid: Yes, it does. In the past, most functional verification has been performed at the block level. However, with the increase in more specialized SoCs, functionality is spread across multiple blocks, as well as the software running on the processors, driving full system-on-chip (SoC) functional verification. In addition, new requirements such as security and safety must be validated. A system-level infrastructure such as cache coherency and power domain execution has become more complex and these must also be tested. The new frontier in verification is ensuring a fully operational SoC. Of course, given the size of these SoCs, hardware-assisted verification such as emulation is essential, and porting tests from block simulations to SoC emulations has become a requirement. This porting process is problematic and this in turn has driven portable tests, giving rise to the idea behind Accellera’s Portable Stimulus Standard (PSS), of which Breker was a major participant. Indeed, some companies are taking this to the next level by composing their system-level testbench at the same time as they commence SoC architectural design, and then developing the hardware design, software design and test content all in parallel, in the so-called “shift-left” manner. Smith: Is “shift-left” a growing trend that are you seeing in verification? Hamid: Yes. Shift-left is taking hold in hardware and software design, giving way to an increase in early test content composition. Then as individual blocks are finished and connected, their verification is driven from this same test content, saving a significant amount of time and effort. This is a huge verification and test generation change that was inevitable given the increased time-to-market constraints and SoC complexity. Figure 1: Shift-left is ushering in the next generation of SoC verification. Source: Breker Smith: As an entrepreneur, what advice would you give someone founding a startup or thinking about starting one? Hamid: Do not take the attitude “Build it and they will come.” My best advice for an entrepreneur or fledgling entrepreneur is to solve a specific customer problem, however narrow it might seem. Including services as part of a product offering and developing partnerships with other vendors helps with this and turns your company into a solution provider not a product developer. This is essential for getting the right products to market on time and within budget, and then ultimately scaling them across the market. The ESD Alliance and Accellera are hosting a two-part webcast series on the work-from-home experience titled Remote Work, Remote Chip Design: Building Chips During a Pandemic. The first panel, Wednesday, June 9, at 9:00am PDT, will feature a discussion led by Tom Fitzpatrick, strategic verification architect from Siemens EDA verification engineers through their experiences converting their home offices into verification test labs. The second panel in July will explore how executives managed a remote workforce and explain how they plan to bring employees back to physical offices. About Bob Smith Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community. He is responsible for the management and operations of the ESD Alliance, an international association of companies providing goods and services throughout the semiconductor design ecosystem.

A change is underway in the manufacturing sector as the use of curvilinear shapes on photomasks grows, leading to the real possibility of curvilinear shapes in designs. It may just be the start of a revolution away from Manhattan or rectangular shapes to curvilinear shapes. Changing the physical design infrastructure to be curvilinear seems too daunting a task. Are curvilinear shapes in designs a real possibility? I turned to Aki Fujimura, CEO of D2S, a member of the ESD Alliance, a SEMI Technology Community, to further explain the shape of the future. Smith: What is the difference between Manhattan and curvilinear shapes? Fujimura: Manufactured masks and wafers are all curvilinear, even if the input CAD geometries are rectilinear (shown in Figure 1). It’s always been true that nature can’t make 90-degree turns, so sharp corners were always a matter of how closely you looked. These days, at the leading-edge nodes and their required resolutions, wafers and even masks are all visibly curvilinear as you can see in the graphic on the left in Figure 2. Since the 1980s, both chip design and chip manufacturing systems have used axis-aligned rectangles, or “Manhattan” geometries, because 1) that was sufficient to design transistors and interconnect for the most part, and 2) CPU-based computer algorithms can be made much more efficient for Manhattan geometries. Curvilinear shapes can be piecewise linear polygons of some resolution, or spline-like formats that are curvilinear at any resolution, or specific curved patterns like circles and ovals. Figure 1: All shapes on masks and wafers are curvilinear, even if the input geometries are Manhattan. Source: D2S Smith: What are the benefits of curvilinear masks? Fujimura: The manufacturing side of the semiconductor community knows that the best possible process window for wafer lithography is obtained by using curvilinear correction of mask shapes instead of Manhattan shapes. There have been numerous studies on the topic over several decades. The technique to generate purely curvilinear mask shapes is known as inverse lithography technology or ILT and is an advanced form of optical proximity correction (OPC). At a February 2020 eBeam Initiative event, Micron Technology presented a study showing process window improvement up to 85% for advanced memory designs as a result of using curvilinear ILT (shown in Figure 2). Additionally, Ryan Pearman from D2S presented a study at Photomask Japan 2019 showing that it is preferable to move toward a completely curvilinear paradigm, not only because ILT is better, but because the mask manufactured will have reduced variability. Figure 2: Micron Technology explained the benefits of curvilinear mask shapes for advanced memory at the eBeam Initiative event during 2020 SPIE Advanced Lithography Conference. Source: Micron Technology Smith: If the benefits have been known for decades, why is it happening only now? Fujimura: Several things happened at the same time. Multi-beam mask writing is now available. GPU acceleration for general computing has become mainstream. And wafer process window (resilience to manufacturing variation) is increasingly a problem for the leading-edge nodes as we are in the 5nm node, going to 3nm. Curvilinear ILT is needed much more now than before, will soon be needed for EUV lithography too, and is now possible because of multi-beam mask writing and GPU acceleration. Smith: Curvilinear mask shapes enable curvilinear design shapes too? Fujimura: Adoption of curvilinear mask shapes is the first step in targeting curvilinear shapes on wafers. Without curvilinear masks, it is difficult to target and reliably manufacture curvilinear designs. Curvilinear ILT works in the pixel-space to output the desired mask shape to maximize the process window for wafer lithography. A side effect of curvilinear ILT is that it can also take curvilinear targets as input. ILT, most likely GPU-accelerated ILT, works with rasterized input data, so the ILT algorithm itself is not affected even in runtime by having any amount of curvilinear design data. The resulting mask shapes are written in multi-beam mask writers, which write pixels with doses. They too will write curvilinear masks at the same speed as Manhattan masks. Suddenly now, curvilinear designs can be handled by chip manufacturing equally well for the first time in about 30 years. Smith: But curvilinear designs would be hard, right? There are a lot of tools that depend on the Manhattan assumption. Fujimura: Yes, you’re right. We’re not going to suddenly see chips that have curvilinear routing all over the place, or curvilinear intra-connect in standard cells or memory cells. The entire physical design infrastructure that includes place and route, timing, custom layout, parasitic extraction and design rule checking moving to curvilinear design all at once is extremely unlikely. Could portions of these problems be tackled for specific cases over time as “hot spot” solutions? With GPU-accelerated SPICE being available now, as an example, if GPU acceleration is adopted for design, the same transformation that happened in manufacturing can (gradually) happen in design too. The key question is whether it’s worth the trouble. Smith: Is it worth the trouble? Fujimura: I don’t know if it’s worth the trouble for the entire infrastructure. For hot spots, “hot” for various reasons, there are certainly benefits. Jogging a 32-bit bus by one grid is certainly much more economical space-wise with curvilinear shapes. Inside standard cells or memory cells, there are certain types of features that pack better with curvilinear designs. In general, interconnect is the limiter to chip size of course, but there are always critical areas that could use help to shrink. There are manufacturability benefits as well. In general, when something changes so drastically as this for the first time in 30 years, there’s bound to be some innovation that takes advantage of the discontinuity. Let’s see what the combined capitalistic power of the entire community might be able to come up with. The first thing is to let everyone know that curvilinear designs will be manufacturable today. Hear insights from other leading electronic system design industry CEOs at the SEMI ESD Alliance CEO Outlook on May 18, 2021, 2:00pm-3:00pm PDT. Panelists will discuss the state of the industry along with their views of the outlook for the coming years. Registration is free for SEMI members. About Bob Smith Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community. He is responsible for the management and operations of the ESD Alliance, an international association of companies providing goods and services throughout the semiconductor design ecosystem.

As we pass the work-from-home one-year mark, most of us still work remotely and will do so for the foreseeable future. As live trade shows and technical conferences were cancelled one after the other, virtual events became the norm. And, teleconferencing became a way of life. While possibly overstating our role, we have the semiconductor industry – from system design through manufacturing and system integration – to thank for a long history of achievement that made the transition to working remotely relatively seamless and straightforward. The shift, in some cases, took some time to sort out as we set up a workable home office, moved to video conferencing with intermittent connections and settled into a routine. Nonetheless, many of us became more productive and, in some cases, even too productive. Each spoke in the global electronic products hub contributed through creativity and innovation with a pinch of ingenuity and grit. Of course, we could have worked remotely 10 years ago, but not nearly as efficiently. Over the last 10 years, the economy moved to the cloud, producing new opportunities across the global market. Many of these opportunities were made possible by the electronic system supply chain and combination of semiconductor technology, electronic product innovation and people who figured how to leverage it with software platforms to tie it together. Zoom, one of our teleconferencing lifelines, is a good example, as are Netflix, our ongoing source of entertainment, and Roblox, a platform to build games. Facebook, Twitter, LinkedIn and the like sourced the news for us and kept us in touch. Amazon delivered our online purchases and GrubHub brought us our takeout dinners. All rely on cloud computing with thanks to the semiconductor industry. Another great example are data centers powered by semiconductors and the amount of data they processed last year. According to International Data Corporation (IDC), 64.2 zettabyte (ZB) of data was created or replicated due to the dramatic increase in the number of people working, learning and entertaining themselves from home. (Its revised model for global data creation and replication predicts the CAGR will grow to 23% over the 2020-2025 forecast period, a sure bet that the semiconductor industry will address ways to manage the growth, possibly through new AI chips.) Our connectivity is driven by smartphones optimized for low power and the performance of more complex chips. Over the last 10 years, design tools have been enhanced and new methodologies have been introduced to respond to the needs of the increasing complex chips for applications that demand high bandwidth, low latency and reduced power consumption and area. Manufacturing is retooling for higher automation under smart manufacturing initiatives and packaging is even more sophisticated with increasing integration and the 2.5D and 3D packaging rollouts. Let’s take stock of our success. The semiconductor industry has a storied tradition of breakthrough technology since its inception. The consumer electronic product craze started when the first PCs were rolled out in 1971, notes the Computer History Museum. Primitive laptops that followed in 1986 gave way to notebooks in 2007 and the ubiquitous smartphone in 2002 – and the rocket fuel for much of this was the buildout of computer networks, hyperscale datacenters and the cloud. Nothing’s been the same since. The next time we turn on our laptop, click on the link for the latest teleconference from our remote home office in comfortable sweats sitting in our ergonomic chair, let’s take a minute to acknowledge our industry’s grand achievement. And, thank one and all for their contribution and consider what’s coming next. About the Author Robert (Bob) Smith is Executive Director of the ESD Alliance, a SEMI Strategic Association Partner. He is responsible for the management and operations of the ESD Alliance, an international association of companies providing goods and services throughout the semiconductor design ecosystem.

Even though microchips continue to get smarter, vital security gaps continue to be exposed through such hack attacks as Meltdown, Spectre, and in recent weeks, Plundervolt. Researchers continue to discover open doors in chip architectures for malicious players to steal increasingly sensitive data, hide the identity of counterfeits, or tamper with electronics systems most anywhere along the global microelectronics supply chain. Today, it’s impossible to have full visibility of the distributed chip making process – from design and fabrication to packaging, testing and delivery. That’s why our industry’s future hinges to a large degree on establishing a hardware root of trust throughout the silicon’s operational lifecycle. Trust but verify! It’s easy to say, but how do we do it?To gain insights, SEMI interviewed Dr. Mark Tehranipoor, currently the Intel Charles E. Young Preeminence Endowed Chair Professor in Cybersecurity at the University of Florida’s Electrical and Computer Engineering Department. A foremost authority on microelectronics security and trust, counterfeit electronics detection, and supply chain risk management, Dr. Tehranipoor will be a keynote speaker at the SEMICON Taiwan Security on Chip Summit, Friday, September 25, where a full program of industry leaders will address key security challenges and solutions involving IoT, systems on a chip (SoCs), integrated circuits, physical unclonable function (PUF) technology, future design, certifications, managed services, and more.For additional insights and to hear Dr. Tehranipoor’s full presentation, register for SEMICON Taiwan 2020, which SEMI is holding as a hybrid event with both a virtual format and an in-show program September 23-25.SEMI: What are the major uncertainties in providing the hardware root of trust within the cyber domain?Tehranipoor: One of the most critical issues we’re dealing with now is loss of control over the process of designing and fabricating integrated circuits and systems. This has happened along with globalization and the movement of supply chain operations overseas to lower costs of nearly all goods, including electronics products and semiconductors. As skill sets, talent, design and fabrication have all shifted offshore, concerns have also risen about security controls across the many different segments of the microelectronics supply chain.For example, when you think about the security of military, space, transportation, power grids, financial or other networks, it becomes a major concern if you cannot trust the underlying electronics system that runs them. New SoCs are also holding more sensitive data around encryption keys, biometrics, personal information or banking data. And as reports escalate about cybersecurity gaps at the electronics part level, it’s increasingly important to establish a hardware root of trust. Today, it’s not enough for a buyer to just call up the design house and verify the electronic ID of an asset. The ID might match, but the device could have been tampered with or replaced with a counterfeit somewhere along its end-to-end journey. Unlike software or networks where problems can be automatically identified, upgraded and fixed, verifying electronic hardware is a costly and time-consuming process, especially when they’re as complex as microchips. It can take months to deconstruct, reverse engineer, inspect, and authenticate a chip. By then, discovery of any security breaches is too late.When addressing the security of electronics systems, there are three important features to keep in mind. First, there’s confidentiality. The device shouldn’t leak information to an unauthorized user. Second, there’s integrity. Unauthorized users should not be able to manipulate an SoC’s sensitive data. The third feature is availability, which can be a result of Denial of Service (DoS) attacks. If the device is under attack and can’t access your online service or network, you must still have security measures for your electronics system to be available in a safe mode while you simultaneously identify the problem, recover from it, and return to normal functions.SEMI: What framework should be followed to establish greater trust and confidence across the entire microelectronics supply chain?Tehranipoor: In the United States, we recognize it may not be possible to bring all manufacturing, design, and delivery teams back to this country and have them certified by the U.S. Department of Defense. You could do some of it, but it would be very costly and complex to bring back all the design, fab, testing, and packaging operations involved with electronics systems and still have complete control.The most practical approach is to make sure we design electronic systems with security and trust in mind from the start. We need to provide security features up front throughout the extended supply chain – into the design flow, fab flow, and out into the field to make it easier and faster for anyone at any point to verify the authenticity of an electronic system as well as identify and mitigate a problem. Finally, we have to remember that we are all in this together – designers, developers, packaging facilities and fabs. We can’t just blame semiconductor manufacturers or any other single entity. As a result, we must be cooperative and collaborative by focusing on this issue as a consortium. Everyone in this ecosystem must come to the table, share best practices, establish standards, and initiate best practices for device to system authentication.SEMI: How can SEMI and the SEMI Electronic System Design (ESD) Alliance help the industry meet these challenges?Tehranipoor: It’s certainly of utmost importance for members of organizations like SEMI and its ESD Alliance committees to jointly develop and adhere to standards or guidelines that establish hardware root of trust across all participants in the global supply chain. At the same time, such alliances should make it a high priority to protect each company’s intellectual property (IP). Collectively, we need resolutions that allow us to develop unique IPs and more easily trace, identify, and verify the authenticity of electronics systems as they flow throughout the end-to-end electronic supply chain. Great efforts are under way and progress is being made. But it’s not enough. Clearly, more needs to be done to establish root of trust standards at the chip level.I can’t emphasize enough the importance of consortia like the SEMI ESD Alliance to create an environment where industry, government, and academia can come together, share best practices and even case studies on how they handled security vulnerabilities and breaches. We understand that not everyone wants to share their security problems, vulnerabilities, or attack surfaces, but learning from each other’s experiences can have a tremendous impact on industrywide progress. If you don’t know what you need to address, you won’t be able to address it when it happens.I also encourage organizations like SEMI to create standards or guidelines that reduce the complexity of microchip designs for security purposes. Realtors often say there are three things to consider in finding a home that will appreciate in value: Location, location, location. To build more secure electronics systems, my mantra is: Automation, automation, automation. Complexity is the enemy of security. By using automation to simplify security mechanisms and detect inconsistencies, it will be easier to find and fix security problems, not to mention lower costs at the same time. SEMI: What will an attendee take away from your talk at SEMICON Taiwan?Tehranipoor: I have a large team of researchers who day and night spot vulnerabilities by attacking and assessing data from different electronic systems set up in our labs. Attendees will see real-world examples and lab animations that show how electronics systems can be hacked most anywhere across the supply chain. They will also learn about step-by-step security solutions we have developed at the microchip level. We need to do a better job of protecting the security of our semiconductor assets and the electronic solutions or services they power. My call to action will be that we need to invest more in research and foster an environment of more open trust and cooperation. We can do this by bringing together different countries, companies, and organizations in the microelectronics ecosystem to overcome this major challenge.Dr. Mark Tehranipoor is currently the Intel Charles E. Young Preeminence Endowed Chair Professor in Cybersecurity at the ECE Department, University of Florida. He is currently serving as Director for Florida Institute for Cybersecurity Research (FICS), National Microelectronics Security Training Center (MEST), CYAN Center of Excellence, and ECI Transition Center. He also serves as Program Director of Cybersecurity for UF Herbert Wertheim College of Engineering. His current research interests include IoT security, hardware security and trust, and reliable circuit design.Samer Bahou is senior manager of corporate communications at SEMI.

About 70% of the U.S. Gross Domestic Product (GDP) is driven by consumer demand. What consumers are looking for is influenced by, for example, fashion trends, product innovations, environmental forces, and personal interests. Regarding personal interests: Sales of electronic components at Fry’s are poor. Radio Shack stores even vanished completely. Today’s consumers do not like to tinker; they want to buy software-enabled, user-friendly systems with over-the-air updating that serves their current and future requirements well – e.g. smartphones. System vendors followed the same transition, and so did semiconductor vendors. Instead of offering (low margin) components, they develop and manufacture big portions of, if not complete, (high value) hardware and software solutions for electronic systems, targeted at specific markets.Mid-August, two SEMI webinars outlined the Smart Mobility market and what it expects from system and semiconductor vendors.SEMI's Smart Initiative“None of us knows as much as all of us,” “Connect – Collaborate – Innovate,” and other strategic considerations have motivated SEMI to become the gateway for the $2 Trillion (= 2,000 Billion) global electronic design and manufacturing supply chain. Figure 1 shows how many companies and organizations have joined this large industry organization, to work together efficiently and serve customer demands cost-effectively. Especially in four high-growth markets/application areas – Smart Data, Smart Mobility, Smart MedTech, and Smart Manufacturing – SEMI enables highly rewarding cooperation. Figure 1: Overview of SEMI members, technology communities, and areas of focus. (Courtesy: SEMI) MEMS and Sensors for Smart Mobility Tim Brosnihan, executive director of MEMS Sensor Industry Group (MSIG), moderated the webinar on MEMS and sensors for Smart Mobility. Bettina Weiss, Chief of Staff and Global Smart Mobility Lead at SEMI, presented the overview. In addition to Figure 1 above, she showed how many companies are now supporting SEMI’s Smart Mobility efforts and have joined the Global Automotive Advisory Council (GAAC). The European GAAC was founded in 2018, based on requests from VW and Audi. Regional chapters have also been formed in the U.S., China, Taiwan, and Japan. Figure 2 shows the current members of the American GAAC – new members are welcomed in all five regions. Figure 2: Current GAAC members in the Americas. (Courtesy: SEMI) Market Trends and Technology Innovations in MEMS Sensors Andreas Breiter, Partner at McKinsey Company, addressed markets, and Armen Mkrtchyan, Associate Partner at McKinsey Company, spoke about technology. Breiter addressed both vehicle and infrastructure changes required, as well as many ongoing and planned activities to enable Smart Mobility. He outlined autonomy, connectivity, electrification, and shared mobility of vehicles as the major opportunities for MEMS sensors. Mkrtchyan showed which technologies enable Smart Mobility and which regions will invest how much in software, hardware, and services by 2030, to capture data and process it in partially/fully autonomous vehicles’ Domain Control Units (DCUs) – see Figure 3. Figure 3: Pre-COVID market estimates. (Courtesy: McKinsey Company) MEMS-based sensors are used in vehicles to monitor pressures and perform as accelerometers or gyroscopes. Non-MEMS-based sensors capture light (e.g. for time-of-flight distance measurements) or magnetic fields (e.g. for RPM measurements). Regarding the many infrastructure upgrades needed for enabling autonomous vehicles on the roads, in Figure 4, Breiter gives road planners a lot of food for thought and planning work. City planners face much more complex challenges. That’s why electronic systems will also be needed to make these large infrastructure investments earn returns. Figure 4: Smart roads are essential for autonomous driving. (Courtesy: McKinsey Company) EDA and Smart Mobility The second Smart Mobility webinar focused on how Electronic Design Automation (EDA) tool vendors, Intellectual Property (IP, System Building Blocks) vendors, and system/IC Design Services can contribute to the success of Smart Mobility. Bob Smith, executive director of Electronic System Design Alliance (ESDA), moderated the webinar, highlighting where the relatively small but essential ESDA and its members fit in the semiconductor ecosystem – see Figure 5. Figure 5: EDA, IP, and design services enable the entire electronics ecosystem. (Courtesy: ESDA) Bettina Weiss explained how SEMI and the Smart Mobility Team are working to bring together stakeholders in the semiconductor ecosystem in general and the Smart Mobility segment specifically, to jointly address topics of common interest, work on solutions and agree upon standards where and when needed. Market Trends and Technology Innovations in EDA, IP and Design Services Andreas Breiter and Armen Mkrtchyan presented McKinsey’s perspectives regarding these topics. In addition to the above-mentioned market data, Breiter emphasized that DCUs are playing an increasingly important role in capturing the data provided by smart sensors, are processing it, and initiating appropriate actions. Together with application-specific software, these DCUs perform tasks like sensor fusion, manage creature comfort, assure safe operation of the vehicle, and secure communication with the outside world (Figure 6). Figure 6: High growth for DCU; likely shift in business models. (Courtesy: McKinsey Company) Mkrtchyan addressed EDA, IP, and services for Smart Mobility from 10 different technical perspectives. Here are the highlights. Component failures can and will have severe consequences in Smart Mobility. Therefore screening, testing, and exhaustive verification are extremely important. Software content is likely to increase at 10% CAGR during this decade. To increase the productivity of software and middleware developers, he emphasized that standards need to be agreed upon. Over-the-air (OTA) updating capabilities are needed. That’s why cybersecurity is important to keep vehicles current and safe. Power train electronics need to function at up to 150°C. New materials will be needed to increase reliability, reduce cooling efforts, and lower unit costs. Last, but not least, Mkrtchyan emphasized that every city needs to design its own infrastructure, not only to enable Smart Mobility but also to monetize the large investments needed; EDA, IP and design support will help to achieve both. In summary, he stated that Design and IP as well as packaging and test will be the most impacted areas in the transition to Smart Mobility. Personal Comments After having attended several MSIG events, I am impressed by how MEMS, NEMS (Nano…), and sensors can lend machines in many ways sight, smell, taste, touch, and hearing. They can replicate these human senses, often better than found in us. If you, like me, celebrated when your first modem enabled your PC to communicate with the entire world, you’ll appreciate the value MEMS and sensors can and will add to machines’ “communication skills.” Also, I can assure you that innovative engineers in this field will find many new ways to capture data in the physical, chemical, and biological domains and enable machines to keep humans safe. (I look forward to a handheld Covid-19 sensor that provides results within a few seconds!) Having worked for a small, then a large EDA vendor, many years ago, and for the ESD Alliance several years ago, I know how difficult it is to motivate innovative software developers to work together or agree upon standards. I am glad that the ESD Alliance is now working closely with SEMI. Most SEMI member companies, and their innovative employees, have learned over the years how important standards are to reduce development cost, processing, and test time, as well as time to profit. I wish Bob Smith and the ESDA members all the best for cooperating closely to define design standards, bi-directional hand-off points up and down the entire supply chain, primarily at the interface between design and manufacturing. I want to encourage EDA and IP experts to work closely with the experienced and knowledgeable people in materials, equipment, manufacturing, and test. 5G mm-wave communication, artificial intelligence/machine learning (AI/ML), reliable solutions for Smart Mobility, and development/characterization of new materials offer great opportunities and challenges for design AND manufacturing. Together, these two big camps can monetize required solutions much better and faster, than on their own. Your contact at SEMI can tell you how and where you can watch the webinar recordings and/or download all the slides. P.S.: Having two eCars and one eBike in our garage encourages me to appreciate SEMI’s efforts in advance Smart Mobility! Republished with permission from 3D InCites.

Automotive original equipment manufacturers (OEMs) and their direct suppliers of parts and systems share a vision: Next-generation vehicles will be more electric, autonomous and connected. At a market size of more than $1 trillion, automotive is steadily becoming a high-tech market as cars morph into advanced technology platforms with partially or fully autonomous features. Call them semiconductors on wheels. Big players such as Google and many carmakers are investing heavily in chip advances to help drive increases in silicon content in automobiles.At SEMICON Europa, Pierrick Boulay, Solid State Lighting and Lighting Systems analyst at Yole Développement, will provide a market update on autonomous automobile trends including the state of sensors, radars, cameras and LiDARs as the industry works to increase the level of autonomy and electrification.Autonomous vehicle design can only thrive with the development of an industry standard for chip and device traceability across the supply chain. The importance of chip traceability to the automotive industry is reflected in its central role in driving a chip traceability standard.According to Heidi Hoffman, senior director of technology communities marketing at SEMI, “chip traceability is one of the next big things for the technology industry. The benefits are enormous, and the upsides – including yield enhancements, counterfeiting safeguards, and support for new applications – are plentiful. But the implementation challenges of chip traceability are also big and will require considerable effort to overcome. The biggest hurdle of all? We need to transcend industry fears by demonstrating that we can secure IP when it is shared across the hardware supply chain.” The Importance of Standards, Data Collection and Collaboration Across the Supply ChainThe automotive industry has long embraced tracing the sources of defects. Now, as the automotive and semiconductor supply chains increasingly overlap, traceability has taken on greater importance in the semiconductor industry. SEMI committees, task forces and events such as the Smart Transportation Forum at SEMICON Europa are ideal platforms for collaborating to develop new standards and best practices for the automotive industry.Earlier this year, German luxury automobile maker Audi AG became the first automotive original equipment manufacturer (OEM) to join SEMI as member, strengthening alignment across automotive supply-chain segments. At SEMICON Europa, the SMART Transportation Forum and Pavilion, staged by the SEMI Global Automotive Advisory Council (GAAC) and bolstered by the Electronic System Design Alliance, a SEMI Strategic Association Partner, will gather key stakeholders across the automotive value chain, from design and semiconductor equipment to materials and carmakers, to explore innovation opportunities in automotive electronics. SEMI Global Automotive Advisory Council (GAAC) “If the industry wants to reach the goal of zero defects, a new collaborative approach is necessary,” observed Antoine Amade, senior regional director EMEA at Entegris. At SEMICON Europa, Amade will present new ways to collaborate in reducing chip defectivity and meet other challenges in the automotive industry.More than half of semiconductor failures on the automotive assembly line today (so-called 0km failures) are traced to semiconductor fab defectivity. “The increasing semiconductor content in automobiles – driven by growth in ADAS, electrification and autonomy – has put a growing focus on the quality and reliability of these devices and their implications for consumer safety and satisfaction,” said Oreste Donzella, senior vice president and CMO at KLA.The smart manufacturing (Industry 4.0) revolution is already spurring higher performance and great efficiencies throughout the supply chain and will also be crucial to driving innovation in automotive. Smart manufacturing makes possible significant improvements in factory key performance indicators (KPI) for cycle time, on-time delivery, overall equipment effectiveness, cost and product quality.“These KPI gains are key to meeting quality levels the automotive industry must reach to support the deployment of autonomous driving vehicles,” said John R. Behnke, general manager of Final Phase Systems at INFICON. In his talk at SEMICON Europa, Behnke will provide an overview of existing, in-progress, and future smart manufacturing solutions for the semiconductor industry and their impact on the automotive supply chain. The SMART Transportation Forum, 13 November, 2019 (9:30-15:30 at ICM Munich, room 14c) at SEMICON Europa is the premier platform for key stakeholders to connect, collaborate and innovate across the automotive value chain. Automotive and semiconductor industry experts will offer insights into trends in design, semiconductor equipment and materials, and automotive innovation and the roadmap to 2030. The SMART Transportation Forum will also showcase innovations in imaging, sensing, artificial intelligence (AI), smart manufacturing and L5 mobility.Other SEMICON Europa highlights: Advanced Packaging Conference: Packaging and Test Challenges Towards High Reliability (12-13 November 2019) 23rd Fab Management Forum: Game Changers for Semiconductor Operations(11-12 November 2019) Strategic Materials Conference: Strategic Materials Enabling Industry Roadmaps(12-13 November 2019) SEMICON Europa registration is open for visitors and exhibitors. For more details, please visit the SEMICON Europa website and connect with SEMI Europe on Twitter or LinkedIn @SEMIEurope (use #SEMICONEuropa).Learn more about the SEMI chip traceability standard – SEMI T23 - Specification for Single Device Traceability for the Supply Chain – and SEMI Technology Communities.Serena Brischetto is a marketing and communications manager at SEMI Europe.

New system-on-chip (SoC) devices are driving new memory architectures and photonic interfaces, while specialized new intellectual property (IP) requires analysis down to the nanometer and atomic levels because of single nanometer process nodes. According to Babak Taheri, CTO and EVP of products at Silvaco, a leading EDA Software, semiconductor IP company, a member of SEMI and the ESD Alliance, a SEMI Strategic Association Partner, design technology co-optimization and proven IP are required for this analysis.Taheri recently discussed atoms to systems in next-generation SoC designs with Nanette Collins ahead of ES Design West, co-located with SEMICON West, July 9-11 at the Moscone Center in San Francisco.ESD Alliance: For years now, the assumption is that each new chip design is more complex than the last. Why are the latest SoC designs even more complex than before?Taheri: New SoC devices for mobile phones, automobiles, intelligent edge nodes, big data compute and storage are adopting artificial intelligence and machine learning technologies. This is driving new compute, data flow, as well as memory architectures that are bandwidth-limited and some require photonic interfaces.One common denominator in present SoC design are the numerous blocks of IP. On average, over 85% of these blocks are reused. It’s cost-prohibitive to make these chips over and over again with new IP. According to some estimates, 90% of IP used in an SoC design by 2025 will be reused – only 10% is new technologies. That 10% is significant.ESD Alliance: How so?Taheri: Complex new technologies including flash memory, other advanced non-volatile memory technologies such as MRAM, RRAM and SoCs such as NVIDIA’s Xavier and Apple’s A12 use and reuse design IP at the architectural level.New technologies mean new materials and new processes. Single nanometer process nodes require specialized new IP that needs to be simulated and analyzed down to the nanometer and atomic levels.ESD Alliance: Does the atomic level changes the design equation?Taheri: Yes, it does. Designers need to be able to simulate at the atomic level and understand properties of these materials, and how they behave in at-process and at-device levels. They need be able to simulate the material's nanometer geometries, how molecules behave and how they interact for device operations. When they put together a process and a device, they need to know how the pieces behave and simulate before production.In other words, they run quite a few design experiments and quite a bit of simulation before they finalize the circuits and devices to silicon to save money.ESD Alliance: It’s obvious design automation will continue to have a vital role in design.Taheri: Yes, absolutely. Design technology co-optimization (DTCO) using TCAD solutions and proven design IP are needed to address the span from architecture to device and process physics. The importance of simulation, emulation and design technology co-optimization, along with fully verified and proven IP for SoC design, cannot be overstated. As designers generate devices and processors, they take that up to circuit-level simulation and high-level simulation, schematic capture, extractions and back annotation. They can go from atoms to simulating systems to the ability to do that under the same umbrella in order to get better chips, better yield and lower cost.Taheri’s talk Next Generation of SoC Design: From Atoms to Systems will be part of the Meet the Experts More than Moore session Tuesday, July 9, at 11:30 a.m. at the ES Design West SMART Design Pavilion. SEMICON West attendees are invited to Moscone Center’s South Hall to learn more about electronic system and semiconductor design and its links to the electronic product manufacturing and supply chain. Register for ES Design West or SEMICON West.Babak Taheri is Silvaco’s CTO and EVP of products, has more than 25 years of design experience. His current role managing Silvaco’s Technology CAD (TCAD), electronic design automation (EDA) and IP product divisions makes him an expert on what’s needed for the design of next-generation system-on-chips (SoCs). Previously, he was the CEO and president of IBT working with investors, private equity firms, and startups on M A, technology and business diligence. Babak received his Ph.D. in biomedical engineering from the University of California Davis with Bachelor of Science degrees in Electrical Engineering and Computer Science and Neurosciences. He has published more than 20 articles and holds 28 issued patents.Nanette Collins is a public relations representative for the Electronic System Design Alliance.