computing

Artificial intelligence (AI) is scaling at a pace that is reshaping semiconductor roadmaps, data center design, and long-term infrastructure strategy. AI promises many economic and social benefits; but the growth comes with an escalating demand for power, and energy has emerged as a major challenge.SEMI, as the global semiconductor and electronics association connecting over 4,000 companies, continues to unite the entire ecosystem to “bend the curve” – to maximize AI performance while minimizing power consumption. In a series of successful, sold-out workshops that the SEMI Smart Data-AI Initiative held on this topic, a resonant theme has emerged: sustaining AI progress requires energy-efficient computing with holistic co-design and co-optimization across materials, devices, systems, data transmission, data centers, emerging architectures and software. While this dialog is an important starting point, the ultimate goal is to drive concrete action through collaborative innovation.The AI Energy ChallengeAI training compute for frontier models is growing at an estimated 4–5x per year, driving unprecedented demand for hardware capability and infrastructure capacity. That trajectory has resulted in a global “data center gold rush” and is testing energy availability limits. As model sizes scale exponentially, so too does the energy required to train and deploy them; and power consumption has become a significant limiter to performance gains. Further, this increases heat dissipation, and requires innovations like direct liquid cooling.Modern AI and high-performance computing systems now operate at levels comparable to small cities, with tens of megawatts per installation and a trajectory toward gigawatt-scale data center campuses. Grid capacity—both in the U.S. and globally—may be challenged to keep pace with projected demand. Thus, AI infrastructure is no longer just a technical challenge, but it is an energy, systems, and policy challenge.System-Technology Co-OptimizationContinuous advances in chip and inference efficiency have delivered orders-of-magnitude improvements over many decades. These gains must now be expanded by holistic co-optimization of the entire compute system from silicon technologies to data center to the grid.For example, processors can be made more efficient by customizing them for specific workloads. However, only part of total data center power is consumed by the processor itself. A significant portion is used by data movement, power conversion and cooling. The energy required to move data increases dramatically with distance. Moving bits across packages, boards, and networks can consume far more energy than the compute operations themselves. This makes locality a critical design principle. The opportunity—and necessity—therefore lies in cross-layer optimization: efficient compute, efficient communication, and intelligent power management across the entire system. Not surprisingly, advanced packaging and integration are becoming central to performance. These technologies can enable architectures that tightly couple compute, memory, and I/O—using 2.5D and 3D integration techniques—reducing energy per bit and increasing bandwidth. Photonic interconnects and low-power materials can further lower the cost of processing and moving data.The bottom line is that incremental chip-level gains alone will not be sufficient and energy optimization cannot be siloed—system-technology co-optimization is needed.Hardware-Software Co-optimizationKeeping data as localized as possible depends as much on software algorithms as it does on hardware architectures. The challenge is that the development cycles are mismatched: new software models can be developed in months, while designing and fabricating new hardware can take years. While this cycle mismatch is fundamental, closer coordination between hardware and software developers can significantly improve efficiency. For example, offloading selected functions in the algorithm, including distributed DPUs, and reducing the level of data precision can reduce energy use. Partitioning workloads logically across the hardware/software stack between cloud services and compute-on-edge can also reduce energy appreciably. Further, risk mitigation techniques—for example, building in strategic redundancy—can make future designs more resilient to shifts in software algorithms and models.Diverse Computing ModalitiesWhile AI dominates current infrastructure investment, the future of computing will likely include multiple, diverse computational modalities such as quantum, neuromorphic, photonic and analog computing.Different computational paradigms will be applied where they are most effective. For example, quantum computing is likely to complement—not replace—classical systems; especially for specific classes of problems where it offers exponential advantages. However, progress in quantum computing is tightly coupled to advances in semiconductor infrastructure. Error correction, orchestration, and hybrid algorithms all depend on high-performance classical systems operating with low latency alongside quantum processors. While there is no single silver bullet, system-level design can ensure that multiple computing modalities work together within unified workflows spanning edge, cloud, and exascale environments.Why It Matters What to WatchEnergy will now be a key constraint for AI performance and infrastructure expansion.The evolution of gigawatt-scale AI campuses and their interaction with public energy grids will accelerate – or slow down – AI growth.Data movement, memory bandwidth, interconnect efficiency, advanced packaging and heterogeneous integration will be strategic levers. Enhanced system-technology co-optimization and integration of advanced technologies like 3D ICs and photonics will be critical.Co-optimization across hardware, software, and systems will be required.Future architectures will blend classical and emerging compute modalities like quantum, photonic and neuromorphic.In conclusion, AI has become a defining global force with much promise, but its trajectory will be shaped by technology, energy and infrastructure economics working together. This is a formidable challenge because it requires many diverse players with divergent priorities to collaborate effectively.We invite you to join the SEMI Smart Data-AI initiative to collaboratively address this challenge and help realize AI’s full potential sustainably. Our next workshop in this series will be on September 9 in Silicon Valley – please join us for this exciting event.SourcesSEMI Smart Data-AI Initiative – Future of ComputingEnergy-Efficient Computing for AI and Beyond, SEMICON West, October 2025Sustainable AI Systems, SEMI HQ, March 2026About the AuthorsDr. Pushkar P. Apte is the Strategic Technology Advisor for SEMI Global Lead for the Smart Data-AI Initiative Dr. Melissa Grupen-Shemansky is Senior VP and CTO of SEMI

AI is proliferating rapidly, fueled by ever-larger models and data sets that are expanding AI use cases and improving its accuracy. Future computing systems are now required to simultaneously deliver high performance, process large amounts of data, and use the least possible energy. The growing energy footprint of AI and the strain it places on the power grid is an increasing concern for companies and even entire countries. This could adversely impact future growth and could slow the semiconductor industry’s march towards $1 trillion in revenue, which is largely driven by AI applications.This is a formidable challenge that cannot be addressed in silos by individual companies or even industry segments. The SEMI Smart Data-AI Initiative is exploring how to overcome this challenge with collaborative and innovative system-level solutions that connect the dots across the entire AI system stack. In March 2025, we hosted a successful workshop, bringing together industry leaders across the value chain for a day of thoughtful discussions and knowledge sharing. Building on this foundation, we developed an exciting Smart Data-AI session to be held at SEMICON West in Phoenix, Arizona on October 7 from 10:30 a.m.-4:40 p.m. The “Future of Computing: Energy-Efficient Computing for AI and Beyond” forum will bring together executives and thought leaders across the entire ecosystem – including design, fabrication, interconnects, system integration, hyperscale architectures, advanced materials, and emerging technologies such as photonics and quantum. Attendees will have a unique opportunity to get strategic perspectives from these distinguished experts and learn about exciting future trends.Why Attend?Gain insights from global leaders and learn about innovative paths towards an energy-efficient computing future.Network and build cross-industry collaborations for the next wave of AI, photonics and quantum.Promote a more sustainable path for continued growth of AI to benefit humanity and the planet.Join the SEMI Smart Data-AI initiative to develop solutions and take concrete actions to reduce AI’s growing energy footprint.Support the industry in achieving its goal of reaching $1 trillion in revenue. Speaker Highlights Include:AMD • Ciena • Hewlett Packard Enterprise • IBM • Merck KGaA, Darmstadt, Germany •Microsoft • Quantum Economic Development Consortium • Rapidus • Rigetti •Siemens AG • Stanford UniversityDr. Pushkar P. Apte is the Strategic Technology Advisor and leads the Smart Data-AI Initiative at SEMI.

As artificial intelligence (AI) proliferates rapidly, AI models and datasets are also growing rapidly in size. This growth far outpaces performance improvement in hardware systems, and is increasing AI’s energy consumption unsustainably. To address these challenges and explore collaborative solutions, SEMI’s Smart Data-AI Initiative - as part of its Future of Computing focus - recently hosted a day-long workshop on Sustainable AI Systems that brought together domain experts from the entire AI ecosystem. Speakers included industry leaders Applied Materials, AMD, Arm, ASE, Google DeepMind, IBM, Intel, Lam Research, McKinsey, Micron, NVIDIA, Qualcomm, SK hynix; exciting start-ups Cerebras, LightMatter, Mentium Technologies and Mueon; and leading-edge academic institutions, Stanford University and University of California, Davis Irvine. The keynotes, panels and spirited audience discussions covered novel devices, materials, advanced packaging, chiplets, photonics and architectures algorithms for data centers, cloud edge. This article synthesizes high-level insights from the workshop.The AI ImperativeThe day started with a basic question – why is AI essential to continued progress and prosperity? The answer lies partly in shifting global demographics, with the population aging in most developed economies. At the turn of the century, there were ~6 people in the workforce supporting each retiree, but projections indicate there will be only 2 active workers per retiree by 2050. In parallel, productivity growth rates have fallen to half of what is required. AI can help bridge this gap, if we can ensure continued progress of AI in a responsible and sustainable manner.The Energy WallA formidable roadblock to continued progress of AI is its rising energy demands. For example, the energy used by some large language models (LLMs) to run just one training cycle could be used to power thousands of homes. The switch to transformer models has increased AI-driven computing demand by a factor of 50 million over 5 years, and by some projections, this demand will consume half the world's generation capacity by 2050. This is clearly not sustainable! All players in the ecosystem are deeply committed to reducing AI’s energy consumption, and the industry has already decreased the energy used per token of computing by a factor of 100K in the past 10 years. However, the rapid growth of AI outpaces this, highlighting the huge challenge ahead.The System StackThis workshop was developed with the hypothesis that innovation is required across all segments, and an important first step is to initiate a dialog. Our highly distinguished speakers covered the entire solution stack, and while it is impossible to capture the ocean of insights that they shared, the following provides a flavor.Materials DevicesMaterials and devices used to build semiconductor chips form the foundation of the stack for all computing systems. Silicon substrates with copper interconnects remain industry’s mainstay, but are being augmented by innovative ideas. As device dimensions continue to shrink, novel 2D materials such as MoSe2, WSe2, ZrSe2 and NbP are being researched. While Si mobility degrades with decreasing film thickness, 2D materials maintain high electron mobility in thin-film substrates. These can be stacked to build 3D systems with lower power consumption than traditional planar structures. In parallel, novel device technologies such as gate-all-around (GAA) can provide power savings up to 25%.These novel materials and devices are complex, and require almost magical wizardry to build. For example, they may require depositing a stack of multiple defect-free films that are only a single (or few) atomic layer(s) thick, or etching a steep well that is one hundred times as deep as it is wide. It is an incredible accomplishment of the semiconductor industry to build these devices and chips successfully, but it is getting harder and more expensive. Consequently, AI is now being used as a tool to help with this ever-growing fabrication complexity of semiconductor R D and manufacturing. This is a synergistic virtuous cycle, where AI algorithms enabled by chips are used in turn to help with chip fabrication.System IntegrationThe next layer of the stack is the integration of individual devices into a system. Advanced packaging techniques, such as silicon or glass interposers (2.5D) for interconnecting chips, can reduce the communication distance and power consumption. These are often deployed for high-performance computing systems running AI algorithms. Beyond this, the industry is actively exploring 3D systems that are even more compact, both as multi-die 3D packages and as monolithic 3D chips.The concept of chiplets – smaller chips with specialized functions that can be assembled flexibly to optimize system performance – holds much promise. Industry consortia are developing protocols such as Universal Chiplet Interconnect ExpressTM (UCIeTM) to enable seamless integration of chiplets both in the planar and vertical dimensions. These advanced techniques pack more functional elements into increasingly compact form factors, but this proximity makes power delivery challenging and often generates intense heat. Much work is needed to ensure optimal power delivery and adequate thermal dissipation.Looking beyond traditional electronics, photonics represents an exciting opportunity. Most long-distance data communication is on fiber-optic cables and thus already photonic – bringing this to shorter distances can save energy while increasing bandwidth and performance. This requires efficient photonic-electronic integration at the packaging or even chip level, which is a major challenge requiring cross-disciplinary collaboration.Architectures and AlgorithmsAI algorithms need enormous amounts of data processing compared to traditional computing workloads. This requirement stretches (or breaks) the limits of traditional Von Neumann architecture, which requires frequent data movement between memory and processor elements for each computation cycle. Much of current architecture innovation focuses on bringing processor and memory elements closer to each other. System integration is already driving “compute-near-memory” architectures like high bandwidth memory (HBM). Other forward-looking implementations combine them into a single chip, known as compute-in-memory (CIM). Memory elements being explored for this purpose include resistive RAM (RRAM), phase-change memory (PCM), ferroelectric RAM (FeRAM) and magnetic RAM (MRAM). However, there is no one “perfect” memory – each has pros and cons in terms of latency, capacity, bandwidth, power consumed per operation, manufacturability, etc. Other researchers are also exploring devices like memristors for analog computing, which can improve energy efficiency for certain workloads.Finally, hardware-software co-optimization is crucial. Algorithms mismatched with the underlying system are energy expensive; conversely, co-optimized systems are highly efficient. While conceptually obvious, this is difficult in practice because development cycles are quite different – software algorithms can transform in a few months, while new hardware often takes years to develop. While some strategies can be used for mitigation – such as designing in redundancy/flexibility or making the hardware application-specific – much work remains to solve this conundrum.Pre-competitive Collaboration to Find SolutionsAll speakers emphasized that pre-competitive collaboration across the entire stack is critical, as these challenges are formidable and cannot be solved by one entity or in isolated silos. SEMI is a global and neutral organization with over 3,000 member companies, and is well-positioned to provide a pre-competitive collaboration platform to connect the dots across silos. In fact, SEMI’s mantra is “Connect, Collaborate, Innovate” – reinforcing its commitment to advancing the entire industry. For this purpose, SEMI’s Smart Data-AI Initiative continues to drive robust discussions on this topic – next there will be a roundtable discussion during SEMICON Southeast Asia, May 20-22 in Singapore, followed by a focused technology session at SEMICON West 2025, October 7-9 in Phoenix, Arizona. The overall objective is to move from “talking-the-talk” to “walking-the-walk,” towards creating system-level solutions for energy-efficient AI computing. Specifically, we want to identify the pre-competitive actions that could synergize individual innovations and make the whole greater than the sum of parts. Some ideas include collaborative proof-of-concept projects, industry standards and independent benchmarking. Come join us on this journey and connect with us at [email protected]. Dr. Pushkar P. Apte is the Strategic Technology Advisor and leads the Smart Data-AI Initiative at SEMI.

The world is abuzz with the new opportunities being created by artificial intelligence (AI), enabled by availability of unprecedented amounts of data. AI runs on the semiconductor engine, and in turn, creates a rising demand for semiconductor chips. The semiconductor industry is predicted to reach $1 trillion in revenue by 2030 by McKinsey Co., in large part due to the market demand for AI and data. There are, however, formidable challenges to overcome for this virtuous cycle to continue. The SEMI Smart Data-AI Initiative, together with the SEMI Future of Computing Think Tank, is working to help the industry address these challenges. This article paints the big picture and lays the groundwork for an in-person workshop on March 19, 2025, in Silicon Valley, where pre-competitive and collaborative solutions will be explored.“To unlock the full potential of AI, innovation is required across the technology stack – from the models and software to datacenter architecture, chip design and how those chips are made. Advancements in foundational semiconductor technologies will have a dramatic impact on system-level energy and cost reduction in the AI datacenter.” – Gary Dickerson, President and CEO of Applied MaterialsThe Performance ChallengeInvestment in AI system infrastructure is rising at a dizzying pace, with hundreds of billions of dollars being committed by individual companies as well as public-private partnerships around the world. AI models built on larger data sets generally deliver better results, so model sizes are growing exponentially each year, with leading-edge models requiring billions and even trillions of parameters. This is especially true with the rapid growth of the Large Language Models (LLMs) used for Generative AI. Can the foundational semiconductor technology keep up? Even if semiconductor chips were following the famous Moore’s Law, performance would only double every 2 years. The real pace of performance improvement is even slower, as leading-edge technologies are reaching physical limits of materials – with the tiniest patterned dimensions on chips now approaching the fundamental atomic separation distance. While semiconductor designers and process technologists continue to innovate with new materials, devices, 3-dimensional stacking and so forth, there remains a formidable challenge for silicon chips and hardware systems to keep up with the growth rate of AI models and data sets. The Energy ChallengeProcessing ever-larger data sets and AI models also requires increasing energy. A recent report by the US Department of Energy indicates that data center energy consumption tripled over the past decade and may triple again in just 5 years! Other analyses show that a single data center powered by 20,000 GPUs can consume almost 40,000 KW, which is enough to power 31,000 homes in the US! Consequently, it is challenging for data centers to meet their power needs through public utilities, and several hyper scalers are investing in nuclear power. This acceleration in AI energy demand is further exacerbated because silicon technology evolution no longer follows power scaling with “Dennard’s Law,” which states that power density remains constant as technology scales to tinier dimensions. In fact, energy consumption of silicon devices has been increasing with technology scaling for the last decade. These combined factors give rise to the second formidable challenge – energy consumption is rising unsustainably for AI systems.Exploring SolutionsAddressing these challenges requires innovation from algorithms and architecture to foundational silicon technologies. The following are illustrative examples (not comprehensive) spanning the entire AI system stack.At the software and algorithm level, innovators are finding ways to reduce model size and to use hardware more efficiently. For example, IBM’s Granite models are smaller in size, with less than a billion parameters. Similarly, Google's Gemma platform offers small language models (SLMs). The recent market disruption from the publication of the DeepSeek reasoning model suggests that relatively smaller domain-specific reasoning models may offer significant efficiencies. At the architectural level, multiple paths are being explored. Special-purpose (or domain-specific) processing elements can deliver improved performance at equal or lower power for specific tasks. Examples include Cerebras’ wafer-scale designs with optimized AI accelerators and Mueon’s system-scale integration solutions. Another innovation path focuses on bringing computing closer to the memory elements, where the data resides. This addresses the major bottleneck between processors and memory in the traditional Von Neumann architecture, which has been the mainstay of the industry since inception. In-memory or near-memory computing, such as memory-focused architectures from Micron or processor-in-memory (PIM) solutions from SK hynix, offer higher performance with lower energy consumption for certain workloads. In parallel, leading CPU and GPU makers like AMD, Intel, and NVIDIA continue to innovate with power-efficient solutions. And “Edge Intelligence” innovations – for example, internet-of-things (IoT) solutions from Arm and Qualcomm – help reduce the processing and power load on data centers by executing more operations on edge devices.Critical enabling technologies also contribute significantly. Advanced packaging, for example ASE’s heterogeneous integration solutions, enable efficient, high-performance computing by integrating multiple diverse components optimally. Another emerging development is the advent of “chiplets,” which split the chip into smaller parts, and enable special-purpose accelerator building blocks to be assembled with more general processor, memory, and interconnect elements. A well-developed chiplet ecosystem could provide silicon designers with more degrees of freedom to design optimized systems. Looking beyond electronics, the integration of photonics can enable low-power, high-bandwidth connectivity – for example, LightMatter’s silicon photonics interconnects and Ciena’s data center interconnects.Materials and devices form the foundation of the technology stack. Example technology innovations include Stanford University-led N3XT, a 3D solution that integrates multiple novel devices and materials including resistive and spin-torque transfer RAMs, carbon nanotubes and 2D materials. Similarly, a University of California-led effort synthesizes low-dimensional nanostructures, sensors, detectors and photonics in an integrated solution. Finally, advanced and innovative processes and equipment are being developed – for example, by Applied Materials and Lam Research – to fabricate these novel materials and devices.All these individual innovations are amazing and necessary, but are they sufficient? What if we could collaborate across the entire system and co-optimize hardware and software innovations synergistically? Could the integrated whole be greater than the sum of parts? What efficiencies could we unleash? And what business opportunities would this unlock?The SEMI Future of Computing workshop on March 19, 2025, seeks to answer these questions by uniting AI innovation leaders from industry, academia and start-ups, including most of the companies and universities mentioned in this article. We will begin building pre-competitive collaboration that breaks through silos and explores system-level solutions – with the ultimate objective of radically improving the energy-efficiency of computing for AI.Pushkar Apte is the Strategic Technology Advisor and leads the Smart Data-AI Initiative at SEMI.Jim Sexton is a Fellow at IBM.Melissa Grupen-Shemansky is CTO and VP of Technology Communities at SEMI.

SEMI spoke with Christian Driller, Vice President of Research and Development at Comet Yxlon, about opportunities to accelerate time-to-market and increase yield for advanced packaging manufacturers through x-ray inspection.

AEM Holdings Ltd, a Singapore-based multinational corporation, is listed in Forbes Asia’s 200 Best Under A Billion 2019 and 2020 spotlighting small and midsized companies in the Asia-Pacific region with sales under $1 billion. AEM clinched the Singapore Business Review Technology Excellence Award 2020 for Analytics-Semiconductor and the Singapore Business Awards Enterprise Award 2019/2020. These achievements are testament to AEM’s vision and innovation and the company’s contributions to the increasingly complex testing of chips in a rapidly evolving technological world. I spoke with AEM CEO Chandran Nair, a new Regional Advisory Board (RAB) member of SEMI Southeast Asia, about the company’s intelligent test and handling solutions, its role in digital transformation, the company’s key role in the smart manufacturing movement and the growth prospects for Singapore’s electronics sector. SEMI: AEM’s application-specific, intelligent system test and handling solutions for semiconductor and electronics companies serve the advanced computing, 5G and AI markets. How do you differentiate your solutions from those offered by competitors? Nair: A key differentiation for AEM is that we work closely with our customers to develop application-specific integrated test and handling solutions that meet their needs in a scalable manner from lab to production. We offer our customers customized, full-stack test and handling solutions that give them the agility to accelerate their delivery cycles and enhance product quality. Over the years, AEM has developed and acquired world-class technologies in instrumentation, test, automation, robotics, optical inspection, high-end thermal control, and software. These technology pillars, along with our deep know-how to customize test and handling solutions using the technology pillars as a platform, enable AEM to meet the fast-changing needs of our customers faced with the challenges of testing heterogeneous and complex devices. In addition to investing in technology, AEM has also invested in delivering application-specific solutions to meet customer demand. Our recently announced acquisition of CEI with its manufacturing capabilities in Vietnam and its specialization in low-volume, high-mix manufacturing increases our geographical reach and our ability to quickly turn application-specific test and handling solutions to be deployed. We have a unique and differentiated approach that enables our customers to test high-performance computing devices, automotive devices, and mobility devices with maximum test coverage, cost-effectively, in a manufacturing environment. Our experience in serving the high-performance computing market that traditionally drives advancements in thermal control also puts us at the forefront of delivering comprehensive thermal management, vision, and deep automation and test solutions for the computing, automotive, and mobility markets. AEM also has a strong instrumentation portfolio, including high-density digital instruments and mixed-signal and protocol-aware instrumentation that is well-suited for ATE solutions for SoC, high-power devices, and CMOS image sensors. Over the last few years, we have also established leadership positions in developing and deploying application-specific test solutions for MEMS devices and offering wafer and frame probing stations suitable for R D, wafer sort, and final test. We form strong partnerships with our customers, provide them with end-to-end support in product development, and take them through the entire life cycle process from concept to mass production. Chandran Nair and Goh Meng Klang, vice president of operations, at the AEM manufacturing site in Singapore. (Photo credit: AEM) SEMI: Digital transformation is powering strong growth of advanced computing, 5G and AI. Will AEM be expanding its AEM manufacturing plants in China, Malaysia and Singapore to meet rising demand for these technologies in the coming years? Nair: In regards to manufacturing, AEM currently has manufacturing facilities in Singapore, Malaysia, the U.S., Finland, and China. With our recently announced acquisition of CEI, we will add manufacturing capability in Vietnam and Indonesia. AEM will continue to expand manufacturing appropriately to give our customers cost-effective solutions while maintaining our proven track record of delivering on time and scaling rapidly in times of crises like the pandemic or geopolitical disruptions. As for advanced technologies, the three key factors that will bring the full potential of 5G to fruition are 1) cost-effective, high-powered processing devices at the edge, 2) easy access to high-bandwidth communications, and 3) cost-effective sensor technology. Semiconductors are the primary drivers of these three key success factors. As devices become more complex and our reliance on semiconductor-powered devices in all aspects of our lives deepens exponentially to include mission-critical applications, AEM’s role is to ensure that our customers' electronic and semiconductor devices are shipped thoroughly tested, safe to use, and highly reliable. It is imperative that, as a testing company, we find innovative ways to help our customers test their products with maximum coverage and minimum cost. To do this, we are focusing our R D efforts and investments to continue building on our key technology pillars to ensure that we stay ahead of the curve when it comes to test and handling solutions. We prepare our customers to test increasingly complex devices manufactured on the latest process node. SEMI: During your career you’ve driven projects in test and automation and more recently robotics solutions for ports, logistics warehouses and transport. With robotics and automation a key part of Industry 4.0, what role do AEM solutions play in powering the smart manufacturing movement? Nair: The smart manufacturing movement is powered by semiconductors, software and increasingly by artificial intelligence (AI). Test is at the heart of the process of ensuring that semiconductor and electronics devices reach the consumer well-tested for reliability. With our vision of enabling A Zero Failure World, AEM addresses the necessity for safe, highly reliable devices. The semiconductor companies themselves are adopting smart manufacturing methods. AEM’s tools are Industry 4.0-ready, and we continue to invest in machine learning and data analytics, which are integral to the future of test. Our tools are automated and feature embedded sensors to provide our customers with data about tool usage, the state of a machine’s health, and more. Our tools are connected to our customers’ manufacturing automation platforms. Additionally, we continue to invest in our ability to better slice and dice test data to understand trends and patterns to help our customers analyze data and make decisions faster. SEMI: You also have experience heading autonomous vehicle projects. With the COVID-19 pandemic hastening digital transformation, do you see an acceleration in the development of fully autonomous vehicles and smart manufacturing? Research and development efforts for autonomous vehicles (AV) continue at a fast pace worldwide. With shutdowns and restricted movement rules globally, the pandemic has hastened digital transformation in many ways. The delivery of goods and services is transforming, and AV will surely play a part, especially in secure environments for autonomous transport. The pandemic has accelerated the development of autonomous vehicles and smart manufacturing technology in automation-friendly environments like factories and ports. SEMI: At the recent Global Technology Summit hosted by SEMI, you spoke about testing innovations to meet the demands of highly complex devices. Please elaborate on innovative testing solutions versus traditional testing? Nair: AEM offers a disruptive and differentiated solution, one that is driving a paradigm shift to asynchronous, modular, highly parallel, smart testing solutions. ​ The traditional approach of ATEs to test increasingly complex devices on advanced nodes has reached a point of diminishing returns as it gets exponentially more expensive to increase test coverage to acceptable levels. Additionally, as devices get more complex and companies are rapidly adopting heterogeneous packaging technologies, the realization that System Level Test (SLT) is necessary is forcing a rethink of the entire test process. AEM’s provides asynchronous, modular, highly parallel test cell solutions that enable each test cell to run SLT, final test, or burn-in all in one system and its ability to handle hundreds of test cells independently with each test cell testing multiple devices. Our solutions suddenly make comprehensive testing of every complex device cost-effective. Freeing us from legacy ATE allows AEM to provide these innovative solutions to our customers. AEM engineering and manufacturing teams in Singapore at work on semiconductor test and handling systems for global deployment at world-class semiconductor facilities. (Photo credit: AEM) SEMI: Singapore seems to be in the sweet spot of digital transformation. Singapore’s industrial production grew 8.6% year-over-year in January 2021, an expansion driven mainly by a surge in sectors including electronics, and more growth is seen in the year ahead. Digital technologies such as 5G technology and cloud computing together with continued demand for work-from-home equipment is behind this growth. What are the growth prospects for the region’s electronics sector? Nair: Singapore is well-poised to benefit from the current digital transformation accelerated by the adoption of these technologies during the pandemic. Being a safe, well-governed country with strong IP protection, excellent infrastructure, and the rule of law, Singapore is in a great position to play a central role in cloud-based services, 5G, and the semiconductor industry. Singapore’s semiconductor sector output is at a record high, and the prospects for renewed growth in the region are very good. SEMI: As a new Regional Advisory Board member of SEMI Southeast Asia, how is your industry experience relevant to the scope of this role? What opportunities lie ahead for the region? Nair: I am honored to represent AEM in the SEMI’s Southeast Asia RAB. The SEMI RAB can influence policymakers with ideas and information on the current and future needs of the industry. I also believe that SEMI Southeast Asia can cultivate a strong innovative semiconductor ecosystem that helps regional and global growth. I look forward to working with other very experienced and accomplished board members. Bee Bee Ng is president of SEMI Southeast Asia.

SEMI met with Gerald Beyer, program manager at imec, to discuss the co-existence of various 3D interconnect technologies and their need for new materials and integration solutions. The two talked in the runup to his presentation at the Advanced Packaging Conference at SEMICON Europa 2018, 13-16, November 2018, in Munich, Germany. To register for the event, click here. SEMI: Can you confirm this trend towards heterogeneous integration and do you think it will be a long-term development trend?Beyer: We consider heterogeneous integration as a scaling booster for functional partitioning and as a fashion method to create systems, which would not be possible or economical on such as a single chip. As you can apply it to numerous systems, we expect it to stay for the long term.SEMI: What are the new critical challenges for the combination of different technologies into one package?Beyer: When you create a complex system, there is usually more than just one challenge. On one side, you need to be able to design such a system. If you disintegrate a large chip, you need to decide how to reconstruct it, i.e. which function goes into which strata. You would like to do that not manually but with a set of tools supporting the designer. Only recently EDA (Electronic Design Automation) and design houses have started to support this idea.On the technology side, interconnections between some strata of such a reconstructed chip will require small pitch interconnects of the order of 1µm pitch and less. Today, wafer-to-wafer bonding technologies have sufficient overlay margins for 1µm pitch. Wafer-to-wafer bonding technologies, however, have a number of constraints such as equal die size and the necessity to realize chip stacking rather in a fab environment than in a traditional packaging house. Die-to-wafer assembly technologies still need to bridge the gap to deep sub 10µm pitch in terms of alignment and cleanliness.SEMI: What kind of new materials or integration solutions do you expect to be developed? Are you working on it already?Beyer: As explained above, die partitioning requires sub 1µm pitch interconnects. We are investigating fine pitch wafer-to-wafer and die-to-wafer (direct) bonding. For the latter, not only new alignment capabilities but also die cleaning and thin die handling technologies need to be developed. To build a complete system with data processing, memories etc., novel integration schemes such as Flip Chip – Fan Out Wafer Level Packaging with high density 2D and 3D interconnect capabilities are being investigated. These new systems differentiate from current ones by high density Through Package Vias (TPV), Si bridges and sub 2µm line/spacing RDL. The new integration approaches push the materials such Temporary Bond Materials (TBM), Wafer Level UnderFill’s (WLUF), photo patternable polymers for fine Line/Spacings to name a few, to the limits. Hence, development of new materials is a key aspect.SEMI: What trends and developments do you expect in the near future and why would you recommend attending the Advanced Packaging Conference?Beyer: The development and commercialization of products using heterogeneous integration is a big effort drawing on resources from EDA vendors, materials and packaging tool suppliers, OSATs, foundries, memory suppliers and IEDMs and academia alike. The agenda of the Advanced Packaging Conference at SEMICON Europa reflects this diversity and I am looking forward to interesting discussions with all participants. Gerald Beyer has been working in the field of 3D Technologies since 2012 as the technology program manager of the 3D System Integration Program of imec. Prior to this role, he was the interconnect program manager and group leader of BEOL integration. He received a PhD in materials science from Imperial College, London and a MSc from Thames Polytechnic, London.Serena Brischetto is a marketing and communications manager at SEMI Europe.

The Japan semiconductor manufacturing supply chain is a global semiconductor industry workhorse, producing about one third of world’s chip equipment and more than half of its semiconductor materials. In contributing the vast majority of these products, SEMI Japan member companies hold the high distinction of enabling continuous development of the worldwide semiconductor industry. Aptly, then, technology powerhouses IBM, Nissan Motors and Toshiba offered insights into the latest trends and innovations in computing and smart cars at the late-May SEMI Japan Members Days in Tokyo with 133 technologists from member companies in attendance. As the audience discovered, chip innovation never sleeps and, as futuristic as it can be, invariably gives rise to possibilities beyond the human imagination. That was the message of kickoff presentation “Computing Reimagined – AI/Quantum/IoT” – by Dr. Shintaro Yamamichi, Senior Manager, Science Technology at IBM Research-Tokyo. Dr. Yamamichi cited three examples of how semiconductors uncover new technology frontiers. Computational materials discovery, a novel methodology, is the application of theory and computation to unearthing new materials and the key to enabling an ongoing stream of semiconductor innovation. In particular, using cognitive technology to mine huge volumes of literature reveal new insights into materials that uncover even more functionality such as greater conductivity and heat resistance. With new materials the oxygen of ever more advanced semiconductor chip manufacturing, the semiconductor industry will surely benefit from this methodology. The opportunity to accelerate quantum computing innovation is now. Launched in May 2016, the IBM Quantum Experience gives students, researchers and general science enthusiasts hands-on access to IBM’s experimental cloud-enabled quantum computing platform. The online platform features a forum for discussing quantum computing topics, tutorials on how to program IBM Q devices, and other educational material about quantum computing. Dr. Yamamichi encouraged the audience to join the program. The world’s tiniest computer, unveiled by IBM at the company’s Think 2018 conference in Las Vegas, packs several hundred thousand transistors and, IBM claims, the equivalent power of a 1990s x86 chip into a package smaller than a grain of salt. The computer’s small form factor (less than 1mm x 1mm) and low manufacturing cost means it can be embedded in product price tags and packages as an anti-fraud device using blockchain technology. Vehicles need to be both electric and intelligent as countries become more populous and traffic density increases. More drivers extend average drive time, boost greenhouse emissions, devour precious energy resources and lead to more traffic congestion and accidents. Dr. Haruyoshi Kumura, fellow at Nissan Motor, highlighted these issues in stressing the importance of a new era of intelligent mobility. To mitigate these problems, Nissan is focusing on the electrification and intelligence of its vehicles: Nissan’s electric vehicle, Leaf, reduces accidents with electric intelligence systems such as e-Pedal, which uses an accelerator pedal only for both acceleration and deceleration, and ProPILOT Park, a feature that automatically parks the car by using multiple cameras and ultrasonic sonars to detect pedestrians and other objects around the vehicle. With more than 90 percent of traffic accidents caused by driver error, Nissan plans to introduce autonomous driving on multi-lane highways by the end of 2018 and on city streets by 2020. By 2022, the company plans to roll out full autonomous driving to reduce traffic accidents caused by inattentive drivers. For full autonomous driving to materialize, sensor fusion technology must incorporate a combination of technologies – radar systems, light detection and ranging (LiDAR) systems and cameras – to identify the shapes and locations of nearby moving objects and measure their speed. Sensed information is then processed by a 3D graphic analyzer to make electric throttle, braking and steering decisions. The outlook for automotive industry includes car sharing and more electrification – both insights from Yoshiki Hayakashi, general manager, automotive solution strategic planning division at Toshiba Electronic Devices Storage, who offered his perspectives on trends in Japan’s automotive industry and beyond. To meet the requirements of the COP21 Paris agreement, the global automotive industry is shifting to electrification. Toshiba estimates 60 percent of new cars will be electric vehicles by 2040 to meet the International Energy Agency’s global EV outlook. In Japan, autonomous driving or advanced driver assistance systems (ADAS) will be offered in certain areas by 2020, the year of the Tokyo Olympic games. Growth of these advanced driving systems hinges on infrastructure development. Supporting data centers, intelligent transport systems, vehicle-to-everything connections, and smart city are all necessary components. Car ownership will begin to cede ground to car sharing with technology elites such as Tesla, Apple and Google leading the way. To expand the car-sharing industry, new alliances will take shape between new and old-guard automotive companies and electronics manufacturing services (EMS) providers. Autonomous driving requires precise 3D renderings of actual roadways using sensors for route mapping. While sensor fusion must be deployed for these capabilities, LiDAR offers better sensing range and space resolution precision than ultrasonic sonars, radars, and cameras. The next SEMI Japan members day is scheduled for October 30 in Tokyo. SEMI holds similar events in most regions where SEMI and its members operate. For the members events in your region, contact the SEMI office nearest you. Yoichiro Ando is a marketing director in SEMI Japan.