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TEL/NEXX

The arrival of Fan-Out Panel Level Packaging (FO-PLP) appears to be at a perfect time: This technology will leverage processes developed for Three Dimensional Stacked Integrated Circuits (3DS-IC) as well as panel processing technologies developed for industries such as solar panels and large-screen TVs. In this combination, FO-PLP promised the improved performance of 3DS-IC, without the expense. There was just one problem…That problem is the size of the panels to be processed. As different companies developed FO-PLP processes, they chose panels sized to meet certain technical or business goals, or chose a size based on familiarity. So, processes were being developed for more than ten sizes, each of which had one or more companies championing them. For people in the wider semiconductor industry, the development of many processes, each with a unique panel size brought a feeling of déjà vu, reminding them of the 1970s, when each device manufacturer created their own specification for wafer size, forcing them to manufacture their own wafer processing equipment since no external manufacturer was willing to produce tools usable only by a single customer.SEMI responded by developing an industry consensus silicon wafer standard – which described basic parameters, including diameter and thickness – to resolve the issue. Almost overnight the landscape changed, and new tool manufacturers sprung up, enabling the incredible growth that has persisted over more than 40 years.Recently, Cristina Chu (TEL NEXX) presented the state of FO-PLP to the North America Chapter of the SEMI Three-Dimensional Packaging and Integration (3DP I) Technical Committee, suggesting that the Committee develop a single standard dimension that would enable the technology to move into high-volume manufacturing.The Committee began by surveying the industry to determine the interest level in such a standard as well as its contents. A key finding came in response to the question “Would you support a standardized panel size?” Overwhelmingly, over 70 percent of the respondents supporting the idea for the standard, with less than 2 percent opposed. The survey also asked if other parameters should be standardized and, if so, which parameters. Majority responses pointed to edge profile, flatness, and warp, prompting the 3DP I Committee to immediately form the FO-PLP Panel Task Force (TF) to develop such a standard. Chu and Richard Allen (NIST) agreed to chair the TF and respondents to the survey were asked to participate as TF members.The TF initially decided to follow the model of SEMI M1, Specification for Polished Single Crystal Silicon Wafers, and write the document as a purchase specification. The purchase specification would indicate a limited number of mandatory parameters, identified as those that serve as bottlenecks to the development of a FO-PLP ecosystem. Parameters that were not perceived as bottlenecks but might be useful for implementing a FO-PLP process would be included as optional.Working under the SEMI Standards umbrella allowed the TF to take advantage of work done in the development of other standards, without having to recreate it from scratch. In particular, Flatness and Shape were repurposed from SEMI M1, ensuring consistent definitions of these parameters.The TF could not come to consensus on how the other parameters should be categorized, so the decision was made to move the ordering table to a new Appendix as optional.The TF will be balloting its first specification for panel substrate in the upcoming cycle, which opens September 5, 2018 (Cycle 7). The voting is open to all industry experts. Based on the feedback, the task force will continue to refine and otherwise improve the specification by incorporating other parameters that are critical to making FO-PLP a reality.SEMI Standards development activities take place throughout the year in all major manufacturing regions. To get involved, join the SEMI International Standards Program at: www.semi.org/standardsmembership.For more information regarding FO-PLP Panel Task Force activities, please contact Laura Nguyen at [email protected] Allen is a physicist in the Nanoscale Metrology Group in the Engineering Physics Division of the Physical Measurement Laboratory (PML) at the National Institute of Standards and Technology (NIST).
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New metrology and inspection technologies and new analysis approaches made possible by improving compute technology offer solutions to finding the increasingly subtle variations in materials and subsystems that meet specifications but still cause defects on the wafer. More collaboration across the supply chain is helping too. SEMICON West programs on materials and subsystems will address these issues. New metrology approaches needed to deal with process margin challenges As device process margins shrink and subtler materials variations cause unwanted deviations, the need for better monitoring of both surface and sub-surface material variations is driving a trend towards “metro-spection” – the convergence of metrology and inspection. “Device process margins have eroded to the point that traditional metrology strategies and techniques are no longer viable for controlling yield and parametric performance,” says Nanometrics Vice President Robert Fiordalice, who will speak in the materials program at SEMICON West. “Limited sampling capability, low throughput, insufficient sensitivity or the destructive nature of the techniques can often become problems. What’s more, deviations in material characteristics are not always determined by the initial quality of the material, but often arise from variations during the integration of the materials.” One new type of inline tool or line monitoring technology is Fourier Transform Infrared (FTIR) spectroscopy, traditionally used in quality control or tool characterization. Better sensitivity and higher throughput now enable rapid analysis and feedback for on-the-fly detection of subtle deviations in film properties that may compromise device performance or yield. More advanced analytics will help extract new information from old metrologyMore expensive metrology may not be required to identify subtle variations in in-spec materials that cause wafer defects. Today’s advanced compute capabilities now enable more sophisticated analysis of existing data and the identification of small but significant variations in raw materials and finished goods. The figure of merit (FoM) values presented in certificate of analysis (CoA) reports miss subtle variations in raw material properties. Of particular note is the reduction of molecular weight distributions to a mean, and standard deviation, whereas variations in the tails are associated with pattern defects. Advanced compute capabilities now allow the industry to step beyond the FoM in favor of more holistic measures, enabling predictive analysis of resist chemical variations associated with specific pattern defects. Source: JSR Micro“We often don’t need to find a new measure, but just a new way of looking at what we measure now,” says Jim Mulready, vice president of global quality assurance at JSR Micro. Mulready will speak in the SEMICON West program on materials defectivity issues. “The certificate of analysis reduces multiple measurements to a single figure of merit. But if we ignore all that raw data, we miss a chance to learn. One of our sayings in quality is ‘Customers don’t feel the average, they feel the variation.’ In many electronic materials, the quality of the raw material can have a big impact on the final performance, but the types of analysis needed to look at the tails of the distribution of these measures (such as molecular weight) in detail used to be really hard to do. Now it’s becoming increasingly straightforward and affordable.” Mulready says tools now available in the data processing sector enable the identification of subtle variations in materials that can cause defects on the wafer. These tools use methods like detailed subtractions of chromatography curves of polymer raw materials or analysis of tails of distributions of molecular weights. “Our job now is to drive these kinds of more sophisticated data analysis back into our chemical supply chain as well,” says Mulready. “We must work more closely with our suppliers to integrate their raw materials into our products. The reason the JSRs of the world exist is as a safety valve to reduce the variation from the chemical industry before it gets to the fab.”Continued collaboration with equipment suppliers required While the industry has been talking about the need for tighter collaboration between materials suppliers and equipment manufacturers for years, it still doesn’t always happen. “The material supplier and the equipment maker are tied together like kids in a three-legged race when we deliver an integrated system for consistent on-wafer performance,” says Cristina Chu, TEL/NEXX director of strategic business development, another speaker in the materials program. “When we introduce changes to the tool hardware, we need to make sure it doesn’t upset the system. Similarly, we need the material supplier to send a bottle over when a new chemistry formulation is under development. If a new chemistry runs into problems in the field, it will take much more time for both of us to fix it at the customer site. The toolmaker can provide a slightly different perspective on applications, while being more objective than a customer on how the formulation performs compared to earlier versions.”Regular and ongoing collaboration between chemistry suppliers and toolmakers enables the highest quality system solution to reach the customer. Chu notes that her team tries to maintain consistent collaborations with material suppliers across changes in organizations as the business environment changes. “For consistent on-wafer capabilities, we need a consistent collaboration process with chemistry suppliers. We need to meet with materials providers at a regular cadence throughout their development process. We need to check back with them as we scale up results from the coupon to the wafer level and to work out the kinks in the integrated solution together. The quality and consistency of our combined performance at the customer depends on ensuring the quality and consistency of our development and evaluation process as well.”Fabs and subsystems suppliers look to pilot data sharing program to improve process margins With ever tighter process margins, subtle variations in parameters that don’t appear in the specifications are also compromising results on the wafer, and neither the fab nor the supplier alone has the full information needed to improve performance. To help, a SEMI standards group is developing a protocol for a pilot program to standardize and automate some data sharing.The fab knows that performance is best with a particular parameter value, and knows when performance fluctuates, but often faces a black box problem with no way of knowing what exactly is wrong. In the rush to get the tool back up, the fab engineers may not get around to emailing the supplier about the issue for some time. The subsystems supplier, on the other hand, may know the cause of the variation, but likely has no way of knowing the critical parameters or ideal target values for the fab’s process. “In order for engineers to have constructive conversations about how to improve performance, we all need to exchange more information,” says Eric Bruce, Samsung Austin diffusion engineer, and co-chair of the SEMI Standards initiative addressing the issue, who will speak in the subsystems program at SEMICON West. A potential solution could be to create a standard and automated process to share particular data, agreed to in the purchasing contract, whereby the subsystems supplier shares more information about their parameters with the fab, and the fab in return gives feedback on what parameters work best to drive improved performance. The best place to start will likely be on parts that do not contain core yield-related IP, but where usage and lifetime information is useful.“We’re looking for people to participate in a pilot program to work together with suppliers to try sharing some information to improve performance,” says Bruce. “There’s a lot of this sharing in the backroom anyway, but this could make it fast and automated, and make everyone’s engineering job a lot easier.”Paula Doe, SEMI
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