Automotive

China’s semiconductor sector has exploded to become one of the largest in the world and match the region’s prominence as the biggest consumer of chips. From 2015 to 2020 alone, revenue of China’s integrated circuit (IC) industry expanded at a rapid clip of 20% CAGR (RMB) to $128 billion.

Despite the pandemic lock-down, demand for electronic products and services remains strong. Work-from-home, video conferencing, and remote learning are driving data center growth and laptop and tablet demand. 5G infrastructure rollout is underway and smartphone sales are returning to normal levels. Automotive sales are increasing. At the same time, the industry is experiencing acute shortages of substrates. The October 2020 fire at Unimicron’s IC package substrate plant in Taiwan exposed the serious nature of the capacity shortage for IC package substrates. Substrate makers have been reluctant to make large investments in capacity over the last few years due to the fear that demand could decline and they would have excess capacity. Relentless price pressures by customers and the resulting low margins have weakened the finances of substrate suppliers. With tight capacity, substrate prices have increased and lead times are 14 weeks or more. The most critical shortage is for flip chip ball grid array (FC-BGA) substrates. In addition to increased demand in units, applications such as servers and networking products are seeing requirements for larger body sizes and increased layer counts. Shortages will not improve very soon because it takes time to build a new plant. And equip it. Key equipment for substrate production has lead times of up to a year. SEMI and TechSearch International detailed the substrate makers and provide projections for the substrate market, trends, and a list of suppliers and their plant locations in the Global Semiconductor Packaging Materials Outlook report. The report also highlights the market and suppliers for leadframes, bonding wire, encapsulation materials, underfill, die attach, solder balls, wafer level package dielectrics, and wafer-level plating chemicals. In times of shortages the report is an important indicator of suppliers in the industry and trends. Jan Vardaman is President at TechSearch International Inc.

Call it a wild guess, but I suspect I am not the only follower of the automotive industry who is tired of reading articles that lament the impact of Covid-19 and speculate, to varying degrees of accuracy, what kind of recovery is in store for major automotive markets around the world.I’m much more interested in what solutions and creative approaches people, companies, and countries have come up with to make cars smarter and safer despite the pandemic or even because of it.A friend of mine who works at a major European vehicle OEM told me that “innovation cannot, must not stop – despite current difficulties.” This sentiment echoes through the automotive supply chain, particularly in the resilience of the semiconductor industry during these challenging times.The recent publication of the AspenCore Guide to Sensors in Automotive – Making Cars See and Think Ahead is a refreshingly positive and inspiring collection of articles, interviews, technology deep dives and business news, all carefully curated and edited by AspenCore Global Editor-in-Chief Junko Yoshida.One article I particularly enjoyed was her “6 Trends on ‘Perception’ for ADAS/AV.” The insights she was able to gather from experts attending the AutoSens show in Brussels are fascinating, even if consensus on what, exactly, will be the winning “robust perception” solution appears to be far off. This is only fitting with so many companies elbowing for that prime spot!Another feature article that stood out was Nitin Dahad’s “Level 5 AVs Unlikely Before 2035” article. It wasn’t so much the longer ramp to full autonomy that caught my eye but the daunting challenge the automotive industry and AVs have to tackle: “…all possible unusual driving situations under all driving conditions and in all environments.” This is truly a mind-boggling undertaking. The author argues that the road to Level 5 “is likely to be paved gradually, as more advanced driver-assistance features come to market.” Sounds reasonable.Both these articles point to the need for collaboration across the automotive electronics supply chain in order to not only sustain the pace of innovation, but accelerate it, as we face our current challenges. This made me think about the SEMI Smart Mobility initiative and how the great minds supporting it might be able to help. The initiative is designed to bring together automotive OEMs, Tier 1s, device makers, design houses, equipment and materials companies as well as R D institutes to address shared challenges and opportunities.SEMI used to stand for Semiconductor Equipment and Materials International, but over the past several years – and driven by the advent of IoT, AI, and everything “smart” – we now represent the entire electronics manufacturing and design ecosystem, with more than 2,400 member companies on our global roster. We created the Smart Mobility initiative in late 2017 with the initial goal of connecting a substantial number of members to new business opportunities involving rapidly rising silicon content in automotive. IHS Markit projects automotive semiconductor revenue to continue to grow at a 6% CAGR to 2026.Over the past 2 ½ years, the initiative has quickly evolved into a global platform connecting the semiconductor, sensor and automotive electronics ecosystem under one roof – the Global Automotive Advisory Council or GAAC. While “silicon content” is still the operative word for many of our core members, the Council’s mission is to address opportunities and challenges that impact more than one segment of the value chain. For example, the challenge of getting to zero defects involves just about every stakeholder – from contamination control in wafer carriers to ensuring device reliability and robustness to packaging and, ultimately, system integration in the car.SEMI also encompasses a number of Technology Communities that provide deep technical expertise in support of the GAAC’s mission. Member companies in our MEMS Sensors Industry Group (MSIG) are directly engaged in and contributing to the GAAC work. GAAC Europe Chapter - Participating Companies“Sensorizing” – making things smarter through the application of sensors – has created solutions for the automotive and mobility space that bring innovation, safety, security and comfort to driver and passenger and that benefit the environment around the car.This makes the AspenCore Guide to Sensors in Automotive a great resource for our members and SEMI staff as we collaborate to accelerate the drive toward Level 5 autonomy.If you are interested in learning more about SEMI’s Smart Mobility and the GAAC, please contact Bettina Weiss, Chief of Staff and Global Smart Mobility Lead at [email protected] with permission from EE Times.

VeriSilicon provides platform-based, all-round, one-stop custom silicon services and semiconductor IP. For two years running, they’ve been the #1 Chinese IP provider and well into the Top 10 worldwide (per IPnest 2020). They’re also an FD-SOI design powerhouse. Founded in 2001, VeriSilicon first began work on FD-SOI in 2013. Now they’re headed for listing on the Shanghai STAR exchange. SOI News talked to President CEO Dr. Wayne Wei-Ming Dai about his company’s innovative business model, and opportunities for FD-SOI.SOI News (SN): You call the VeriSilicon business model “SiPaaS”, for Silicon Platform as a Service. Can you tell us what that means? Is it particularly well-suited to designs based on FD-SOI? Dr. Wayne Wei-Ming Dai (WD): We see SiPaaS as the third transformation in the semiconductor industry. If you take a minute to look at the evolution, first was the IDM model of the 1960’s and 70’s, largely based in the US and Japan and driven first by the US military, then home appliances and consumer electronics. The second transformation was the foundry model, driven heavily by the PC and cellular communication, with a geographic center heavily based in Taiwan and Korea. That solved the CAPEX challenge. Now with the IoT, we solve the OPEX – operational expenses – challenge. Although 60% of our business comes from outside China, we do see particularly good opportunities for China. With AI and AIoT, there’s a lot of custom designs. You have a new model with the chip as a system, with lots of IP – but it also is much more expensive. The VeriSilicon SiPaaS model covers everything from IP to final tape-out, delivers packaged and tested parts, and that accelerates time to market and saves money. If you consider the share of R D expenses as a percentage of chip revenue, for leading fabless companies, they can be 20-30%, and you need to have a gross margin of 50% and higher. But if your gross margin is 40% or below, you might out of business. The VeriSilicon model seeks to transform the design-heavy model, where designers use their own IP, to the next wave, which is design-lite. When you’ve got a design-lite model for A/IoT, you don’t need such a big team. This is the third transformation. You first saw this starting in a major way in Israel, where going to design-lite enabled fabless companies to move very quickly. But you still need IPs, and for those working under a traditional model, we have those. In SiPaaS, we offer IP platforms. Chip design is kind of like building a house. If you want, we can just give you the kitchen – so that’s some specific IP. But we can also give you the entire house. The IPs form the solutions. For each type of application, there are similar IPs that need to be integrated. Sets of IPs form subsystems for IoT, automotive, medical, wearables, audio, video, etc. There are no boundaries on the platforms, but each have typical elements. In this industrial transformation, and now especially for AIoT, you’ll need many more chips in many different places. We have a lot of IP that we created organically, but we also made some major acquisitions over the years. For example, 13 years ago we bought a Dallas based DSP division from LSI Logic. Our design-lite platform approach plays particularly well in FD-SOI, where designers want to maximize the advantages of the technology. Remember that much of the original IP for FD-SOI comes from ST or Samsung. When Samsung first licensed 28nm FD-SOI from ST, we got a whole set of 28nm FD-SOI IP from ST with modification rights. So we started to play with them. Then that IP went to Synopsys. We have modified, optimized and customized it for customers. And with GlobalFoundries’ 22nm FD-SOI, when the IP comes out, we're the first ones invited to test it. So we focus on those IPs. We do benchmarks on ARM and others. And we’ve designed our own IPs for RF and more. We’ve done the body biasing circuits and software control, so we support design methodologies. People often ask us to show them how good FD-SOI is. So we do a lot of benchmarking. At 28 bulk, we can do apple-to-apple comparisons. And 28 bulk or 22 FD-SOI, it’s the same team, so we can do those comparisons, so they can compare the two nodes. And we’re partnering with more 3rd party IP companies – including smaller players – providing FD-SOI IP, which is great. [bctt tweet="Our design-lite platform approach plays particularly well in #FDSOI, where designers want to maximize the advantages of the technology - @VeriSilicon CEO Wayne Dai #IoT #edgeAI #wearables" username="SOIConsortium"] SN: You have been a very vocal champion of FD-SOI. Why? WD: We’re not against FinFET – that a really big part of our business and we’re very advanced in it. We were the first to do a tape-out on Samsung’s 7nm UV FinFET test chip and are working on 5nm. While overall we tape out over 30-50 chips a year, we are foundry neutral. But we recognize that FinFETs are not for everything: there are some things that FD-SOI does much better. Integrating RF, for example – it’s not impossible but it’s not natural in FinFET. Yes, if you’ve got a big digital chip running at high speed most of time, FinFET is better. But if you’re running high speed some of time, say around 20%, especially integrating RF, FD-SOI is better. And back biasing is impossible in FinFET. In the end, we “walk on two legs”. SN: What do designers need to know about FD-SOI? WD: Body biasing can sound complicated, but the thing is, you don't play with each transistor. In theory, you can control each transistor with body bias, but in reality, you do it region by region. With body biasing, you can dynamically make different parts of the chip behave differently. This is key. Some parts are reverse biased. Some parts are forward biased. You play with this block by block, and kick it in as-needed by software after the chip comes back. So in IoT, for example, where it's very serious low power, you may want to shut down certain parts when you're not using them, while other parts always need to be on. If you choose one of our platforms, we’ve taken care of that. There may be parts you only need to bring up and run at high-speed for certain tasks. So body biasing gives you all sorts of controls. With FinFETs you can't do that, you can just play with voltage scaling. You can drive up the speed – the dynamic power – when needed with forward biasing. During that time, you're not really worrying about leakage power because when the task is done you can completely shut down those parts again. It also changes tape out. Typically designers do worst case. But you might not need to design for the worst case: you leave too much on the table. With body biasing, if you solve for typical, when the chip comes back, you can tune and make adjustments post-silicon. So you can do an aggressive tape-out, which is much more effective than starting off with a worst case. True, if you sign off worst case, your chip can always run very fast, but sometimes you don't need that. And in order to solve for worst-case, you put in a lot of buffers or whatever for timing closure, which is unnecessary effort. What's more, for different applications, the worst case can be different: some applications may need some higher speeds and sometimes less. If you solve for typical, then depending on the application you can software-tune the device. In the past, you never had that kind of thing. With body biasing in FD-SOI, you can solve for typical, so you can save a lot of area and a lot of design cycle in terms of timing closure, in terms of use of buffers. If silicon comes back, and it's missing something – say you need it to go a little faster – I’ve done body biasing, so I adjust the timing. Most times it's probably ok, it's good enough. Of course, some applications you need some combination of fast and slow, and you can leverage the body-biasing post silicon to change what's fast and what's slow on the fly. Like in wearables, power is very critical – some parts are always on, and some parts are sometimes on. For the parts that are always on, you need to reduce the leakage, and you do that with reverse body biasing. For other parts, you bring them up and you run as fast as you can for a short period of time – in this case leakage isn't as important because most of the time it's shut down. But dynamic power is important. High performance is important. For that part you need forward biasing. With different parts of the chip, you can play with different things. Before, you had to do this before tape-out, and sometimes had to do worst-case, which should never happen: you leave too much margin on the table, because after silicon you couldn’t do anything. But now with body biasing in FD-SOI, you have the capability – you don't need to do worst case – if needed you can always adjust. And for different applications in the chip, you might need a different kind of operating frequency, right? So you can create different chips from the same chip. With body biasing, you can always tune to whatever you want. If I’m short of something, I can do some body biasing bring up the speed. Now that's different from voltage scaling. You cannot dynamically achieve voltage scaling. You might have two voltages – one's high, one's low. But you cannot continuously change. In FD-SOI the same die maybe has different applications with different performance requirements, so we don't need to do worst case design. They can come up with different performance chips in the same silicon. SN: What do you see as the drivers? WD: IoT, AIoT and automotive. Also RF, mmWave and connectivity. And at the edge, where you need very low power. FinFET and FD-SOI both solve the leakage problem. But if you need sleep mode most of the time and high performance 20% of the time, it is more energy efficient to use FD-SOI. There are a lot of applications in this category. In 12nm FD-SOI, you’ll reach almost the same performance as 7nm FinFET at 14nm cost. [bctt tweet="#FinFET #FDSOI both solve the leakage problem. But if you need sleep mode most of the time and high performance 20% of the time, it is more energy efficient to use FD-SOI /@VeriSilicon CEO #edgecomputing" username="soiconsortium"] You’ve seen some stagnation of IoT at the 40/55nm process nodes because at those nodes the performance was not as good as expected. You needed two AA batteries. The value of the IoT data was not generated, collected or analyzed. What you need is AI at the edge to pre-process the raw data so you lower network capacity requirements. AI at the edge is a great opportunity for FD-SOI. SN: How do you see the role of the SOI Consortium? WD: We work with the consortium for these big forums; in particular VeriSilicon co-founded and has now co-sponsored the Shanghai FD-SOI Forum for seven years. They’re the most visible and high quality. The consortium knows the people that need to know each other. There are a lot of meetings during these events, and a lot of deals are sealed; one signature event is the river dinner cruise where “everyone is on the same boat”. ~ ~ ~ Related VeriSilicon press releases: VeriSilicon Releases Most Advanced FD-SOI Design IP Platform on GlobalFoundries 22FDX for Edge AI and IoT Applications (2019-10-24). The VeriSilicon 22FDX IP Platform includes over 30 low-power, low-leakage and high-density memory compiler IPs and various key mixed signal IPs. VeriSilicon provides a one-stop silicon design service to customers designing for AIoT with mature IPs to shorten custom design cycles and reduce their R D costs. FD-SOI Body-Bias technology allows the user to adjust device threshold even after silicon is manufactured: it can enable dynamic tuning between High-Performance and Low-Power, and enhance the design flexibility without extra cost. Advanced ATSC 3.0 Chip Launched for Mobile and Broadcast Applications (2019-01-08). The demodulator SoC was designed and developed by Saankhya Labs with ASIC turnkey design and manufacturing services from VeriSilicon, using Samsung Foundry’s state of the art 28FDS (its Fully Depleted SOI process technology), chosen for its unique low power capabilities offered by the back bias option. (See more in-depth coverage on this announcement from SOI News here.) VeriSilicon Announces Ultra Low Power BLE 5.0 RF IP based on GLOBALFOUNDRIES 22FDX FD-SOI Process for IoT Applications (2018-11-01). The IP includes a transceiver that is compliant with the BLE 5.0 specification and supports GFSK modulation and demodulation. The silicon measurement shows that the sensitivity can be tested up to -98dBm with less than 7mW power dissipation in typical conditions. It largely improves battery life for low power IoT applications. In addition, the RF transceiver saves 40% area compared to a similar implementation on 55nm bulk CMOS. Besides the RF transceiver, this IP integrates on-chip balun, TX/RX switch and 32K RC OSC driver to save the BOM. Moreover, high efficiency DC/DC and LDOs are also available for power management. “Wearable and IoT markets especially the wireless earplug market are growing rapidly, and it will surge through consumer use, hearing aids, personal care and other industrial applications.” said Dr. Wayne Dai, Founder, Chairman, President and CEO of VeriSilicon. “By taking advantage of integrated RF capabilities of FD-SOI, in particular GF’s 22FDX, our BLE 5.0 RF IP will significantly reduce the system cost and greatly boost the growth momentum of wearable products such as wireless earplugs.” GlobalFoundries and VeriSilicon to Enable Single-Chip Solution for Next-Gen IoT Networks (2017-07-13). The integrated solution leverages GF's 22FDX technology to decrease power, area, and cost for NB-IoT and LTE-M applications. VeriSilicon's Artificial Intelligence Engine Delivers Multi-Sensory Experiences in NXP's i.MX 8 Flagship Applications Processor. (2017-06-08).

In the first part of this double feature, we looked at the automotive industry’s transition toward a mobility ecosystem and the shifting business model perspective from selling vehicles to miles. At the core of these changing dynamics are four trends represented by the acronym ACES: Autonomous, Connected, Electric, and Shared mobility. Each of these trends is largely enabled by microelectronics through computer processors, sensor units, and communication architectures. Part 2 of this series explores the business opportunities at the transition from automotive to mobility, and the specific role SEMI can play as a natural bridge between the two ecosystems.Electronics and Software as Drivers for Automotive InnovationThe ACES trends represent an acceleration of the shift in automotive from the industry’s traditionally strong focus on mechanics and hardware toward electronics and software. This transition to electronics and software as drivers for automotive innovation already started in the 1970s with electronic fuel injection, anti-lock brakes, trip computers, and many other attributes that are now considered standard features. As a result, there are now hardly any automotive systems that are not computer-controlled. A vehicle without power windows and locks, electronic climate control, or MEMS-reliant airbags are basically unimaginable in many markets.As shown in the graphic[1] depicting the electronics share of total vehicle cost, the numbers paint a clear picture of the continued growth of electronics over time, with a 44% share today expected to grow to 50% by 2030. McKinsey Company estimates the automotive software and electrical/electronic (E/E) components markets combined will grow at a 7% CAGR from USD 238 billion in 2020 to US$469 billion by 2030[2].The assumption of continued and sustained growth presents a promising outlook for semiconductor and sensor content in vehicles over the next decade, which is particularly strong in the electrification space. Hybrid electric vehicles (HEVs) already contain $900 worth of semiconductor content, and battery-based electric vehicles (EVs) contain $1,000 worth of semiconductors – much higher than the average of approximately $450 of content in conventional vehicles[2]. Other business opportunities in the mid-term (3-5 years) include software, battery technology, infrastructure (charging stations, other hardware components, etc.), as well as vehicle-to-vehicle (V2V) and vehicle-to-environment (V2X) communication. These technologies also demonstrate how the industry’s business focus is expanding beyond the confinement of an individual vehicle to increasingly contemplating the evolving ecosystem around it, resulting in real mobility solutions. Image credit: Continental AG This creates significant opportunities for a large number of SEMI members in the semiconductors and sensors business by connecting them with new customers and partners in the automotive and mobility supply chains, primarily vehicle manufacturers and Tier 1 suppliers, and together realizing new business in new automotive applications such as: Autonomy, including ADAS (GPUs, LiDAR, radar, camera, accelerometers...) Connectivity (link to outside infrastructure and in-cabin devices, roadside units...) Electrification (power electronics, battery monitoring, H2 detection in fuel-cell...) Sharing (customizable vehicle interior, trackable mobility devices such as scooters...) In-cabin experience (media systems, displays, VR/AR, occupant detection...) Vehicle architecture (flex-ray, automotive ethernet, diagnostics, smart parts...) Safety and security (HW/SW firewall, parts authentication, upgradability...) In these partnerships, the vehicle manufacturers and component suppliers clearly benefit from leveraging semiconductor capabilities including: Device and system reliability/robustness/quality (“Zero Defect”), which creates opportunities for new SEMI Standards (e.g. wafer-to-device/system traceability) New design architectures for added functionality, safety and security New packaging solutions (automotive OEMs are already participating in the Heterogeneous Integration Roadmap, seeking to collaborate with device manufactures and Original Semiconductor Assembly Test (OSAT) companies to reduce costs and differentiate on automotive-grade solutions Sensors and imaging (cameras) SEMI Smart Mobility Initiative – Connecting Mobility and ElectronicsSEMI launched its Smart Mobility Initiative in 2018 based on the mandate of providing “SEMI members with access to new business opportunities and collaborative platforms in the automotive electronics supply chain.” The initiative is currently focused on synchronizing the automotive and microelectronics supply chains for automotive electronics innovation – in particular semiconductor devices, sensors, and related products manufactured for this space and sold to vehicle OEMs and Tier 1s. To facilitate closer dialogue among stakeholders from this combined ecosystem, SEMI formed the Global Automotive Advisory Council (GAAC) which now has five regional chapters and represents dozens of companies. Collectively, GAAC members discuss and act on a wide range of topics, from Silicon Carbide (SiC) standardization to new design architectures and closing the OEM requirement gap.While continuing to build on the strong automotive foundation, SEMI’s Smart Mobility Initiative is now expanding its reach and scope of activities to broader mobility themes, such as infrastructure and battery technology and Smart City, to infuse SEMI member communities and the GAAC with new stakeholders and new ideas. These are exciting times!Please contact Bettina Weiss, Chief of Staff at SEMI, at [email protected] for further information about SEMI’s Smart Mobility Initiative, the Global Automotive Advisory Council, and how SEMI can help your organization navigate electronics in the automotive industry to drive innovation in the mobility space.[1] see graphic, created with data from NXP / Freescale[2] Source: McKinsey Company, 2019Microelectronics Power the Future of Mobility – Part 1: Autonomous, Connected, Electric and SharedBettina Weiss is Chief of Staff and Global Smart Mobility Lead at SEMI. Sven Beiker is Smart Mobility Consultant at SEMI.

As the amount of electronics in automobiles continues to increase, it is becoming more common to hear a vehicle referred to as a “computer on wheels.” To that end, innovation occurs at the intersection of automotive and microelectronics so that leveraging synergies and contemplating joint initiatives becomes crucial in shaping the future of both fields. In this two-part article, we will discuss the current trends in the automotive industry, which are to a large extent driven by microelectronics, and will reflect on the transition from “just the vehicle” to “the mobility ecosystem.”SEMI encourages its members to partner in seizing opportunities in safe, efficient, and convenient mobility solutions. Before diving into specific opportunities that the automotive industry offers to electronics companies, we will start by taking a closer look at this sector and the current trends.Automotive or Mobility? Shaping the New EcosystemThe automotive industry and its supply chain of vehicle manufacturers and component suppliers has been evolving for decades around the sales of vehicles. The customer groups used to be fairly well established with individual consumers and commercial entities, the latter often as fleets. The automotive industry has grown in depth by vertically integrating design, manufacturing, sales, service, accessories, etc. More recently, the traditional players have also begun to venture into mobility services such as car sharing, showing their ambitions to become “mobility providers.”The term “mobility” has been used increasingly instead of “automotive” for about a decade now. This reflects the more recent transition to creating businesses and functionalities around the sales of miles. In line with this, the industry’s perspective is also shifting toward use-cases and experience rather than just focusing on the vehicle or plain transportation. Much of this transition from “vehicles to miles” is driven by key trends that require massive use of microelectronics, in particular autonomous driving and electric vehicles.One of the key questions to raise for SEMI members is: at which stages should the supply chains for the microelectronics and mobility industries interact with one another to shape the evolving ecosystem? In order to answer this question, we will examine the four main trends shaping the future of mobility represented in the acronym “ACES”: Autonomous, Connected, Electric, Shared.ACES – Autonomous, Connected, Electric, SharedThese four trends, together with the broader transition from “vehicle to miles,” also include newcomers “disrupting” the industry and changing it for good. Basically, every mobility player, traditional or new, is taking ACES (or CASE) into consideration at the moment.Autonomy: computers are taking over the task of driving from humans, first through advanced driver assistance systems (ADAS) and then at some point with complete self-driving. Following the levels of automation from zero to five, as defined by SAE International[1], the current market frontier is SAE Level 2, which means the vehicle can under certain situations (e.g. highway) drive itself but has to be monitored by the driver at all times. Many industry experts assume that artificial intelligence and computing power hold the key to higher levels of automation.Connectivity: vehicles are increasingly exchanging data with a central hub and with one another through cellular, WiFi, satellite, etc. At present, there are mostly entertainment and convenience offerings on the market, but maintenance and safety functionalities are emerging. One key differentiation between solutions is whether connectivity is “built-in” with embedded OEM solutions, “brought-in” (e.g. smartphone apps independent of vehicle or dashboard navigation systems), or “tethered” (e.g. smartphone used as communication gateway).Electrification: traditional mechanical and fossil-fuel-powered vehicle driveline components are increasingly being replaced by electrical components. The spectrum includes hybrid electric vehicles (HEV), plug-in HEV (PHEV), battery-based electric vehicles (EV), and hydrogen fuel-cell vehicles (FCV). The transition from traditional to electrified driveline technology requires more and more diverse electronics, such as more control systems, sensors and high-voltage systems. Ultimately though, the transition requires fewer systems, i.e. ignition, injection and multiple other systems being replaced by high-voltage power electronics and battery monitoring.Sharing: a growing number of consumers are seeking convenient access to mobility to get “from A to B” while viewing vehicle ownership as a burden rather than a benefit. Typical forms of this trend include car-sharing, ride-sharing, ride-hailing, micro-mobility, and micro-transit. Mobile computing enables much of the convenience that shared mobility offers, such as instant access, competitive and convenient payments, and flexible work opportunities (i.e. “gig economy”). Therefore, electronics, connectivity, and computing all play an important role in this trend.SEMI as the Natural Convener for Industry Exchange and ProgressClearly, for all four of the ACES trends, microelectronics play a crucial role in driving mobility innovation and making future solutions safe, efficient, and convenient. Based on this, mobility represents one of the largest opportunities for semiconductors: by 2025[2], a projected 14% of all integrated circuits produced globally will go into vehicles. As the trade association representing the complete microelectronics manufacturing and design supply chain, SEMI is positioned as a natural convener of experts for cross-industry and pre-competitive exchanges with the automotive supply chain. This positioning led to the foundation of the Smart Mobility initiative at SEMI, in part, to facilitate collaboration across these increasingly interdependent supply chains. The second part of this blog will present opportunities for electronics based on the ACES trends in the automotive industry, along with an overview of the Smart Mobility initiative.[1] © SAE International from SAE J3016™ Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles (2018-06-05), https://www.sae.org/standards/content/j3016_201806/ (retrieved 05/5/2020)[2] Source: IC InsightsMicroelectronics Power the Future of Mobility – Part 2: Opportunities for ElectronicsBettina Weiss is Chief of Staff and Global Smart Mobility Lead at SEMI. Sven Beiker is Smart Mobility Consultant at SEMI.

SOI News spoke with Philippe Berger, CEO of chip silicon IP design / power management specialist Dolphin Design. Here’s what he told us about the work they’re doing on FD-SOI.SOI News (SN): Dolphin Design has been offering IP solutions for bulk technologies since 1995. What is your specialty, and why are you expanding your offering to FD-SOI? Philippe Berger (PB): Low power is part of Dolphin’s DNA since its inception and we work hand-in-hand with our customers to offer IPs that enable design of Energy Efficient SoCs while allowing our customers to focus their design activity on their core competencies. Technology scaling is no longer the only answer for the next generation of Energy Efficient SoCs. FD-SOI is one of the attractive technologies to address the upcoming energy efficiency challenges of next SoC generations, be it for IoT or automotive among several other applications. FD-SOI offers the opportunity to deal with a complex SoC architecture, made of multiple power domains, including RF, including digital processing with AI, and sensor interfaces, all together with a complete power management on a single chip. [caption id="attachment_33090" align="alignright" width="175"] Philippe Berger, CEO, Dolphin Design.[/caption] This is a great opportunity for Dolphin Design. Adding the deep expertise of our engineers in this technology and our turnkey design platforms, we can really help companies targeting FD-SOI implement easily, quickly and safely an energy-efficient SoC. We have two complementary offerings for companies that want to leverage FD-SOI: A sensor-centric MCU subsystem as a configurable RTL design platform. This design platform, named Chameleon, allows achieving the best energy efficiency by turning the CPU off whenever possible and by eliminating latency and congestions on the memory bus. A power management design platform as a total solution to implement fast and safely a power management network that leverages low power techniques to meet the energy efficiency targets. This design platform, named Spider, combines a library of configurable power management IPs, including adaptive body biasing, with a scalable power controller enabling to control power and clock activity autonomously, even with the CPU off. We can intervene at a very early stage of our customers’ design cycles thanks to our system-level utilities rather than just IP bits and pieces. The figure below describes the components of our Spider power management design platform which is a key turnkey solution to leverage some unique capabilities of FD-SOI, such as the capability to operate at a very low voltage with a decent speed or the capability to support as high as 5V input voltage. ASN: What’s driving that business? PB: The emergence of new IoT and automotive markets is driving the business forcing IC design teams to pursue tough objectives: zero power consumption in off modes while maximizing the performance in active modes at minimal power consumptions. Unfortunately, scaling down to the next technology node makes it even harder to reduce power in off modes and is an expensive choice - too expensive - for many applications to achieve the energy efficiency targets in active modes. As a result, design teams must now pursue their gains by deploying increasingly complex power management techniques to meet the stringent requirements of the new IoT markets. This is particularly tricky in advanced IoT where near-sensor processing must be efficiently combined with RF connectivity, together with advanced power management. In addition, designers must confront the complexity of supporting high input voltage for interfacing with 4.2V/4.4V Li-Ion batteries or 5V USB charging mode that rely on 1.8V IO transistors. The need for solutions that enable to select fast and to implement safely the power management network which allows a seamless system-level integration while meeting power consumption targets in each SoC power mode -- that drives our business. SN: What do you see as the biggest benefits – and challenges – for designers moving to FD-SOI? PB: Its biggest benefit is its high integration capability. One of its key challenge is the ”so-far” relatively more complex design methodology that is required to take advantage of all FD-SOI characteristics, namely for example the biasing of the bulk to either reduce leakage or improve energy efficiency depending on working mode and technology centering. And ultimately, assuming the FD-SOI design flow is no longer a point of discussion, we need to get all designers “Thinking FD-SOI”. By that I mean to be aware of the breadth of FD-SOI advantages, so they are using it at every possible opportunity: in RF, in switches, in A/D converters (ADC) – in everything! FD-SOI’s double gate lets you think about more than decreasing noise and energy consumption. There are many opportunities for many blocks – especially analog. [bctt tweet="We need to get all designers “Thinking FD-SOI” so they’re using it at every possible opportunity: in RF, switches, ADC – in everything! Body biasing is usually thought of in the digital context, but it is also very useful in analog. – DolphinDesign CEO" username="soiconsortium"] SN: What does Dolphin Design offer designers moving to FD-SOI? PB: In order to ease these tasks, we developed the turnkey Spider platform based on power management IPs and system-level utilities. It speeds-up the design of energy efficient power management systems to weeks instead of months. Spider obviously exists in FD-SOI technology. It enables chip-architects to explore many power architectures and to select the best one to match the targeted PPA. It bridges the complexity gaps of designing fast and safely a power controller that can deal with numerous power domains and several operation modes for each domain and that can operate even when the CPU is off. Then, it bridges the gap between standard RTL and GDS flow, as it is able to generate the UPF backbone of the SoC. It offers a standardized and predictable power management flow, securing first silicon success. As an example, one of our key customers doing a ULP MCU shared that they have been able to design a complete power controller in less than one week instead of a couple of months. SN: You announced design kits with Adaptive Body Bias (ABB) solutions for GlobalFoundries’ 22FDX technology at the end of 2019. What challenges is that solving? PB: In the race for higher energy efficiency, digital designers face the impact of process variations. Chip designers have added margins all along their design to ensure the future chip will work fine whatever the technology centering after fabrication. Performance or size tradeoffs are necessary to cope with extreme variation cases (the so-called “corners”). At low voltage, SoC designers often use compensation techniques to limit the impact on the SoC energy efficiency. Through the control of transistor threshold voltage in FD-SOI technology, body biasing acts as a fantastic and automated control method to offset all variations. Designers can design their SoCs with reduced design corners for process, temperature and aging, boosting the PPA trade-off up to 10x at low voltage. We have been cooperating with GlobalFoundries over the last two years to provide the market with an Adaptive Body Bias (ABB) IP solution. The ABB feature allows designers to leverage forward and reverse body bias techniques to dynamically compensate for process, supply voltage, temperature (PVT) variations and aging effects. Our ABB IP embeds the body bias voltage regulation, PVT monitors and aging sensors, and a control loop. From standard-cell library to sign-off verification, our customers will continue to use their usual standard flow. For IoT on GF 22FDX, the design kits are available for production. For automotive, it will be in the next months. SN: Looking to the future, will there be a need for more application-specific FD-SOI IP? Where are the growth opportunities? Which ones will you be working on? PB: We anticipate new needs along the time as new applications will emerge in FD-SOI. We have a roadmap to enrich the catalog of power management IPs for addressing each market vertical with the most complete offering. But where we see the biggest growth for us is the growing adoption of power management IPs even by companies that were used to make voltage regulators on their own. Power management is no longer an issue of designing some good voltage regulators, like LDOs. Fabless companies face the challenge of dealing with the growing complexity of SoC power management network. It absorbs a significant portion of their design “energy”, in logic and in analog domains. They need to customize voltage regulators for each SoC and to maintain their design to keep them competitive. They also face the challenge of complex and sensitive power controller design. Finding the right design expertise to make such complex SoCs is a challenge in itself and in many cases power management complexity is the cause of a design respin. With the emergence of solutions such as Spider, that streamline and secure the selection and the implementation of the power management network, fabless companies start to question whether their core competency is power management IP design or if they can focus their design resources where they are the best at. The addition of body biasing into this picture makes it even more obvious for fabless companies that relying on a solid IP partner is a strong option. For Dolphin Design another opportunity for growth will mainly come from our capability to expand our offering for complementary design platforms for various FD flavors. We will communicate a lot in the coming months on our design platforms. We are also looking for diversification to other SoC functionalities. Processing is definitely an area in which we are significantly investing (MCU sub-systems and their associated DSPs), but energy harvesting and RF could also be good candidates in the future. SN: Dolphin Design is a member of the SOI Consortium. What do you see as the advantages of membership? PB: The 2019 Silicon Valley SOI Symposium was my first participation in an SOI Consortium event. [Note: you can get his full presentation here.] My first impression was good! I was positively surprised by the wide diversity of material shown. But really the key advantage was the opportunity to meet with so many different companies, all involved, from near or from far, with an FD-SOI tape out. It really helped me understand what I needed to put my teams to work on next!

The Compact Model Coalition (CMC) has selected Leti’s L-UTSOI as a standard model for FD-SOI in the industry. The CMC is a working group composed of the major semiconductor companies and is part of the Silicon Integration Initiative (Si2). The Si2 Compact Model Coalition announcement covers the approval and financial support of L-UTSOI. L-UTSOI is derived from the Leti-UTSOI compact model, which has been implemented in circuit-simulation software and used in industrial process design-kits for several years. Thierry Poiroux, head of CEA-Leti’s Simulation and Compact Model Laboratory, said the selection of L-UTSOI as a Si2-CMC standard model ensures that it will be supported as long CMC industry members use it. “This is of paramount importance for large chip makers who will use this model in the future,” he continued. “With a standard model, they are assured that a team of model developers is able to take care of the model improvements and/or bug fixes they need during the whole lifetime of their technology. It also positions CEA-Leti among the few compact-model developer teams able to develop and support a standard model.” The role of compact models Once a new or enhanced chip is designed, it must be simulated prior to entering the expensive manufacturing phase. This proof-of-concept step relies on compact models that are expressed through a set of equations implemented in a form ensuring accuracy, robustness and numerical efficiency. Such compact models are approved and supported by the standard-setting arm of Si2, the CMC, which is an international working group focused on standardizing SPICE device models. “As a member-driven organization, the CMC strives to provide value for its members and the semiconductor supply chain,” said Peter Lee, CMC chair. “With 15 models now available, CMC members have a distinct competitive advantage with early access to new features and bug fixes, and an 18-month lead on standard models released to the public. Adding L-UTSOI to the mix of models was a direct response to our customer requests for model support as we continue to add value to their membership.” Standard models are developed by the world’s leading SPICE-model experts. They are used by designers working at the most advanced fabless semiconductor companies, foundries, and IDMs. Implemented in the industry’s top versions of circuit-simulation software and duly qualified, standard models give designers the assurance that their integrated circuits will perform according to the design specifications. Industry proven L-UTSOI was extensively proven by the industry and its standardization will ensure long-term access and maintenance in EDA tools for FD-SOI designers. Available to coalition members now, it will soon be implemented in major versions of circuit-simulation software, and its source code will be released publicly in June 2021. “CEA-Leti’s compact model boasts physically based model parameters,” said Harrison Lee, chair of the L-UTSOI Working Group and principal engineer of the Foundry Design Enablement Team at Samsung Electronics. “We can utilize predictive analysis of a process technology to optimize a transistor’s design implementation for a specific end-use. With a capability to 10 nanometers and below and the ability to simulate a wide range of voltages and body biases, we can easily research a wide variety of analog and digital applications.” As noted in Leti’s announcement (read the whole thing here), the FD-SOI transistor’s back-gate allows tuning of the device in a low-leakage and low-power operating regime or higher-performance operating regime. This unique capability offered by FD-SOI enables the fabrication of smaller, faster and denser chips than standard bulk CMOS technology. FD-SOI devices are widely used in wearable electronics, automobiles and IoT. Leti pioneered FD-SOI in 1992. Here at ASN we’ve been covering their FD-SOI compact model work for over a decade.

GlobalFoundries recently announced that its embedded magnetoresistive non-volatile memory (eMRAM) has entered production on the company’s 22nm FD-SOI (22FDX®) platform. (See the full press release here.) The company says this advanced embedded non-volatile memory on its FDX™ platform provides a cost-effective solution for low-power, non-volatile code and data storage applications. It is now working with several clients with multiple production tape-outs scheduled in 2020. GF heralds the announcement as a significant industry milestone, demonstrating the scalability of eMRAM as a cost-effective option at advanced process nodes for IoT, general-purpose microcontrollers, automotive, edge-AI, and other low-power applications. [caption id="attachment_31334" align="alignright" width="485"] (Courtesy: GlobalFoundries. Click to enlarge.)[/caption] “We continue our commitment to differentiate our FDX platform with robust, feature rich solutions that allow our clients to build innovative products for high performance and low power applications,” said Mike Hogan, senior vice president and general manager of Automotive and Industrial Multi-market at GlobalFoundries. “Our differentiated eMRAM, deployed on the industry’s most advanced FDX platform, delivers a unique combination of high performance RF, low power logic and integrated power management in an easy-to-integrate eMRAM solution that enables our clients to deliver a new generation of ultra-low power MCUs and connected IoT applications.”[bctt tweet="In production! @GlobalFoundries’ eMRAM on #22FDX FD-SOI replaces #eFlash for #IoT genpurpose #microcontrollers #automotive #edgeAI more. #lowpower #chipdesign #FDSOI" username="@soiconsortium"] [caption id="attachment_31330" align="alignleft" width="467"] (Courtesy: GlobalFoundries. Click to enlarge.)[/caption] Designed as a replacement for high-volume embedded NOR flash (eFlash), GF’s eMRAM allows designers to extend their existing IoT and microcontroller unit architectures to access the power and density benefits of technology nodes below 28nm. It is a highly versatile and robust embedded non-volatile memory (eNVM) that has passed five rigorous real-world solder reflow tests, and has demonstrated 100,000-cycle endurance and 10-year data retention across the -40°C to 125°C temperature range. The FDX eMRAM solution supports AEC-Q100 quality grade 2 designs, with development in process to support an AEC-Q100 quality grade 1 solution next year. [caption id="attachment_31331" align="alignright" width="280"] GF’s state-of-the-art 300mm production line at Fab 1 in Dresden, Germany, will support volume production of 22FDX with MRAM. (Courtesy: GlobalFoundries)[/caption] Custom design kits featuring drop-in, silicon validated MRAM macros ranging from 4 to 48 mega-bits, along with the option of MRAM built-in-self-test support is available today from GF and their design partners. eMRAM is a scalable feature that is expected to be available on both FinFET and future FDX platforms as a part of the company’s advanced eNVM roadmap. GF’s state-of-the-art 300mm production line at Fab 1 in Dresden, Germany, will support volume production of 22FDX with MRAM. Prior to this announcement, an excellent GF blog by David Lammers recapped GF's 2019 IEDM presentation of their eMRAM reliability data. You can read that here. It also provides a lot of interesting background information.

Digitimes Research is predicting a doubling of the global SOI market between 2019 and 2024, "...thanks to significant expansion in applications to mobile devices, communication infrastructure, IoT devices and automotive electronics in the 5G era...". (Read the full article in Digitimes here.) Beyond the continued enormous success of SOI in front-end modules (FEMs) for RF (aka RF-SOI, which as we know is found in every smartphone on the planet), the report cites high growth specialty areas such as imaging chips for smartphones and photonics in data centers. They also predict that FD-SOI will be "massively applied" in 5G, with applications in base stations and data centers. And of course, low voltage and low power consumption will be the big drivers in IoT and wearables. All this is driving Soitec, the major SOI wafer manufacturer, to expand capacity at its facilities in France and Singapore in 2020, says the report. This is happening in strategic cooperation with Shanghai-based Simgui. As noted in ASN about a year ago, Soitec and China’s SOI wafer leader Simgui announced an enhanced partnership and increased production capacity of 200mm SOI wafers in China, securing future growth. At that time the two companies redefined their manufacturing and licensing relationship to better serve the growing global market for RF-SOI in mobile and Power-SOI in automotive and consumer electronics. Separately, Okmetic of Finland, which specializes in SOI wafers for MEMS, sensors and RF, is also doubling its capacity (we covered their 2019 Shanghai presentation here.) (Image courtesy: Soitec)