SiP

Jay Vleeschhouwer, managing director of Griffin Securities, has followed the EDA industry as a leading financial analyst for 25 years and is a popular speaker at the annual Design Automation Conference. Vleeschhouwer discusses his DAC presentation The State of EDA: A View from Wall Street.

Dr. Walden Rhines, former CEO of Mentor Graphics (now Siemens EDA), and current CEO of Cornami, recently joined Dan Nenni of SemiWiki.com for a podcast to discuss the latest Electronic Design Market Data (EDMD) report.

SEMI has long promoted the industry collaboration that has contributed to the rise of the smart digital world we live in today. A world where data is being generated continuously by systems, gadgets, and sensors around us – often referred to as the Internet of Things (IoT). In our personal lives, most of us have smartphones, smart watches, smart TVs and smart cars, and we live in smart homes and smart cities generating huge amounts of data.In the work world, data and analytics are now influencing almost every industry including healthcare, government, financial services, construction and transportation. This data has the potential to transform our lives and make our world even smarter – if we can communicate and process this data, and use it to come up with actionable recommendations or actions. Artificial Intelligence (AI) and Machine Learning (ML) techniques have generated much excitement precisely because they offer us ways to realize the full value of data by harnessing it and transforming it into active intelligence.Data-intensive technologies are required to store, communicate and analyze data. And it all starts with innovation in microelectronics chips and systems spanning processors, memory, sensors, radios and other devices, presenting a huge opportunity to producers of these technologies. However, with Moore's Law beginning to slow, technology paths and innovation options are diverging. Companies must swiftly assess these options in order to develop competitive offerings. But the technological complexity and divergence makes it increasingly expensive or even unaffordable for many companies to track and pursue these options.The good news is that cost-effective early assessment is possible through pre-competitive collaboration that can produce new and often unexpected cross-disciplinary insights by overcoming traditional silos in industry and academia. Unfortunately, important collaborative industry platforms, such as the International Technology Roadmap for Semiconductors (ITRS), have folded, opening a collaboration gap in the global microelectronics ecosystem.As part of its mission to help companies connect, collaborate, and innovate, SEMI has built a collaborative, cross-supply-chain platform – the Strategic Innovation Platform (SIP). The goal is to provide early and comprehensive assessment of future technologies that are five to eight years away from commercialization. The assessment identifies not just technical barriers but also manufacturing and supply-chain constraints to implementing new technologies. SIP brings together the entire microelectronics ecosystem including strategic technology thought leaders, subject matter experts, technology and application developers, academia, researchers, start-ups and government. With more than 2,100-member companies spread across the global electronics manufacturing supply chain, SEMI is uniquely positioned to enable this critical collaboration. Award-Winning First ProjectThe inaugural SIP project assessed key drivers of future technologies. A key finding was that fast, efficient interconnects between devices and components are critical to the system performance important to customers and users, implying that system-level optimization is required. For data-intensive applications, interconnects have emerged as a key bottleneck for both performance and power in various circuits and systems in part because the slowing of Moore’s Law has decelerated advances in individual device performance, and in part because systems are becoming more complex, requiring heterogeneous integration.To address this challenge, SIP brought together industry experts from ASE Inc., Dow Chemical, Lam Research, Qualcomm and Xilinx to assess the future impact of interconnects for data-intensive applications. SEMI also involved Stanford University professors to collaborate on modeling and simulation. Through this unique cross-disciplinary collaboration, SIP developed a realistic model to evaluate the system-level performance of single-chip systems, as well as multi-chip systems – including traditional 2D packages, high-performance 2.5D systems that use interposers, and futuristic 3D systems. SIP also explored supply chain challenges in business continuity, manufacturability, Environment, Health and Safety (EHS) and the regulatory environment. SEMI worked with a broad range of industry partners to ensure that the model parameters accurately reflected realities on the design and factory floors to ensure usable results. Experimentation has become ever more expensive, with one industry player reporting that “it costs us $100 million to do a good experimental evaluation.” Accurate models can go a long way toward reducing the cost of technology assessment. The SIP collaboration produced key quantifiable insights including comparisons that highlight the benefits and limitations of various materials being explored for future interconnects, and of architectures under consideration for future data-intensive applications. For example, the current workhorse for artificial intelligence (AI) platforms – 2.5D technology – delivers a 4X improvement over 2D packaging but falls short of providing the orders-of-magnitude improvement that future AI/ML applications may require. These findings enable the industry to begin to identify ways to optimize 2.5D architectures, transition to 3D heterogeneous integration for performance-critical applications in the medium term, and to eventually evaluate new paradigms such as neuromorphic and quantum. The project findings were presented late last year in the form of two research papers at Electronics System-Integration Technology Conferences (ESTC) and International Microelectronics Assembly and Packaging Society (IMAPS) recently. One received the “Best Paper of the Session” award at IMAPS – a recognition that affirms the power of a collaborative platform such as SIP to produce valuable insights to address the growing technology complexity within the microelectronics industry. The microelectronics industry is on the cusp of a historic inflection point, where it could fuel the rise of emerging applications in AI/ML and IoT, and can grow into a trillion dollar industry over the next several years. More importantly, the industry is poised to help solve some of society’s most complex problems in areas including healthy living, climate change and transportation. No company can do this alone, and pre-competitive platforms such as SIP are key both to accelerating innovation through cross-disciplinary collaboration, and to reducing costs for individual companies. Please contact Tom Salmon at [email protected] or Pushkar Apte at [email protected] for more details and to get involved in future projects.Tom Salmon is vice president of Collaborative Technology Platforms. Pushkar Apte is a strategic technology advisor at SEMI.

SEMI met with Gerald Beyer, program manager at imec, to discuss the co-existence of various 3D interconnect technologies and their need for new materials and integration solutions. The two talked in the runup to his presentation at the Advanced Packaging Conference at SEMICON Europa 2018, 13-16, November 2018, in Munich, Germany. To register for the event, click here. SEMI: Can you confirm this trend towards heterogeneous integration and do you think it will be a long-term development trend?Beyer: We consider heterogeneous integration as a scaling booster for functional partitioning and as a fashion method to create systems, which would not be possible or economical on such as a single chip. As you can apply it to numerous systems, we expect it to stay for the long term.SEMI: What are the new critical challenges for the combination of different technologies into one package?Beyer: When you create a complex system, there is usually more than just one challenge. On one side, you need to be able to design such a system. If you disintegrate a large chip, you need to decide how to reconstruct it, i.e. which function goes into which strata. You would like to do that not manually but with a set of tools supporting the designer. Only recently EDA (Electronic Design Automation) and design houses have started to support this idea.On the technology side, interconnections between some strata of such a reconstructed chip will require small pitch interconnects of the order of 1µm pitch and less. Today, wafer-to-wafer bonding technologies have sufficient overlay margins for 1µm pitch. Wafer-to-wafer bonding technologies, however, have a number of constraints such as equal die size and the necessity to realize chip stacking rather in a fab environment than in a traditional packaging house. Die-to-wafer assembly technologies still need to bridge the gap to deep sub 10µm pitch in terms of alignment and cleanliness.SEMI: What kind of new materials or integration solutions do you expect to be developed? Are you working on it already?Beyer: As explained above, die partitioning requires sub 1µm pitch interconnects. We are investigating fine pitch wafer-to-wafer and die-to-wafer (direct) bonding. For the latter, not only new alignment capabilities but also die cleaning and thin die handling technologies need to be developed. To build a complete system with data processing, memories etc., novel integration schemes such as Flip Chip – Fan Out Wafer Level Packaging with high density 2D and 3D interconnect capabilities are being investigated. These new systems differentiate from current ones by high density Through Package Vias (TPV), Si bridges and sub 2µm line/spacing RDL. The new integration approaches push the materials such Temporary Bond Materials (TBM), Wafer Level UnderFill’s (WLUF), photo patternable polymers for fine Line/Spacings to name a few, to the limits. Hence, development of new materials is a key aspect.SEMI: What trends and developments do you expect in the near future and why would you recommend attending the Advanced Packaging Conference?Beyer: The development and commercialization of products using heterogeneous integration is a big effort drawing on resources from EDA vendors, materials and packaging tool suppliers, OSATs, foundries, memory suppliers and IEDMs and academia alike. The agenda of the Advanced Packaging Conference at SEMICON Europa reflects this diversity and I am looking forward to interesting discussions with all participants. Gerald Beyer has been working in the field of 3D Technologies since 2012 as the technology program manager of the 3D System Integration Program of imec. Prior to this role, he was the interconnect program manager and group leader of BEOL integration. He received a PhD in materials science from Imperial College, London and a MSc from Thames Polytechnic, London.Serena Brischetto is a marketing and communications manager at SEMI Europe.

Outsourced Semiconductor Assembly and Test (OSAT) service providers experienced strong growth in 2017, but will this growth continue? In the last few years, OSAT growth has been driven by shipments for packages found in smartphones, but this market is slowing. What will replace it? Growth in power devices is strong and electronic content in vehicles is increasing. Will OSATs participate in this growth? Many OSATs have plants dedicated to automotive package assembly and will see continued growth. Growing demand for connectivity everywhere, called IoT, is generating large amounts of data, creating the need for more servers and datacenters. The adoption of Artificial Intelligence (AI) across a broad range of applications is driving demand for high-performance packages, but will this assembly take place at the OSATs or foundries? In the third and fourth quarters of 2017, growth in cryptocurrency provided unanticipated revenue for a number of OSATs. Given that the most well-known crypto mining companies and the biggest mining pools are all based in China, several OSATs, including major Taiwanese and Chinese service providers, experienced revenue growth in 2017 directly attributed to the assembly of ASICs in flip chip scale packages (FC-CSPs) and GPUs in flip chip ball grid arrays (FC-BGAs) for the cryptocurrency market. However, the first and second quarter of this year has seen decreased demand for GPUs and ASICs for this application. The assembly of packages for cryptocurrency slowed considerably in the first half of the year and therefore can’t be counted on to add as much to the revenue base as in the previous year. Going into the latter half of the year, the demand for Crypto ASICs is expected to pick up as new generation of 7nm chips will drive new investment and replacement cycle while crypto-mining GPU will see a further decline. Three of the top 10 OSATs, Jiangsu Changjiang Electronics Technology (JCET), Tianshui Huatian Technology (Huatian), and Tongfu Microelectronics (TFME), are based in China. China’s share of the top 10 OSATs’ revenue increased from slightly less than 23 percent in 2016 to more than 25 percent in 2017, and this trend is expected to continue. Crypto-related packaging and test business has certainly contributed a big portion of the share gain. Major OSATs such as TFME and Tianshui Huatian plan expansion in their plants and they expect to fill this added capacity in a broad range of packages. Huatian’s new Nanjing plant will include assembly for memory packages. TFME plans to set up a plant in Xiamen, Fujian Province to provide bumping, wafer level packaging, and system-in-packaging (SiP) services. Tracking the capabilities of OSATs is increasingly important. SEMI and TechSearch International have introduced a new Worldwide OSAT Manufacturing Site Database that provides listings of OSAT facility locations and package and test options in each factory. This database indicates the specific packages offered at each location. Finding plants that offer automotive qualified assembly is also possible with the database. Companies that offer bumping and wafer level packaging are identified. Over 120 companies and 300 facilities are tracked in this database covering both OSAT packaging and test facilities. For additional information about this informative database, please visit https://discover.semi.org/osat-database-registration.html E. Jan Vardaman is president of TechSearch International, Inc., and Clark Tseng is director of Industry Research and Statistics at SEMI.

What’s next for smarter, more connected electronics manufacturing - Part 1The fast-maturing infrastructure now enabling applications for big data and artificial intelligence means disruptive change not just at individual companies but also in data connections among companies across the microelectronics manufacturing value chain. SEMI expands its smart manufacturing program with a Smart Manufacturing Pavilion with displays and three full days of talks to address these industry-wide developments at SEMICON West, July 10-12 in San Francisco.Autonomous autos’ demand for zero-defect systems and 100 percent traceability back to the manufacturing data for each die is driving a push to traceability across the chip sector. “Far more chips are being used by the automotive sector, and its very different requirements are driving demand for traceability,” says Tom Ho, president of BISTel America. “Our chipmaker customers are looking for traceability solutions and the trend is the same in backend packaging and assembly – automotive applications are driving the sector to traceability.”Traceability is also driven by the growth of systems in a package as fabless chipmakers look to connect back to the packaging companies’ fault analysis labs and die interconnect history to diagnose and fix the cases where known-good die are failing in the system, adds Mike Plisinski, CEO of Rudolph Technologies. Plisinski adds that makers of consumer products like phones that can also see harsh conditions are demanding higher quality and traceability as well. The electronic manufacturing services (EMS) sector also must establish an architecture for traceability to collect critical manufacturing-related data and to interface with OSATs and semiconductor fabs. The reason is that EMS companies are adding traditional OSAT processes such as assembly of products with bare die and complex optics modules requiring clean rooms. “A unified sand-to-smart-phone smart manufacturing roadmap should be established,” says Dan Gamota, vice president of Engineering and Technology Services at Jabil. “We need to identify protocols for manufacturing data communications that can be adopted across the supply chain.”To enable smart manufacturing, vendors need to collaborate on getting their production equipment to interoperate and support factory analytics and data management systems. Source: SEMI One big challenge, of course, is how to format this diverse data so it can be linked and used by various supply chain stakeholders. “Smart data needs to be contextual and it needs data standards across the supply chain so it’s easy to link from the front end to the back end, follow common lot IDs front and back end, and have a way to map streaming data from sensors to a discrete lot ID,” notes Ho. New approaches to metrology, analysis and test that increasingly exploit machine learning on simulations will also be needed to help predict which die and connections that test well now may fail in the future as conditions change.Another issue is how to securely share the needed data across companies without jeopardizing IP. “On the equipment side we collect data across customers on how the tool is running to improve the equipment,” notes Neal Callan, ASML VP Silicon Valley. “Next we need to integrate performance and reliability data that today is not as well shared.”The other big hurdle is how to pay for data sharing. “The challenge is that the final manufacturers reap the benefit of traceability, but since they expect their suppliers to deliver good die, they don’t want to pay more for it,” notes Plisinski. He suggests that over the next two to three years, traceability and predictive fault prevention will become the norm as the automotive sector is compelled to invest in it to assure safety. Meanwhile, fabless companies will face so much complexity in integrating different die from different suppliers in SiP that they will no longer be able to afford to simply use the cheapest supplier, potentially driving a fundamental shift in relations and division of labor among fabless chipmakers, OSATs and fabs. Standards extend across supply chainSEMI member committees are collaborating to build the infrastructure to enable these developments. Standards committees are updating standards for higher bandwidth data exchange and extending semiconductor-like vertical and two-way horizontal equipment communication standards to flow shops to enable assembly players to optimize and trace back results across players. The SMT/PCBA community is integrating its smart manufacturing work into SEMI standards, and the SEMI A1 standard was a key reference document in the development of the Japan Robotics Association’s Equipment Link Protocol.Speakers addressing these issues at SEMICON West include Active Layer Parametrics, Applied Materials, Applied Research Photonics, ASML, Bosch Rexroth, Cimetrix, Coventor, ECI Technologies, Edwards Vacuum, Final Phase Systems, GE Digital, Infineon, Jabil, Lam Research, Osaro, Otosense, PEER Group, Qualcomm, Rockwell Automation, Rudolph Technologies, Schneider Electric, Seagate, Siemens, Stanford University, TEL, TIBCO Software. See semiconwest.org.What’s next for smarter, more connected electronics manufacturing - Part 2What’s next for smarter, more connected electronics manufacturing - Part 3Paula Doe, SEMI