DRAM

Powerful winds of change are re-shaping the semiconductor industry as it flexes and re-positions to power a new wave of growth on the back of emerging applications. Today, the industry is thriving, with growth expected to continue through 2019 even as Moore’s Law – the trusty doubling of transistors roughly every two years – begins to pump the brakes. Product mix and production technology are shifting as the dominant smartphone and PC markets, having seen their growth peaks, start to give way to large markets with relatively low semiconductor penetration, such as automotive.What’s more, new potentially ubiquitous technologies and platforms such as AI, blockchain and smart manufacturing are redefining market dynamics and the semiconductor ecosystem that underlies them.Troublingly, the most significant threats to the continued growth of the semiconductor industry are not of its own making. Macroeconomic trends and trade policy disputes loom.These were some of the key takeaways from the SEMI Market Symposium kicking off SEMICON West in San Francisco this week. Following is a deeper look.Semiconductor MarketThe consensus view, reflected in forecasts presented by Clark Tseng of SEMI and Bob Johnson of Gartner, is that the semiconductor industry could top $500 billion in 2019 after reaching $400 billion in 2017. According to Gartner, smartphones and PCs will continue to account for large parts of the market, but will be displaced as major drivers of market growth by the emergence of industrial, automotive and, to a lesser extent, storage, from 2017 to 2022. Johnson noted that while communications and data processing applications drive logic device demand, average sales prices (ASPs) are a bigger contributor to revenue growth than unit growth.Leading-edge processors are a big part of the ASP picture, with equipment costs increasing ~20 percent per node. One challenge is that as Moore’s Law loses steam, leading logic producers are increasingly going their own way with new production technology. The volatile DRAM market – now in a “super cycle,” according to Tseng, and expected to peak in 2019 – has been stoking memory market growth.Initially, supply shortages fueled memory price increases as three of the four leading memory makers invested in flash rather than DRAM capacity. However, memory prices have been more recently been lifted by technology complexity, particularly as DRAM has moved to 3D architectures. The good news is that pricing, at long last, appears to be driven by value.Automotive MarketWith automotive accounting for less than 10 percent of semiconductor demand, there is room for growth. Rudy Burger of Woodside Partners noted that while the end market for automobiles is growing slowly, at 3 percent CAGR, the market size is nearing 100 million units. In market segments such as electric vehicles, the semiconductor content exceeds $1,000 but can be much higher.For example, the BMW i3 sports over $4,000 in semiconductor content. Burger said connectivity, autonomous driving and shared mobility services are also key opportunities for semiconductors to deepen their penetration in automobiles. For instance, the auto market for cameras, is expected to grow from $2 billion in 2017 to $6 billion in 2022.On average, high-end vehicles feature over $1,000 in semiconductor content, whereas low-end vehicles hover in the $400 range, said Anand Srinivasan of Bloomberg. Because the automotive market is segmented by function or subsystem, with different suppliers focusing on different areas, there is little supply concentration. Srinivasan also pointed out that because of significant differences in their objectives, automotive safety and automation systems should be developed separately.BlockchainThe chief benefit of blockchain is the trust it begets among all parties to a digital transaction through four fundamental features, said David Treat of Accenture: The tracking of provenance (knowing who has touched data, and what has happened to it) Tamper evidence (knowing if someone has tried to change the data) Control (which data elements to share with which parties) Security at the data element level While most of the hype over blockchain focuses on tokenized assets and ledgers (bitcoin and other cryptocurrencies), the fundamental application in the semiconductor industry is sharing trusted access to reference data at the data element level. This ability to provide shared trust can reduce costs throughout the supply chain and across enterprises. For example, future blockchain implementations will offer a full ecosystem view to any supply chain participant. While blockchain has typically been deployed through centralized control or platforms, peer consortia, such as SEMI, could help weave the benefits of blockchain through various ecosystems by enabling equipment and material suppliers, device manufacturers, designers and system integrators to share business and technical information securely and, if desired, anonymously.Global and Macroeconomic TrendsThe biggest threats to the continued growth of the semiconductor industry are exogenous. After a decade of steady recovery since the financial crisis, the global economy appears to be heading for a slowdown. Duncan Meldrum of Hilltop Economics made the case that the global economy is at or just past the peak of the business cycle, and semiconductor equipment is past the peak.A key indicator of a looming recessionary is the movement toward an inverted yield curve, in which long-term interest rates fall below short-term rates – a phenomena that could materialize this year or next.The increasingly heated trade climate, marked by high-stakes confrontations between the U.S. and China, threatens complex supply chain arrangements, though mercurial policy statements could do even more harm than stiffer trade tariffs. Underscoring competing interests between the U.S. and China and the unpredictability of their relations, Robert Maire of Semiconductor Advisors pointed out that, in 2019, 60 percent of all semiconductors are expected to be used in China, deepening the dependency of several U.S. semiconductor companies on China.Paul Semenza, for SEMI Industry Research and Statistics

This year’s Advanced Lithography TechXPOT at SEMICON West will explore the progress on extreme ultra-violet lithography (EUVL) and its economic viability for high-volume manufacturing (HVM), as well as other lithography solutions that can address the march to 5nm and onward to 3nm. Several session speakers offered their insights into the readiness of EUVL for 5nm and how other lithography solutions will enable 3nm. See the full list of speakers and program agenda at http://www.semiconwest.org/programs-catalog/lithography-5nm-and-below.Diverging viewpoints on EUVL readiness for 5nmMike Lercel, Director of Strategic Marketing at ASMLASML expects its first customer to start volume manufacturing with EUV at the 7nm logic node and the mid-10nm DRAM node in the 2018/2019 timeframe. “EUV will replace the most difficult layers that require multiple patterning, and many layers will continue to be allocated to immersion tools for the foreseeable future,” said Lercel. “For the 5nm logic node, more layers are expected to migrate to EUV.”Three ASML customers have early-access versions of the next-generation TWINSCAN NXT:2000i for the development of advanced logic and DRAM nodes. “This system delivers 2.0nm cross-matched on-product overlay, achieved through several hardware advancements,” noted Lercel. “It is also significant because this mix-and-match use with EUV features a significantly different hardware platform.” TWINSCAN NXT:2000i features a new alignment sensor and improved wafer table flatness, endurance, and clamping mechanism to enhance matching to EUV.ASML has achieved good industrialization progress of its pellicle, with tests confirming that pellicles can withstand 245W source power and an offline power lifetime test indicating 400W capability. Compared to the 7nm logic node, the requirements for EUV masks will become tighter at 5nm, but Lercel noted that ASML sees good progress with the industry infrastructure to support 5nm in areas such as reducing mask blank defects. “We will continue to improve pellicle transmission for enhanced throughput, but there are no fundamental changes in pellicle requirements for 5-3nm logic nodes. We see no infrastructure showstoppers for the introduction of EUVL at the 5nm node.”Stephen Renwick, Director of Imaging Physics at Nikon Research Corporation of AmericaRenwick said that the 7nm logic node is expected to be fabbed mostly using 193i lithography. “EUV will struggle to be ready for 5nm, limited by yield issues caused by stochastic effects in the resist,” said Renwick. “Ready or not, though, it will be used.” Renwick suggests that introducing multiple-patterning with EUV may be needed but would increase costs. “193i lithography will continue to be used with quadruple-patterning and in combination with other techniques – there is no single solution.”Figure 1. Normalized cost/layer vs. lithography method. SOURCE: Nikon Research Corporation of America When choosing between immersion lithography and EUV for different customer segments at 5nm, Renwick noted that the cost depends on the layer. “Some time ago, we calculated that the costs of either 193i triple-patterning or 193i SADP with two cuts were roughly equal to single-patterning with EUV,” explained Renwick (Figure 1). “That agreed with chipmakers' public estimates and meant that the choice of lithography method depended more on the performance tradeoffs involved, such as 193i's better line-edge roughness. At the 5nm node, we are probably faced with quad-patterning from 193i, double-patterning from existing EUV tools, or single-patterning from as-yet undelivered high-numerical aperture (NA) EUV tools.” Renwick believes that the competition between low-NA EUV double-patterning and 193i quad-patterning will be similar to the current situation (i.e., comparison of 193i triple-patterning or 193i SADP with two cuts vs. single-patterning with EUV), but for high-NA EUV tools he believes it's too early to say.Other challenges Renwick sees on the horizon for EUVL at 5nm are stochastic effects in EUV resists. “They cause yield problems on contact arrays and unacceptable line-edge roughness on line/space patterns,” said Renwick. “It's unlikely that these effects will go away without increasing the litho dose, which will further challenge throughput performance.” He also questions whether EUV pellicles, though under development, will be “ready for prime time.”Harry Levinson, Sr. Director of Strategic Lithography Technology and Sr. Fellow at GLOBALFOUNDRIESLevinson said additional fundamental engineering work is needed to ready EUV lithography for 5nm. “Among the top problems are stochastics-induced resist defects, which increase significantly as dimensions shrink below those for 7nm,” explained Levinson (Figure 2). “Higher exposure doses will be required to address these issues related to stochastics at 5nm, which will require higher source output” (than 7nm).Levinson said there will be greater motivation to use EUVL at the 5nm node vs. at 7nm to offset the large number of exposures associated with 193nm immersion multiple-patterning solutions. “The primary application of EUV lithography at 7nm will be for contact, via and cut layers,” Levinson noted. “It will be important to enable EUVL for metal masks at the 5nm node, which increases the need for an ample supply of very low defect EUV mask blanks.” Levinson added that the 7nm node is already stressing defect inspection capabilities, and no actinic defect inspection system is yet available for patterned masks. “This situation becomes more problematic with widespread application of EUVL to metal layers.” Mask development for 5nmChristopher C. Progler, CTO Strategic Planning at PhotronicsProgler said that the basic infrastructure for delivering EUV masks is available, especially for dark field layers and near in nodes. “The interconnected or more open frame patterns will need refinements to the processes and two to three nodes out will need certain new infrastructure,” said Progler. Overall, the main challenges for initial insertion are about creating a cost-effective and rapid-turn EUV mask process, he said. “The industry can certainly deliver EUV masks in some form. It is more a question of doing it efficiently and productively to match the stated value proposition of EUV over other lithographic methods. We don’t want a pick two of ‘cost, cycle time, capability’ sort of mask solution.” More specifically, Progler explained that after the initial EUV mask development for 5nm focused on contacts and block layers, the major push for N5 switched to delivering single-exposure EUV metal patterning as early as possible. “This has opened some new challenges for masks given the resolution, critical pattern density and tight pitch defect requirements of the re-aggregated single-layer metal mask designs,” said Progler. “For example, on the resolution side, we are accelerating the insertion of higher dose photoresists and also driving patterning module improvements in CD control, mask LER and sidewall angle.” Progler added that at N5, the mask 3D structure itself – including the sidewall – will have a greater impact on lithography because it is tied to stochastic error rates on the wafer.“Reliable, wide-area metrology for some of these 2D and 3D mask parameters is currently hard to come by. We may see an evolution of the blank structure at some point in N5, including hard mask options for pattern stability and expect earlier insertion of EUV mask process correction with model-based hot spot detection and rule checking as well. We also hope mask-scanner dedication is not needed, but there are some indications process sensitivity may push us earlier in this direction.” He added that to reduce metal layer defects, more attention needs to be devoted to advanced repair and model-based validation. “We are, unfortunately, still in a situation of blurry vision and high native defect counts alongside possible in situ contamination during mask changes.” Figure 2. Resist stochastics-induced defects. Graph courtesy of Peter DeBisschop, imec; SOURCE: GLOBALFOUNDRIES Progler pointed out that, with the advent at 5nm, metal masks will require some level of actinic blank inspection for yield, increasing the cost of an already expensive mask technology. “So, unless we want to contend with double and triple photomasks’ starts to deliver a single metal layer, it will be very important to tighten the multi-sensor inspection, defect abatement, and repair loops,” said Progler. He does see some clouds forming around high-volume manufacturing pellicles for metal layers. “This remains an open question, mainly for thermal and materials reasons, not to mention cost and cycle time,” Progler said. “We may be pessimistic, but we do not see an HVM pellicle solution converging in the required timeframe, which means leaning even more on a wafer-level inspection in the validation loop.” He believes that streamlining validation will be a differentiator. “I can imagine one losing most of the EUV cycle time benefits by endlessly circling masks around if this is not done well.” How does the industry get to 3nm? ASML plans to ship its first high-NA EUV prototope/pilot systems between 2020 and 2023 to support 3-2nm process development. “System designs are now being finalized and the platform is starting to come to life,” said Lercel. ASML supplier ZEISS is building a high-NA cleanroom for optics production. ASML believes that EUV, high-NA and DUV systems will be used together at the most advanced nodes and is designing to account for this mixed environment. “As chipmakers drive toward smaller geometries in the most advanced nodes like 3nm, they face unprecedented challenges in devices and materials. This will make the process control requirements even more challenging.” ASML is tackling these challenges with its YieldStar metrology platform, e-beam metrology (HMI) and computational lithography solutions that are designed to expand the process window, enhance process control, and improve patterning defect detection. “This ‘Holistic Lithography’ approach will become increasingly important to ensure throughput and yield at the most advanced nodes.”Levinson said that the issues he projects for 5nm will need to be addressed further at 3nm. “The challenges associated with resists at 3nm dimensions are such that it isn’t clear that chemically amplified resists will be capable of meeting requirements,” said Levinson. “If true, we would be seeing the most significant change in resist platforms in a quarter of a century. Potentially cost-reducing technologies such as directed self-assembly (DSA) are always welcome, but EUVL will be the lithographic workhorse through the 3nm node, and likely beyond.”At 3nm, mask makers will confront the realities of higher EUV NA tools. “We will need to implement thinner mask absorbers, new films, and perhaps hard masks,” Progler said. “This puts us in a new materials regime for masks, and history has shown us the mask industry takes a long time to refine processes and tools for new mask materials.” He explained that the small scale of the mask ecosystem and the small number of large suppliers available to address the challenges accounts for this lengthy time frame. Still, looking ahead, Progler noted that Photronics has already done a few studies on the impact of proposed half-field, high NA anamorphic optics on masks. "We uncovered some challenges that need to be addressed, particularly at boundaries and within the overall mask flow,” said Progler. As mask resolution continues to scale down, the industry will need fundamentally higher resolution mask making and inspection processes, requiring next-generation multi-beam mask writing and electron beam inspection, he explained.At 3nm and below, Progler noted that the metrology needs for masks, while not as severe as that for wafers at these nodes, will test the mask equipment infrastructure in ways that could challenge the relatively small mask industry. “Of course, EUV multi-patterning comes into play as well, and with that, the SRAF sizes will drop below 20nm, requiring an asymmetric compensation over a much wider influence area than the OPC people are used to considering.” With EUV multi-patterning, Progler explained that it will be increasingly important to match or pair EUV masks and to consider how 3D effects and stochastics will drive new technology to enable new requirements for high-speed metrology and simulation components. “All the justifiable hand-wringing over EPE with ArF multi-patterning today gets introduced to the EUV scene when masks are ganged together to make a single device layer,” said Progler.Debra Vogler, SEMI

The growth of China’s semiconductor industry outstripped sector expansion in many other regions in 2017 thanks in part to heavy government investments and supportive state policies. But China’s chip industry also struggled under the weight of overheated investment, inconsistent project quality, insufficient investment in research and development, a poor ability to innovate, and barriers to international cooperation. To overcome these headwinds to growth, China must identify global trends in the development of global semiconductor industry and better understand the forces it needs to mobilize to further expand its own semiconductor sector. AI and 5G fuel global semiconductor industry growthIn 2017, global semiconductor industry revenue reached a seven-year peak, expanding 22 percent to nearly USD 420 billion, and entered a new growth phase with artificial intelligence (AI), 5G and other new technologies leading the surge with greater market segmentation, diversification and decentralization. The emergence of smart automobiles, smart cities, smart medicine, AR/VR and other new markets headed the list of new applications. In the next three to five years, semiconductor industry growth is expected to remain stable, with no marked declines. In 2018, the growth rate is expected to fall to between 5 percent and 8 percent, with the expansion more comprehensive and balanced. The memory market, in particular, will find it hard to match its 2017 blistering growth rate. The market’s expected growth of 10 percent to 20 percent will be chiefly driven by DRAM and 3D NAND Flash. In 2019, NAND growth will continue but DRAM shipments could decline. Emphasis on both innovation and investment key to sustainable growth of Chinese IC Under the China government’s Guidelines to Promote National IC Industry Development, designed to provide key policy guidance and capital support for the development of China’s IC industry, the Chinese semiconductor industry is seeing particularly rapid growth that is expected to be a key contributor to continuing global industry expansion. In IC design, HiSilicon and Unigroup Spreadtrum RDA ranked among the top 10 in the world. In wafer fabrication, Chinese IC manufacturing accounted for 13 percent to 15 percent of global market capacity despite SMIC and Huahong Group lagging international competition in advanced processing. In packaging and testing – China’s strongest segment – JCET, NFME and Huatian Technology also ranked in the global top 10. The Guidelines to Promote National IC Industry Development has fueled a boom in capital investments. However, investments must go well beyond fab construction to add new capacity for China’s semiconductor industry to flourish. A strategy for sustainable, long-term chip industry growth must focus more on technology innovation while continuing heavy capital investments, though it takes time for innovation to lead to higher capacity demand and GPD growth and more jobs. Despite large investments by the 02 Special Project in semiconductor equipment and materials, China trails other regions of the world in advanced technologies. Global spending on semiconductor equipment reached a record-breaking USD 56 billion in 2017, with Korea a major driver. In 2017, Samsung alone invested USD 25 billion in semiconductor equipment, followed by TSMC (USD 10.8 billion), Intel (USD 11.5 billion), Hynix (USD 8.5 billion), Micron (USD 0.5 billion), SMIC (USD 2.3 billion) and YMTC (USD 2 billion). In 2018, Samsung’s equipment spending is expected to drop slightly, to USD 24 billion, while investments by Intel and TSMC will be remain roughly equal. China’s equipment spending will continue to grow in 2018, with SMIC and YMTC maintaining investment levels similar to last year’s and other China semiconductor manufacturers starting to ramp up investments. In 2018, China is expected to surpass Taiwan in equipment spending to claim the number two position after Korea. SIIP China dedicated to international connection and cooperation The huge investments in China’s semiconductor industry need to be supported by robust business strategies, greater international cooperation, deeper expertise in advanced technologies, and more skilled workers. China lags the global industry in all of these areas. The rapid rise of China’s semiconductor industry has raised concerns among many countries over China’s growing influence, with some, most notably the United States, going so far as to implement containment measures. Other regions including Japan, Korea and Taiwan followed suit. The continued growth of China’s semiconductor industry hinges on technological innovation enabled by international cooperation, as well as strong international communication to allay concerns and misunderstandings over the rising prominence of China’s chip sector. China must overcome these obstacles. One partial solution is for China to convince the rest of the world that its need a thriving semiconductor industry if only to meet enormous demand for electronics products within its own borders. As the largest international semiconductor industry association, SEMI enjoys a unique ability to strengthen the connection between China’s semiconductor sector and its international counterparts. SEMI is well-known for its vital support of the traditional semiconductor equipment and materials markets, but SEMI’s work also spans IC design, manufacturing, packaging and testing. What’s more, SEMI has expanded into innovative market vertical applications such as AI, smart manufacturing, smart transportation and smart automotive as it aims to bring together supply chains across these growth areas. For its part, SEMI China remains dedicated to improving communications and cooperation between the Chinese and global semiconductor industries. SEMI China will also continue to encourage deeper collaboration among individual enterprises and government institutions in the interest of industry growth while making full use of SEMI’s international, professional and localization platform to promote the development of China’s semiconductor industry. Last year, we established SEMI Innovation Investment Platform (SIIP) China to help grow China’s pool of skilled workers, promote advanced technology, generate industry capital, and expand China’s semiconductor industry while developing stronger connections with chip sectors in other regions. SIIP China is focused on the following: Promoting sustainable development of the Chinese semiconductor industry Establishing stronger connections to help take advantage of global technology and investment opportunities Providing a platform for open communications between the Chinese and global semiconductor industries Promoting greater coordination between China and its global partners Helping newly enterprises secure funds for expansion Encouraging greater cooperation with foreign semiconductor manufacturers in the interest of openness and mutual benefit will be the best way for China to overcome obstacles to the development of its semiconductor industry. Meanwhile, China will continue to strive to merge into the global semiconductor industry and become a key partner. SEMICON China has witnessed the development of Chinese semiconductor industry SEMICON China marked its 30th anniversary this year. Over the past three decades, China’s semiconductor industry has seen remarkable growth. This year’s SEMICON China was the largest ever. SEMICON China and FPD China 2018 numbered 3,628 booths, covered 74,000 square meters of exhibition space and attracted 1,116 exhibitors from 21 countries and regions and 91,252 professional attendees from 58 countries and regions. Most of China’s top device makers and global leading packaging houses, together with their equipment and materials suppliers, exhibited at SEMICON China and FPD China 2018, representing the global IC manufacturing ecosystem. The number of SEMICON China and FPD China 2018 visitors jumped 32.3 percent from last year, with representation by professionals from the design, manufacturing, assembly and test, equipment and materials sectors. Lung Chu is President of SEMI China.