Electronic Design Automation

Machine learning (ML) and artificial intelligence (AI) have ushered in tremendous opportunities for faster growth, problem-solving and technological development in the electronic system design ecosystem. Cadence Design Systems, Inc., a member of the ESD Alliance, a SEMI Technology Community, is at the technological forefront in incorporating ML techniques in its chip design products. I spoke with Chin-Chi Teng, Senior Vice President and General Manager of Cadence’s Digital Signoff Group, about how ML is reshaping EDA and the semiconductor industry, the cloud’s role in the evolution of ML in design and its impact on Moore’s Law. Teng also offers advice on how engineering students can calibrate their education to prepare to work with this transformative technology and urges them to have fun in the process. Smith: How is ML changing the EDA industry? Teng: ML is changing EDA for the better in many ways. It’s more difficult than ever to design chips, and ML is helping by overcoming the complexity, size and technology interdependencies. At the same time, ML is helping our own engineers solve certain classes of EDA algorithm, tool, and flow/solution challenges so that we can deliver even better EDA tools to our user base. The benefits can include reducing runtime, increasing quality of results, and being better equipped to manage vast complexity and data. Also, and maybe even more significant, is the potential boost to user and team productivity, where engineers have more time to focus on high-value problems because they no longer need to spend time on managing overwhelming volumes of data and details that can be easily automated. Smith: What is the potential impact ML can have on semiconductor design? Teng: ML technology can be leveraged in several ways to improve EDA tool performance and engineering team productivity. For example, we initially applied ML to applications such as formal verification, simulation regressions, analog circuit design, and PCB design. We targeted ML toward specific algorithms that processed lots of data to sharpen and speed decision-making. Then we started to look at digital implementation flows that combine multiple steps with multiple decisions in a recipe, especially for chip implementation where the more efficient use of engineering knowledge can make a substantial difference in the chip’s resulting power, performance and area (PPA). These flows present more challenges and require different ML and optimization techniques since the data points are expensive to create and the volume of data is huge. But flow optimization offers the largest rewards for companies investing in data collection and analysis to improve their operations and product quality. By using ML to improve the implementation flow, our users are seeing up to 20% better PPA and 10x improved productivity in developing data center CPUs and AI engines, automotive sensor processing SoCs, and mobile devices. Smith: What is the cloud’s role in the evolution of ML in EDA? Teng: More ML usage means there will be an inevitable surge in compute demand resources, and engineers need the ability to scale in parallel. The cloud provides engineers with the best opportunity to scale computing resources without facing procurement limitations. The cloud also allows engineers to use task-specific compute and ML accelerators and capitalize on distributed computing innovations that leverage the cloud for greater design flexibility and availability. Smith: You have written that you see Moore’s Law accelerating. How does ML fit into this? Teng: We see the rapid adoption of new process technologies as the biggest trend surrounding Moore’s Law right now. ML technology in EDA will help speed tool certification processes, process design kit (PDK) development and other deliverables aimed at creating and improving customer support through all stages of the process lifecycle. This is a virtuous circle, and it’s expanding beyond hardware design and optimization to also include software. Today’s ML functionality works on the abstraction of register transfer level (RTL), optimizing the implementation and verification flows. ML will soon enable use of a higher abstraction of describing the target systems, exploring architectural options and optimizing across hardware and software partitioning. Smith: What advice would you give engineering students who are studying ML with the goal of becoming an electrical engineer? Teng: With the rapid pace of technology development, things are changing constantly. I’d absolutely encourage students to look at ML because ML isn’t going away — its growth is only going to accelerate from here. I’d also suggest that students look more broadly at computational mathematics because that’s foundational for ML. There are many, many opportunities to apply ML to real-world applications that will make a significant impact when it comes to optimizing computational software. Most important, students should explore and have fun while doing it. About Chin-Chi Teng Chin-Chi Teng has served as Senior Vice President and General Manager of the Digital and Signoff Group (DSG) since 2018. Prior to this role, Teng held senior leadership positions in research and development in digital implementation. Teng joined Cadence in 2002 via the acquisition of Silicon Perspective Corporation and subsequently led various research and development groups. He brought deep technical knowledge and more than 20 years of industry and academic experience to his role as leader of the IC Digital group. Teng holds a BS in electrical engineering from the National Taiwan University and an MS and Ph.D. in electrical and computer engineering from the University of Illinois at Urbana-Champaign. He holds seven patents and has written many EDA papers, several deep learning papers, and the book Electrothermal Analysis of VLSI Systems. Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community.

Alameda, Calif.-based Verific Design Automation, a member of the ESD Alliance, made its name in the electronic system design and semiconductor industry supporting companies ranging from startups to billion-dollar industry leaders such as Synopsys, Cadence, Siemens EDA, Xilinx, Microchip, NVidia, Infineon, Qualcomm, Renesas and Samsung. Its software is used as the front end to design automation tools such as synthesis, simulation, debug, and formal verification. I spoke with Verific president and COO Michiel Ligthart about homegrown and open-source EDA tools and other recent trends in chip design. Smith: What trends are you seeing in chip design? Ligthart: Semiconductor companies are starting to build a portfolio of intellectual property, including homegrown electronic design automation (EDA) tools, that they want to keep secure and differentiated from their competitors. The increased interest in internally developed and supported EDA tools is a trend we started to see about two years ago. It’s not simulation, synthesis or place and route (P R). Instead, it’s pieces of a chip design flow optimized for a company’s specific needs. In the past, a semiconductor company would either standardize on one EDA company’s chip design flow or mix and match best-in-class tools from different vendors. The common denominator was that they used off-the-shelf products. If they had a specific requirement, they went to the EDA provider for assistance. In today’s competitive landscape, semiconductor companies are figuring out ways to diversify themselves and their design flow became a way to do so. They may not build their own P R tool, but they will look at building their own power domain approach, for example. Is this a widespread trend? It could be. We hear about it within end-user applications ranging from 5G and AI to data center processors and there are probably others we don’t hear about. Power optimization is an example of the kind of specific internal need being addressed. Smith: What are your thoughts about open-source EDA tools? Ligthart: Our industry supports open source already with language reference manuals (LRMs) for VHDL, SystemVerilog, Unified Power Format (UPF) and the RISC-V Instruction Set. The LRMs and the instruction set are free. Moving to the development of actual tools becomes a question of who will implement, support and maintain the tools. Implementation is expensive. The Big Three (Cadence, Siemens EDA and Synopsys) invest about 35 to 40% of top-line revenue into R D. For smaller EDA companies, this number is even higher. The industry may come up with a business model that will have open-source components as well as a way to fairly reimburse companies that make these tools freely available. I have not seen it yet. Smith: Business Insider reports that Verilog HDL is among the top 10 tech skills that companies are desperate for their employees to learn right. Does Verific get asked about Verilog training? Ligthart: No. Our customers are experienced users. Nonetheless, it was great to read that article and it suggests the semiconductor industry is healthy, growing and hiring talented engineers. Smith: If an entrepreneur asked you for advice about starting an EDA or IP company, what advice would you provide? Ligthart: I would tell the entrepreneur to focus on the problem the startup is solving. Stick to the company’s core competency and try not to build in-house what can be purchased from a reputable supplier. In the end, it will save time and jump-start the development effort, and the engineering budget can be allocated to the startup’s core competency. The external supplier presumably has years of product validation, which brings a major QA gain. About Michiel Ligthart Michiel Ligthart, president and COO of Verific Design Automation, has an extensive background in engineering, product marketing and general management. Prior to joining Verific, Ligthart was vice president and general manager of West Coast operations for Theseus Logic, a startup in asynchronous logic. Before that, he spent eight years with Exemplar Logic in engineering and marketing roles. Ligthart started his career with Philips Research Labs in California and was a visiting scholar at the Center for Integrated Systems at Stanford University. He has a Master of Science degree in Electrical Engineering from Delft University of Technology, the Netherlands. Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community.

In the span of a few short months earlier this year, Mentor Graphics became Siemens EDA and introduced a suite of integrated hardware-assisted verification tools, the first product launch under the new Siemens EDA brand. Jean-Marie Brunet, senior director of marketing, product management and product engineering at Siemens EDA, orchestrated the launch and connected with me for a discussion about the chip design verification space. As he pointed out, verification and validation of systems is a fast-growing and important market segment to the electronic system design ecosystem. Smith: What trends do you see in chip design? What is driving these trends? Brunet: Chip verification costs continue to grow faster than design costs because of factors such as increasing design complexity, rising computing power, surging I/O traffic activity, increasing energy consumption and the widespread use of peripherals. These dynamics are being driven by new data center networking, communications/5G, autonomous driving, artificial intelligence (AI) and machine learning (ML), and storage applications. These trends also indicate the need for more powerful verification tools and expanded verification objectives that include power and performance analysis. Hardware-assisted verification tools are perfect for meeting these demands. Smith: Chip design verification consumes the most time in a project cycle. Why is this so? Brunet: The verification of designs reaching multi-billion gates and supported by voluminous software stacks is fraught with challenges. To exhaustively check every possible state in a billion-gate design with simulation alone would require up to trillions of verification cycles. That’s why hardware-assisted verification is one of the fastest-growing technologies in EDA. Given the complexity of today’s SoC design, it’s no surprise that verification is the largest undertaking in the entire project design cycle, consuming more than 50% of it. It also has the greatest impact on quality, cost and schedule because it prevents designs from failing at first silicon. While a respin of a large design taped out at a node below 10 nanometers could cost more than $10 million, delaying delivery of a new product for a few months in a highly competitive market may cost hundreds of millions of dollars. Smith: What other challenges do engineers face trying to verify a chip design will work as intended? Brunet: Verifying an SoC design is a massive undertaking and, in parallel, verification teams are trying to streamline and optimize verification cycles. SoC design groups are tasked with completing full system-level verification prior to creating production masks by thoroughly vetting all hardware blocks, interactions between those blocks, and the software developed for the end application before the chip is built. To alleviate this enormous pressure, they are starting to adopt a shift-left methodology for early functional verification as soon as individual blocks of a SoC design become available. It helps jump-start embedded software validation before full system validation is completed to save time and allow engineers to work in parallel, not serially. While it is an effective approach, it creates the need for a complete and integrated suite of hardware-assisted verification tools to verify and validate a design’s hardware and software components. Smith: How do you define hardware-assisted verification and how does it help solve these challenges? Brunet: A typical definition of hardware-assisted verification is special purpose hardware to accelerate verification. In other words, hardware emulation and FPGA prototyping. Hardware-assisted verification is a mandatory investment as single-die or multi-die chips get larger with more complexity and more interfaces, making hardware and software code integration critical early in the design cycle. Because software performance defines a chip’s success, the need to perform software workload-based analysis is acute, not just analysis of chip functionality, but also accurate performance and power consumption in the context of real-world applications. Hardware-assisted verification is the only option when hardware and software meet. By combining emulation, desktop FPGA prototyping boards and enterprise FPGA prototyping platforms to work on the same SoC design, a verification group can assemble a complete hardware-assisted verification system for thorough and exhaustive verification and validation. Smith: Where are the big opportunities for hardware-assisted verification? Brunet: New end-user applications are coming from computing and storage, AI/ML, 5G, networking and automotive. Recently released market data from the ESD Alliance shows that in 2020, hardware-assisted verification revenues exceeded $700 million. It is reasonable to assume that revenues of $1 billion will be within reach in the next few years given the amount of chip design activity at advanced nodes below 10nm. Smith: With the design/verification and manufacturing phases of the semiconductor supply chain more closely aligning, what role does hardware-assisted verification play? Brunet: Semiconductor manufacturing and the supply chain that supports it benefits greatly from the continued innovation in verification and validation tools and methodologies. With this innovation, designs are delivered to the manufacturing flow with a much greater chance of passing first silicon with success. This reduces friction in the semiconductor supply chain since IP and chips are available when anticipated. Hardware-assisted verification is a quick-moving, highly leveraged resource that helps a design and verification team to ensure chips are manufacturable and meet the functionality, power and performance requirements for the end-product application. Jean-Marie Brunet is the senior director of product management and engineering for the Scalable Verification Solutions Division at Siemens EDA. He has served for over 20 years in application engineering, marketing, and management roles in the EDA industry, and has held IC design and design management positions at STMicroelectronics, Cadence, and Micron, among other companies. Jean-Marie holds a Master's degree in Electrical Engineering from I.S.E.N Electronic Engineering School in Lille, France. Jean-Marie Brunet can be reached at [email protected]. About Bob Smith Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community. He is responsible for the management and operations of the ESD Alliance, an international association of companies providing goods and services throughout the semiconductor design ecosystem.

Emerging applications powered by 5G and artificial intelligence (AI) are expected to be a boon to the semiconductor industry, but only once chipmakers overcome a key challenge: Architecting chips that meet the exacting performance, power consumption, size and cost requirements of devices for mid- to high-end applications. One technology – heterogeneous integration – promises to meet these demands and help drive future leaps in semiconductor innovation in the post-Moore era. To help the industry better grasp the technology challenges and business opportunities associated with deploying highly integrated chip and packaging technologies, SEMI and AI on Chip Taiwan Alliance recently gathered industry leaders from organizations including ASE, Unimicron, Dialog Semiconductor, Cadence and AITA to discuss technology trends and the vital importance of building a cross-industry exchange platform to advance next-generation manufacturing processes critical to heterogeneous integration. Following are key takeaways from the forum, Heterogeneous Integration Enables 5G and AI. Overcoming Heterogeneous Integration Technology Challenges Key to Advances in Taiwan High-End Semiconductor Manufacturing The introduction of the Heterogeneous Integration Roadmap (HIR) by the International Technology Roadmap for Semiconductors team in 2016 was an important first step, Dr. C.P. Hung, Vice President of ASE Group, noted in his opening remarks. The HIR is designed to stimulate pre-competitive collaboration to advance heterogeneous integration technology development and accelerate electronics innovation. The roadmap provides a long-term vision for the electronics industry, identifying future technology requirements and potential solutions. Today, the HIR working group focuses on high-performance computing (HPC), 5G and other leading-edge technologies.Dr. Hung predicted that heterogenous integration will reshape traditional collaborations between the semiconductor ecosystem and supply chain in order to clear I/O bottlenecks that hamstring high-performance applications. The retooled industry connections will also need to enable high I/O pin counts, ultra-thin devices, and high-frequency signal shields. In an important step forward, the chip industry today is developing a platform that enhances wafer-level advanced packaging services and deepens cooperation with Oversea Assembly and Testing (OSAT) and substrate supply chain partners. Overcoming the current limits of IC substrates – the connection between IC chips the PCB – is one key for heterogeneous integration technology to flourish, said Dr. Yu-Hua Chen, Vice President, Carrier SBU, RD Division of Unimicron. He noted that the industry must tackle limits to PCB thickness, substrate density, fine pitch and automation to meet the needs of high-end packaging customers. Another barrier the industry must be surmounted is to make the currently inscrutable confidentiality requirements for patents of foreign materials – key to improving chip yields – easier to access and understand for substrate engineers. Chen said partnerships across the entire industry will be necessary to break through this and other technology breakthroughs. Supply Chain and Cross-Border Ecosystem to Strengthen Partnerships for Further DevelopmentTaiwan has long invested heavily in advancing semiconductor manufacturing and application engineering technologies to become a top global chipmaking hub and, in the process, has been behind significant leaps in optimizing chip functionality, said Leroy Liu, General Manager, Asia Headquarters, of Dialog Semiconductor (Germany). With its semiconductor manufacturing prowess, Taiwan can also play a central role in maturing advanced heterogeneous integration packaging technology while managing development costs by partnering with its international supply chain community to overcome technical challenges more effectively, Liu said. The region can also help forge partnerships, even among competitors, to build the ecosystem essential for heterogeneous integration technology to shine.EDA tools will be critical in understanding and resolving heterogeneous integration technical issues since IC substrate, packaging and chip design all pose interdisciplinary engineering challenges, said Julian Sun, Product Marketing Director at Cadence. To help the industry navigate these challenges, Cadence has launched intelligent system design products – solutions that address a wide range of design problems with semiconductor nanometers, micrometers on packaging and testing, and PCB level micro/millimeters to Pin/Pitch, I/O models, and thermals and electricity. By supporting various technical designs, Cadence helps customers shorten the design cycle to strengthen design quality and reduce costs.Sun also pointed to the vital importance of overcoming the significant challenge of designing silicon interposers for heterogeneous integration. Today’s EDA tools are capable of optimizing the design of complex structures including 5GAiP and HBM and are instrumental in aiding Taiwan’s semiconductor ecosystem players to quickly adapt to shifts in the evolving heterogeneous integration market.Heterogeneous Integration Enables 5G and AI speakers (L-R): Julian Sun, Product Marketing Director at Cadence, Dr. Yu-Hua Chen, Vice President, Carrier SBU, RD Division of Unimicron, Dr. C.P. Hung, Vice President of ASE Group, Leroy Liu, General Manager, Asia Headquarters, of Dialog Semiconductor (Germany), Dr. Shih-Chieh Chang, AITA Executive Secretary Designing AI chips is particularly difficult as semiconductor makers struggle with high costs and low yields, said Dr. Shih-Chieh Chang, AITA’s Executive Secretary. That’s why the chip industry now uses FPGAs for small-volume production of AI chips, which makes it easier to improve manufacturing yield through redundant design. For its part, AITA has formed a special interest group (SIG) to help form connections among the chip industry, academia and research institutes. The association’s goal is to build a platform for mass production of AI chips.To get involved in SEMI Taiwan Heterogeneous Integration related events, please contact Ula Huang, outreach senior specialist, at [email protected] Fang is a coordinator and Ashley Huang is a specialist in marketing and public relations at SEMI Taiwan.

Would you buy your next hotdog in parts, from un-coordinated suppliers? For example: Get the bun from a baker, the sausage from a butcher, mustard and/or ketchup and veggies from the nearest supermarket? If yes, you may find the sausage being too small, the veggies too big for the bun, and, when you finally finished adding mustard/ketchup and start eating, you may “enjoy” a cold sausage on a soggy bun!This “hotdog example” is just a very simple way to highlight the advantages of a well-coordinated semiconductor supply chain. What may be a few dollars and cents wasted in this hotdog purchase, can become millions of dollars lost to delays and inefficiencies during the roll-out of a new electronic system.Complexity is Increasing the ChallengeThe very innovative semiconductor industry is continuing to develop more complete and complex building blocks for electronic system solutions, with the intent of making our customers’ lives easier. However, every new technology takes increasingly more time for technical and business interfaces to mature before all the semiconductor supply chain members can serve customers in a smooth, efficient and cost-effective manner. In particular, coordination between design and manufacturing has always turned out to be in the critical path.SEMI, the manufacturers’ trade organization, and the Electronic System Design (ESD) Alliance, representing electronic design automation (EDA) tools vendors, developers of intellectual property (IP = ready-made building blocks for ICs) and IC design service providers, both recognized these challenges. Late in 2018, these two industry organizations decided to jointly address this painful, costly and often a very frustrating, yet critical path and became Strategic Association Partners, The goal is to establish a well-coordinated semiconductor supply chain.To make the value propositions of this partnership highly visible and demonstrate the first joint accomplishments, SEMI’s well-known SEMICON West conference and, in its first year, ES Design West, will be conveniently co-located in San Francisco’s Moscone Center from July 9 to 11, 2019. The synchronized schedules and geographic proximity of these events not only outlines the multi-faceted interdependence of manufacturing and design but encourages and enables conference attendees to do, what previously would have been viewed as “forming cross-border relationships.” It’s a new word now — please join the path to success and expand your network!Navigating SEMICON West and ES Design WestJust in case you are not yet planning to come to San Francisco early July, please check the Agendas-at-a-Glance for SEMICON West and ES Design West, to see how broad and valuable these parallel conferences are for your business. In addition, every customer, partner and semiconductor industry supplier can, from July 9 –11, walk from one conference section to the other, arrange face-to-face meetings, in dedicated meeting rooms, with representatives from both camps and discuss, from the first project planning step to the final production ramp-up, the many topics that need to be coordinated across parts or the entire supply chain to minimize delays and/or cost over-runs.Who Will Lead the Discussions?Conference attendees can, in addition to meeting many important supply chain partners face-to-face, hear about the latest technologies and market trends from key executives in our industry. Featured speakers are: David Pellerin, Head of Global Business Development, Amazon Web Services Lisa Su, President, and CEO, AMD Gary Dickerson, President, and CEO, Applied Materials Laurent Le Faucheur, Principal Engineer, Digital Signal Processing and Machine Learning, Arm, Ltd. Renee St. Amant, Ph.D., Research Engineer in Emerging Technologies and US Innovator of the Year, ARM Dean Kamen, President DEKA Research Development, Founder First and First Global Jeffrey Welser, Ph.D., Vice President and Lab Director, IBM Research-Almaden Dean Drako, President and CEO, IC Manage, Inc. Oreste Donzella, Sr. VP Chief Marketing Officer, KLA Corporation Prakash Narain, President, and CEO, Real Intent, Inc. Aart de Geus, Chairman, and Co-CEO, Synopsys, Inc. Manish Pandy, Fellow, Synopsys, Inc. Nate Baxter, General Manager, Development and Production Group, TEL US Like in previous years, SEMICON West and ES Design West offer a range of special features, addressing Smart Manufacturing, Smart Transportation, Smart MedTech and Smart Workforce development in dedicated pavilions as well as an AI Design Forum. Also, the many exhibitors from both camps will give conference attendees convenient opportunities to get to know new supply chain partners and/or refresh long-term business relationships. Search for the exhibitors you want to meet early July here. Questions to Ask for a Well-Coordinated Semiconductor Supply ChainIf I may, I would like to ask my many friends in the manufacturing camp to spend some time in the ES Design West section and ask the exhibitors a few questions, like: What can you do to get me to profit faster? To reduce development and unit cost? To improve yield, product quality, and reliability? When can you visit my team to discuss how your company can contribute to our goals?Vice versa, I would like to encourage my friends in the design camp to spend time in the SEMICON West section and ask exhibitors what their companies offer. When talking to manufacturers of IC, passive components or circuit boards, assembly and test houses, please ask very specific questions like: How can we help you reduce iterations between you and your customers? How can we help to improve IC test programs? How can we increase the throughput of your manufacturing equipment? How can we apply machine learning (ML) and Artificial Intelligence (AI) to minimize equipment downtime, improve yields and/or shorten production ramp-up?I can assure you that you’ll not only win great friends “across the border” but will be very impressed by the expertise you’ll find in the other camp and the willingness for and benefits of cross-border cooperation.I look forward to meeting you at SEMICON West and ES Design West. Also, if your schedule allows, mark your calendars for the June 12 MEPTEC Luncheon at SEMI in Milpitas, June 18 for the GSA’s Silicon Summit in Santa Clara and June 25 to 27 for the IMAPS SiP Conference in Monterey, CA. Hope to see you at one or all of these important events!Article originally published in 3D InCites. Herb Reiter is president of eda 2 asic Consulting.

Constant coverage of an invigorating topic like machine intelligence in the media often urges us to consider its use in EDA technology. As is often the case, there are many myths and falsehoods that consume our time and effort when trying to apply machine intelligence to EDA. This article aims to uncover the myths and to provide helpful advice on applying machine intelligence to your EDA project or product.Value PropositionFirst, there needs to be a clear value proposition for adding machine intelligence to an EDA product. Using machine intelligence to create a me-too product adds no value. EDA customers are too busy to understand or care about an EDA tool’s underlying technology. They just want to use the tool and get results. If the tool delivers value, if it delivers tangible benefits, then they’ll use it. Otherwise, they won’t.Currently, EDA tool developers are already experimenting with AI and machine intelligence without considering this fundamental truth – without a higher-end objective. AI must deliver something better or new, whether a speed advantage, a performance advantage, new features, new insights, or perhaps even something pleasantly surprising. Before you write a single line of AI-enhanced code, you need to clearly understand how AI will enhance the product. What is the value proposition?Use ModelThere’s a major barrier to customer adoption of AI and machine intelligence technology for EDA tools: EDA users are averse to make decisions based on probabilistic results. Instead, half a century of EDA tool use has conditioned them to expect deterministic outcomes from their tools.Back in 2003, a prominent visionary and EDA investor was quoted in an interview, saying: “If I open my eyes five years from now, all static analysis in VLSI will be statistical.” Many EDA luminaries have been proven wrong over time for betting that EDA users will accept statistical results. As enthusiastic as I am about using machine intelligence to improve EDA tools, I must urge caution based on the history of EDA failures that employed a probabilistic use model. Decision-makers and EDA tool users want to see deterministic answers to questions about yield or slack, not probabilistic ones.Our experiences at Paripath in developing the PASER (Paripath Accelerated Simulation Environment) tool also bear this out. We discovered that delivering results 50x faster but with 92% accuracy was simply not good enough for end users. EDA users only started to use PASER when its answers became 98+% accurate. To be adopted in the production flow, the tool had to deliver 99% accuracy.Data EngineeringThere are specific ways to achieve these accuracy goals. The first is data engineering. Machine intelligence is a new approach to EDA tool development and it needs to be trained on a data set. If the data is poor or incomplete, training will create an inaccurate model. Fundamental software-development rules still apply. Garbage in, garbage out.Without good training data, there’s no way for you to build good neural-network models. If you train a model with garbage data, you’ll get a garbage model. You must cleanse the data before you use it for training. Otherwise, the model will draw inaccurate conclusions and customers will not use your tool. The model is not to blame here. The model’s not wrong. The problem lies in poor data engineering, poor data cleansing, and a lack of discipline to prepare input data.High DimensionalityNext, machine intelligence has a unique ability to quickly solve problems of high dimensionality. Pure EDA problems often have high dimensionality. Over the years, EDA developers have perfected the art of segmenting the problems into sequencing solutions with lower dimension. Machine intelligence technology can handle problems with thousands of dimensions, but you need to be careful when tackling problems that have high dimensionality. Too many dimensions can produce confused or inaccurate results with AI and deep-learning technology.It helps to visualize the problem and to analyze the data set before using the data to train an AI-enhanced EDA tool. Several visualization methods can help. For example, t-SNE (t-Distributed Stochastic Neighbor Embedding) lets you reduce a data set’s dimensionality from a very large number to a much lower number. Figure 1 shows a high-dimension dataset with a dimensionality of 2000, which has been reduced to a low dimensionality of 3. Figure 1: Visualizing the Data Set with Lower Dimensionality Reducing the dimensionality of a data set to 3 using t-SNE and visualization allows you to quickly see whether the data set defines an easy or a difficult problem. If the problem is difficult, you’ll likely need to lower the problem’s and the data set’s dimensionality before using the data to train a neural network.Technology SelectionOne factor that determines whether it will be easy or difficult to incorporate machine intelligence into your EDA tool is your choice of AI development tools. AI researchers have developed a long list of frameworks, libraries, and languages that they use to develop AI and machine-learning software. Frameworks and libraries such as TensorFlow, Caffe and MXNet are most popular for developing deep-learning models.However, these tools are not yet popular with the EDA development community. The languages of choice in the EDA community are traditionally C and C++ for development and Tcl for prototyping and creating user interfaces. The rest of the software world has moved on to newer development languages such as Python, Java, R, and such. Moreover, machine-learning development segments into two distinct processes: training (i.e. generating the model) and inference (i.e. using the model).Another question to consider is where to generate the model – at the vendor site or the customer site?Consequently, fitting AI and deep-learning development into EDA development environments can feel like fitting a square peg into a round hole. You may need to create corners in your hole.EDA is a very small player in the overall software market. Relatively few software developers are familiar with writing EDA tools. It’s best to select AI and deep-learning development tools that can provide some sort of interface that’s compatible with EDA’s development tools of choice. Some AI frameworks have lower-level C and C++ interface layers that provide a familiar entry point for experienced EDA developers.At Paripath, we chose TensorFlow for exactly this reason. TensorFlow has a lower-level C/C++ interface. Although the resulting development path becomes a longer one using this approach, it’s a more familiar path for EDA developers and therefore it’s a path that can ultimately lead your EDA development team to success. An elaborate study of comparing these frameworks has been published in the book Machine Intelligence in Design Automation.Integration into Legacy SystemsWhen you understand the value that you expect machine intelligence to add to your new EDA tool, when you’ve cleansed and then analyzed the data set, and when you have selected an appropriate set of development tools, you’re finally ready to add machine intelligence to your EDA development. There are two use models for AI-enhanced EDA tools. The first uses a trained model to guide the EDA tool’s decision-making. In this use case, the trained neural network doesn’t change. The software’s accuracy doesn’t improve with use unless the company that developed the EDA tool retrains the underlying neural network. This use case follows the familiar, existing use case associated with EDA tools developed using deterministic algorithms.For the second use case, the end user is able to retrain the underlying neural network, which allows the EDA tool to produce better, more accurate results over time. This use case produces a win/win situation because end users are able to hone their tools and improve them over time, without help from the EDA tool vendor’s application engineers. If the retrained models are also sent back to the EDA developer for incorporation into newer versions of the tool, all users benefit from other users’ training data.It’s not clear how you’d support this second use case in the current EDA business environment where most data sets are proprietary and are carefully guarded. Most large EDA tool customers want to keep their data in house under tight control. Even with this somewhat restrictive situation, however, EDA tools benefit from the incorporation of machine intelligence because each EDA tool customer can customize the tool and improve its results.Machine intelligence has much to add to EDA tools’ capabilities. Only time will tell if the customers want and will accept these new capabilities. Rohit Sharma, founder and CEO of Paripath Inc., is an engineer, author and entrepreneur. He has published many papers in international conferences and journals. He has contributed to electronic design automation domain for over 20 years learning, improvising and designing solutions. He is passionate about many technical topics including machine learning, analysis, characterization, and modeling. It led him to architect guna - an advanced characterization software for modern nodes. Sharma has written a book titled “Machine Intelligence for Design Automation.” You can download code examples and other information here.Note from SEMI-ESD Alliance: ESD Alliance’s Interoperability Committee brings together the industry to discuss interoperability. By focusing the efforts of the electronic system design community onto key compute operating systems, the Interoperability Committee seeks to define a stable, interoperable environment for tools and streamline the resources required to support these environments. The EDA Industry OS Roadmap presents guidelines to EDA vendors and customers for compute platforms to target for design starts. Learn more and view the OS Roadmap overview at our website.

I really don’t know clouds at all. – Joni MitchellThe semiconductor industry is finally on the cusp of joining the cloud revolution. The cloud has offered the promise of greatly expanded resources for years, but adoption has been slow due to lingering concerns. The biggest contributing factor for the concern over moving from on-premise EDA servers to cloud-based servers is, surprisingly, the rise of third-party IP. In the old days, if you were developing 100 percent of your own IP, and if you put that IP on a public cloud, and it somehow leaked out, well shame on you. That would certainly be bad for business. It might hurt your reputation a bit. But these days, with so much third-party IP being embedded into chips, if that third-party IP leaks out, that’s a lawsuit-fest in the making.Consequently, semiconductor companies now have even more incentive to protect IP with advanced security. Surprisingly, cloud-based security is far, far better than on-premise security. Why? Because keeping customers’ data secure is the central mission of cloud service suppliers, so they’ve developed a rich set of security tools to protect the data that’s entrusted to them by their clients. In many ways, you can maintain much better security in the cloud than you can with on-premise tools. Image credit: Markus Spiske temporausch.com from Pexels Amazon Web Services: Exemplifying the benefits of cloud computingTake Amazon Web Services (AWS) as an example. (Note: AWS is not the only vendor in the cloud space, but it’s one I’m very familiar with.)AWS has developed the concept of security groups – firewalls that you throw up around any network interface to allow only specific traffic into that secured network. You can do that for just one server or for a fleet of servers, in just seconds. Most on-premise server networks won’t let you work that quickly, or as easily, or with such fine control because most such networks lack the security tools to do this.In addition, AWS allows you to encrypt every bit of data stored on and flowing through its cloud-based storage systems. You can encrypt data at rest in on-premise storage but it’s a lot harder to encrypt data flying through the on-premise network. Amazon’s Elastic File System (EFS), a managed NFS file service, offers the ability to easily encrypt NFS traffic on the wire, a difficult feat at best with an on-premise solution.AWS built-in encryption key-management service can rotate encryption keys automatically. The cloud also allows you to have key policies that are easy to implement and maintain.Internal corporate networks rely heavily on perimeter firewalls for security. Perimeter defense just cannot deliver sufficient security against determined hackers and everyone realizes this. We’ve built big, open, on-premise networks that are just not well-suited to implementing adequate security protocols. Trying to retrofit these network architectures with additional security is time-consuming and costly, and it hurts engineering productivity. Moving to the cloud gives you a greenfield opportunity to right some of the wrongs of the past.Continuing with AWS as an example, here are some additional advantages of EDA in the cloud: AWS provides physical security that’s far above and beyond on-premise security. It doesn’t publish the physical locations of its data centers. It also has professional security staff 24/7, keycard access, and additional security features that far exceed typical on-premise physical security. AWS automatically manages security patches and access controls for their managed services such as database services. AWS gives you plenty of security tools to automate security processes, audits, and so forth to protect your data. AWS gives you so much flexibility that you can get yourself in trouble in you are not careful. If you want, you can create the same sorts of security holes that already exist with on-premise networks. You shouldn’t of course, but you can if you’re not thoughtful about things. You just need to hire the right people to implement and maintain your cloud security.Here are five very big differences between AWS (cloud-based) and on-premise server networking: Elasticity: Cloud-based systems enable you to scale up in minutes. That ability has pluses and minuses depending on how disciplined you are. On the plus side, you can quickly grow your EDA infrastructure as big as you want and then shrink it back down when you no longer need the additional capacity. All you need to do is tell the cloud service that you need more capacity and it will bring that extra capacity online for you in minutes – and will charge you for it. (That’s the minus side.) When you’re done, you can turn off the extra capacity (and stop paying for it) with the same speed. If you want to provision more EDA capacity for your on-premise network, you’ll need to beg, borrow, or steal existing capacity from someone else on your network, or you can order more servers, get the vendor to build and ship them, install them in your server room, provision them, and bring them online. That will take months. Fault tolerance: On-premise networks rely on large, monolithic service architectures, which saddle EDA vendors with more than 30 years of technical debt. The cloud operates on a different model, one that’s based on containers and microservices. This is inherently a redundant, fault-tolerant computing model if you write your code correctly. The difference between redundancy in the cloud and in on-premise networks is night and day. There’s no comparison. No private networks can match the available and growing redundancy of cloud systems, which have redundant servers inside of a data center and redundant data centers in multiple, worldwide geographic locations, which protects your data from natural and man-made disasters. Network segmentation: Many semiconductor developers have several design centers distributed around the world and there may be IP in use on a project that cannot be shared with certain geographic locations either by law or by contract. Cloud networks are already set up with automated tools for network segmentation that can enforce geography-specific rules through VPCs (Virtual Private Clouds), which are easy to set up. VPCs allow you to set up subnets with restrictions based on routing tables so that IP management and control become highly automated. Removal of single points of failure: The typical EDA grid configuration has several built-in single points of failure. For example, a central job dispatcher generally runs on one single node. If that node dies, all EDA work halts. The same is true for EDA license servers and for configuration-management and version-control servers. Again, because cloud networks are based on the microservices concept, the cloud simply doesn’t need to have the same single-point-of-failure vulnerabilities that on-premise networks have. On-premise networksTo get these same advantages with on-premise networks, the grid architecture must fundamentally be changed, starting with the replacement of NFS. EDA systems need to replace huge, monolithic file systems specifically developed for EDA with object storage. That's a tall order – one that requires the rewriting of fundamental assumptions that serve as EDA software’s foundation.In the 1980s, 1990s, and early 2000s, small EDA startups appeared to fill gaps in the offerings of the large EDA players. If they succeeded and grew, they’d eventually be gobbled up by a larger EDA vendor. That flowering of EDA startups seems to have damped down. The market has really matured.Next wave of EDA startups to offer cloud-first toolsGoing forward, I expect the next wave of EDA startups will be offering cloud-first tools that are not burdened by three decades of technical debt. They’ll be able to architect their tools specifically for the cloud.We’re starting to see this happen. For example, Metrics, a Canadian EDA startup, offers a pay-by-the-minute, cloud-based simulator and verification manager. Although one job on one cloud server might run slower than a monolithic simulator running an on-premise server, Metrics has architected its tools so that you can throw more servers at the problem, allowing you to run all of your jobs at once. Here, multiple simulation jobs running concurrently on multiple servers will ultimately finish faster than running the jobs serially on one slightly faster on-premise simulator.That’s the kind of innovation that we’re going to see. That’s the future of EDA.Derek Magill is executive director and president at HPC Pros. Derek has 20 years of experience supporting semiconductor engineering functions. His main focus has been in system architecture and technical management, but over the years he has been involved with technologies such as EDA licensing, ClearCase, HPC architecture, IP management and engineering software support. Derek spent 15 years at Texas Instruments in various technical and managerial roles. He is currently a senior manager, IT at Qualcomm managing the Global License Infrastructure team as well as the lead technical architect for the company's engineering cloud activities. The Electronic System Design (ESD) Alliance, a SEMI Strategic Association Partner, is the central voice to communicate and promote the value of the semiconductor design ecosystem as a vital component of the global electronics industry. As an international association of companies providing goods and services throughout the semiconductor design ecosystem, it provides a forum to address technical, marketing, economic and legislative issues affecting the entire industry. The ESD Alliance also stages events that promote networking, learning and collaboration among member companies. To learn more about the ESD Alliance and how to join the group, visit www.esd-alliance.org or contact Bob Smith at [email protected].