electronics

Maheen Hamid is co-founder of electronic design automation company Breker Verification Systems and a member of both the ESD Alliance Governing Council and the SEMI North America Advisory Board. I spoke with Hamid about the EDA industry and her perspectives on the sector where electronics begins.

The FLEX Conference, held again this year in conjunction with SEMICON West 2023, provided numerous examples of continued developments in flexible, printed, and flexible hybrid electronics technologies applied to sensing, robotics, communications, and other applications.

To help the semiconductor industry keep pace with increasing chip performance and cost demands, SEMI has formed the Advanced Packaging Heterogeneous Integration (APHI) Technology Community as part of our longstanding support of advanced packaging innovation through events and standards development. 

The more than 2,500 SEMI member companies worldwide advance the business of electronics design and manufacturing. SEMI members are responsible for the innovations in materials, design, equipment, software, devices, and services that enable smarter, faster, and more powerful electronic products.

The increasing complexity of IC manufacturing poses a number of challenges including the mask data preparation required to enable technology improvements such as multi-beam (MB) mask writers and extreme ultraviolet (EUV) lithography. Thiago Figueiro, VP of Sales & Marketing of Aselta weighs in.

More than 4,000 participants convened in person at the four-day SEMICON Europa Expo in Munich, November 16-19. Attendees gathered at the Executive Forum for insights into the latest trends in the semiconductor industry and heartily welcomed the long-awaited return to in-person networking.

China’s semiconductor sector has exploded to become one of the largest in the world and match the region’s prominence as the biggest consumer of chips. From 2015 to 2020 alone, revenue of China’s integrated circuit (IC) industry expanded at a rapid clip of 20% CAGR (RMB) to $128 billion.

Throughout the current millennium, System-on-Chip (SoC) has been the gold standard for optimizing performance and cost of complete electronic systems. By incorporating practically all the phone’s digital plus analog capabilities onto a single, giant chip, the mobile phone processor serves as a near-perfect exemplar of SoC. But today’s leading integrated circuits (IC) are pushing up against the upper limit of a chip’s size which is limited by the manufacturing equipment’s optical reticle size. This has proven difficult to increase and has grown only slowly over the years. Yet market pressure continues unabated for bigger, more capable electronic systems with more integrated memory, more digital logic, and more analog/mixed signal circuitry. An emerging solution to this tension is 3D and 2.5D multi-die chip assemblies – often referred to as 3D-IC. The key technology breakthrough of 3D-IC is that it makes it possible to spread a system out over multiple, smaller chips that are then assembled close together and interconnected with high-speed, low-power interconnect technologies. By abandoning the need to integrate an entire system on a single SoC and instead allowing it to be disaggregated over multiple chips, 3D-IC enables Moore’s Law to break through the reticle size barrier, improves yield by shrinking the size of individual chips, and makes it possible to mix different process technologies optimized for each function. The Four Engines Driving Semiconductor Design The road forward is not without its challenges, however, and we are seeing design companies making significant efforts to adapt and come to grips with the following four technology and market drivers: The requirement for concurrent multiphysics analysis to ensure reliable and efficient electronic systems The blurring of the lines between silicon and system The need for open and inclusive multiphysics platforms that interoperate with the multitude of design platforms The need for, and value of, bespoke silicon for hyperscalers and system companies Blurring of Silicon and System Design The advent of 3D-IC opens up new horizons for solutions that can be implemented in silicon. But it also forces a closer integration between two distinct technology markets that have co-existed symbiotically for many decades: IC design and printed circuit board (PCB) design. These markets use different tools, different data formats, different manufacturing back-ends, operate at different computational and geometric scales, and focus on different physical concerns. Yet, 3D-ICs share many aspects of both markets: They include monolithic chips but also board-like substrates to stitch the chips together. And in between the two disciplines is packaging, a completely different domain that is requiring companies to re-imagine their design capabilities and flows, as well as their organizational structure. Open, Extensible Multiphysics Platforms The siloed isolation of chip design from PCB design and package design means that each of these markets has developed insular data structures that are ill-suited to deal with the breadth of multiphysics analysis for 3D-IC design. Many different physical disciplines, including computational fluid dynamics, mechanical stress, and electromagnetic radiation, all need to work together based on open and extensible multiphysics platforms. These platforms must embrace the modern cloud compute paradigm and enable an ecosystem by allowing individual design platforms to connect for comprehensive multiphysics analysis. Bespoke Chips Today’s market-leading companies are heavily dependent on technology for their continued success and market differentiation. Everybody from online retailers to telecommunications to social networking companies and hyperscalers are moving away from off-the-shelf solutions and turning to custom-built silicon to give them an edge. Many of these companies are seeking to gain market share by leveraging proprietary AI/ML algorithms trained on their extensive troves of market data – but this requires huge amounts of compute power and specialized chips. Access to high-quality silicon solutions is vital in today’s world and the demand is for continually more complex and powerful electronics. 3D-IC an Inflection Point in Electronic Design To be sure, 3D-IC design is at an inflection point in electronic design and presents major challenges that are realigning the electronic design industry around this new reality. For more insights on this topic from a semiconductor industry leader, please view the Keynote Address 2.5D and 3D – The Road Ahead by Vicki Mitchell, VP Engineering, Arm Central Engineering Systems Group presented at the latest Ansys IDEAS Forum. And for an EDA perspective, please view Successful 2.5D and 3D Multi-die Silicon System Design Using Synopsys’ 3DIC Compiler and Ansys’ Multiphysics Analysis from Synopsys SNUG World 2021. About John Lee John Lee is general manager and vice president of the Ansys Electronics and Semiconductor Business Unit. Lee co-founded and served as CEO of Gear Design Solutions (now Ansys), developer of the first purpose-built big data platform for integrated circuit design. He cofounded two other startups (Mojave Design and Performance Signal Integrity), which successfully exited into companies now part of Synopsys. He holds undergraduate and graduate degrees from Carnegie Mellon University.

AEM Holdings Ltd, a Singapore-based multinational corporation, is listed in Forbes Asia’s 200 Best Under A Billion 2019 and 2020 spotlighting small and midsized companies in the Asia-Pacific region with sales under $1 billion. AEM clinched the Singapore Business Review Technology Excellence Award 2020 for Analytics-Semiconductor and the Singapore Business Awards Enterprise Award 2019/2020. These achievements are testament to AEM’s vision and innovation and the company’s contributions to the increasingly complex testing of chips in a rapidly evolving technological world. I spoke with AEM CEO Chandran Nair, a new Regional Advisory Board (RAB) member of SEMI Southeast Asia, about the company’s intelligent test and handling solutions, its role in digital transformation, the company’s key role in the smart manufacturing movement and the growth prospects for Singapore’s electronics sector. SEMI: AEM’s application-specific, intelligent system test and handling solutions for semiconductor and electronics companies serve the advanced computing, 5G and AI markets. How do you differentiate your solutions from those offered by competitors? Nair: A key differentiation for AEM is that we work closely with our customers to develop application-specific integrated test and handling solutions that meet their needs in a scalable manner from lab to production. We offer our customers customized, full-stack test and handling solutions that give them the agility to accelerate their delivery cycles and enhance product quality. Over the years, AEM has developed and acquired world-class technologies in instrumentation, test, automation, robotics, optical inspection, high-end thermal control, and software. These technology pillars, along with our deep know-how to customize test and handling solutions using the technology pillars as a platform, enable AEM to meet the fast-changing needs of our customers faced with the challenges of testing heterogeneous and complex devices. In addition to investing in technology, AEM has also invested in delivering application-specific solutions to meet customer demand. Our recently announced acquisition of CEI with its manufacturing capabilities in Vietnam and its specialization in low-volume, high-mix manufacturing increases our geographical reach and our ability to quickly turn application-specific test and handling solutions to be deployed. We have a unique and differentiated approach that enables our customers to test high-performance computing devices, automotive devices, and mobility devices with maximum test coverage, cost-effectively, in a manufacturing environment. Our experience in serving the high-performance computing market that traditionally drives advancements in thermal control also puts us at the forefront of delivering comprehensive thermal management, vision, and deep automation and test solutions for the computing, automotive, and mobility markets. AEM also has a strong instrumentation portfolio, including high-density digital instruments and mixed-signal and protocol-aware instrumentation that is well-suited for ATE solutions for SoC, high-power devices, and CMOS image sensors. Over the last few years, we have also established leadership positions in developing and deploying application-specific test solutions for MEMS devices and offering wafer and frame probing stations suitable for R D, wafer sort, and final test. We form strong partnerships with our customers, provide them with end-to-end support in product development, and take them through the entire life cycle process from concept to mass production. Chandran Nair and Goh Meng Klang, vice president of operations, at the AEM manufacturing site in Singapore. (Photo credit: AEM) SEMI: Digital transformation is powering strong growth of advanced computing, 5G and AI. Will AEM be expanding its AEM manufacturing plants in China, Malaysia and Singapore to meet rising demand for these technologies in the coming years? Nair: In regards to manufacturing, AEM currently has manufacturing facilities in Singapore, Malaysia, the U.S., Finland, and China. With our recently announced acquisition of CEI, we will add manufacturing capability in Vietnam and Indonesia. AEM will continue to expand manufacturing appropriately to give our customers cost-effective solutions while maintaining our proven track record of delivering on time and scaling rapidly in times of crises like the pandemic or geopolitical disruptions. As for advanced technologies, the three key factors that will bring the full potential of 5G to fruition are 1) cost-effective, high-powered processing devices at the edge, 2) easy access to high-bandwidth communications, and 3) cost-effective sensor technology. Semiconductors are the primary drivers of these three key success factors. As devices become more complex and our reliance on semiconductor-powered devices in all aspects of our lives deepens exponentially to include mission-critical applications, AEM’s role is to ensure that our customers' electronic and semiconductor devices are shipped thoroughly tested, safe to use, and highly reliable. It is imperative that, as a testing company, we find innovative ways to help our customers test their products with maximum coverage and minimum cost. To do this, we are focusing our R D efforts and investments to continue building on our key technology pillars to ensure that we stay ahead of the curve when it comes to test and handling solutions. We prepare our customers to test increasingly complex devices manufactured on the latest process node. SEMI: During your career you’ve driven projects in test and automation and more recently robotics solutions for ports, logistics warehouses and transport. With robotics and automation a key part of Industry 4.0, what role do AEM solutions play in powering the smart manufacturing movement? Nair: The smart manufacturing movement is powered by semiconductors, software and increasingly by artificial intelligence (AI). Test is at the heart of the process of ensuring that semiconductor and electronics devices reach the consumer well-tested for reliability. With our vision of enabling A Zero Failure World, AEM addresses the necessity for safe, highly reliable devices. The semiconductor companies themselves are adopting smart manufacturing methods. AEM’s tools are Industry 4.0-ready, and we continue to invest in machine learning and data analytics, which are integral to the future of test. Our tools are automated and feature embedded sensors to provide our customers with data about tool usage, the state of a machine’s health, and more. Our tools are connected to our customers’ manufacturing automation platforms. Additionally, we continue to invest in our ability to better slice and dice test data to understand trends and patterns to help our customers analyze data and make decisions faster. SEMI: You also have experience heading autonomous vehicle projects. With the COVID-19 pandemic hastening digital transformation, do you see an acceleration in the development of fully autonomous vehicles and smart manufacturing? Research and development efforts for autonomous vehicles (AV) continue at a fast pace worldwide. With shutdowns and restricted movement rules globally, the pandemic has hastened digital transformation in many ways. The delivery of goods and services is transforming, and AV will surely play a part, especially in secure environments for autonomous transport. The pandemic has accelerated the development of autonomous vehicles and smart manufacturing technology in automation-friendly environments like factories and ports. SEMI: At the recent Global Technology Summit hosted by SEMI, you spoke about testing innovations to meet the demands of highly complex devices. Please elaborate on innovative testing solutions versus traditional testing? Nair: AEM offers a disruptive and differentiated solution, one that is driving a paradigm shift to asynchronous, modular, highly parallel, smart testing solutions. ​ The traditional approach of ATEs to test increasingly complex devices on advanced nodes has reached a point of diminishing returns as it gets exponentially more expensive to increase test coverage to acceptable levels. Additionally, as devices get more complex and companies are rapidly adopting heterogeneous packaging technologies, the realization that System Level Test (SLT) is necessary is forcing a rethink of the entire test process. AEM’s provides asynchronous, modular, highly parallel test cell solutions that enable each test cell to run SLT, final test, or burn-in all in one system and its ability to handle hundreds of test cells independently with each test cell testing multiple devices. Our solutions suddenly make comprehensive testing of every complex device cost-effective. Freeing us from legacy ATE allows AEM to provide these innovative solutions to our customers. AEM engineering and manufacturing teams in Singapore at work on semiconductor test and handling systems for global deployment at world-class semiconductor facilities. (Photo credit: AEM) SEMI: Singapore seems to be in the sweet spot of digital transformation. Singapore’s industrial production grew 8.6% year-over-year in January 2021, an expansion driven mainly by a surge in sectors including electronics, and more growth is seen in the year ahead. Digital technologies such as 5G technology and cloud computing together with continued demand for work-from-home equipment is behind this growth. What are the growth prospects for the region’s electronics sector? Nair: Singapore is well-poised to benefit from the current digital transformation accelerated by the adoption of these technologies during the pandemic. Being a safe, well-governed country with strong IP protection, excellent infrastructure, and the rule of law, Singapore is in a great position to play a central role in cloud-based services, 5G, and the semiconductor industry. Singapore’s semiconductor sector output is at a record high, and the prospects for renewed growth in the region are very good. SEMI: As a new Regional Advisory Board member of SEMI Southeast Asia, how is your industry experience relevant to the scope of this role? What opportunities lie ahead for the region? Nair: I am honored to represent AEM in the SEMI’s Southeast Asia RAB. The SEMI RAB can influence policymakers with ideas and information on the current and future needs of the industry. I also believe that SEMI Southeast Asia can cultivate a strong innovative semiconductor ecosystem that helps regional and global growth. I look forward to working with other very experienced and accomplished board members. Bee Bee Ng is president of SEMI Southeast Asia.

As monolithic scaling slows down, the semiconductor industry is increasingly relying on advanced packaging technologies to extend Moore’s law through heterogeneous integration. Higher on-package bandwidth, improved yield resiliency and the need to integrate diverse IP from multiple foundries are driving demand for advanced packaging technologies that address these issues but introduce challenges of their own such as efficient power delivery to all the different domains in a heterogeneous system. SEMI spoke with Kaladhar Radhakrishnan, Intel Fellow at Intel, about heterogeneous system integration trends and new developments in the semiconductor industry. Radhakrishnan shared his views ahead of his keynote at the SEMI Connecting Heterogeneous Systems Summit, 1-3 September 2021, an online event. Join the summit to meet experts from Intel and other key industry influencers. Registration is open. SEMI: What is driving the adoption of electronics and semiconductor devices nowadays and why is the development of new and innovative technologies important? Radhakrishnan: We are living in an increasingly data-driven world where devices have become an integral part of our lives. A recent study estimated that in the United States alone, 13.6 connected devices per capita consume an average of 300 gigabytes worth of data every month. In the workplace, COVID-19 has driven fundamental business changes that has sped up the adoption of digital technologies such as virtual conferencing, remote work, and e-commerce. Organizations are realizing that a high-quality video conference can be an adequate substitute for many in-person meetings. As a result, businesses are accelerating the digital transformation in order to adapt and thrive in this new environment. Five decades of sustained exponential growth in semiconductor performance has conditioned the average digital consumer to expect more from their devices. However, there are some headwinds ahead as traditional scaling slows down and power density rises. Because consumers and businesses are now generating data at a faster rate than they can consume it, technologists need to scale compute, storage, and bandwidth even faster to keep pace. Without investments in research and development of new and innovative technologies to address these challenges, the full potential of this data will go unrealized. SEMI: What forces are heightening the importance of heterogeneous system integration? What are the implications for increased on-package bandwidth, improved yield resiliency and the need to integrate diverse IP from multiple foundries? Radhakrishnan: The semiconductor industry increased transistor density and scaled performance through classical Dennard scaling until the turn of the century. By then, the gate oxide thickness had scaled down to atomic dimensions and the exponential increase in sub-threshold leakage signaled the end of scaling through traditional methods. Since that time, the chip industry has been relying on innovations in transistor materials and structures such as high-k metal gate, strained silicon, and FinFETs to keep pace with Moore’s law. However, this alone will not be sufficient to continue scaling and the industry needs to explore other vectors to augment improvements in transistor technology. Heterogeneous integration through advanced packaging is one key technology that can help drive these gains. Technologies like Foveros can enable device density scaling by creating a 3D stack of multiple die using high-density interconnects. Heterogeneous integration enables chipmakers to move from a monolithic system designed on a single large chip to a heterogeneous system comprised of a number of smaller chiplets. The main benefit of using smaller chiplets is that they improve yield and enable application based customization of the foundry processes. However, if the disaggregation to smaller chiplets is not accompanied by an increase in on-package bandwidth, the power and performance penalties associated with chiplet-to-chiplet communication will hobble system performance. This is why advanced packaging technologies that improve die-to-die communication are key enablers for heterogeneous integration. SEMI: What are some of the key technology challenges in developing heterogeneous systems? Radhakrishnan: The obvious challenge that most people focus on is the need for improved on-package bandwidth. However, as we rely on 3D stacking to continue device scaling at the package level, it is important to comprehend power delivery and thermal challenges as well. Power to the top die has to be delivered through TSVs on the bottom die, which not only adds resistance but also reduces the useful area available on the bottom die. This problem is further exacerbated when we stack more than two die. Excessive noise on the power delivery network can cause timing issues that limit the maximum operating frequency of the transistor. Similarly, when we stack multiple die, we must take into account associated thermal challenges. For example, each interface of the multi-die stack adds thermal resistance, which makes it harder to cool the chips at the bottom. SEMI: What are some of the key global market trends that driving demand for heterogeneous and system-level integration? Radhakrishnan: The number of artificial intelligence (AI) and machine learning applications have grown dramatically due to their ability to solve highly complex problems across a wide range of segments. AI and machine learning models require more memory bandwidth and compute capabilities that are difficult to achieve without some form of heterogeneous integration. Another market trend driving demand for heterogeneous integration is the increasing reliance on custom hardware accelerators. To combat the slowdown in frequency scaling and single-core performance, we have moved to multi-core architectures by tackling the inherent parallelism in our workloads. However, Amdahl’s law tells us that such an approach will hit a bottleneck when we reach the limits of the serial portion of the workload. As these constraints slow the performance of general-purpose processors, the reliance on custom hardware accelerators to boost performance for specific workloads is growing. Heterogeneous integration at the system level with a combination of CPUs, GPUs, FPGAs and other accelerators can optimize system power and performance. SEMI: What solutions is Intel developing to address these market needs? Radhakrishnan: Intel is actively involved in the development of the industry ecosystem for heterogeneous integration. We have developed a number of innovative advanced packaging solutions such as the EMIB and Foveros that are used in products today. Intel is also developing the next generation of advanced packaging technologies, Foveros Omni and Foveros Direct, which will dramatically scale the IO density by using direct Cu-Cu bonding technology. Foveros Omni is a crucial building block technology to enable high-voltage power conversion on the package for efficient power delivery. Intel is uniquely positioned to predict the design needs for future systems and deploy its resources to develop the technology building blocks needed to continue performance scaling. Our IDM 2.0 strategy enables us to leverage our leadership in packaging technologies to design the best products and use the best IP to deliver leading products across a broad range of categories. SEMI: What do you expect from your participation at SEMI Connecting Heterogeneous Systems Summit? Radhakrishnan: I’m hoping to shed some light on some of the new technologies we have been developing at Intel to enable heterogeneous system integration. I also want to bring awareness to the power-related challenges we are facing with heterogeneous systems. I also look forward to listening to what other industry leaders have to say on the topic. Kaladhar Radhakrishnan is an Intel Fellow and a Power Delivery Architect with the Technology Development group at Intel. He plays a significant role in shaping and driving power delivery technologies for Intel microprocessors. His areas of expertise include integrated voltage regulators, advanced packaging and passives technologies. Kaladhar is a two-time recipient of the Intel Achievement Award, the highest Intel honor an individual or small team can receive. He has authored four book chapters, over 40 technical papers in peer-reviewed journals, and has been awarded 35 U.S. patents. He has also served as an adjunct professor at Arizona State University. Kaladhar joined Intel in 2000 soon after receiving his Ph.D. in Electrical Engineering from the University of Illinois at Urbana-Champaign. Serena Brischetto is senior manager of marketing and communications at SEMI Europe.