5G

Electronics industry experts will offer insights into key aspects of the radio frequency (RF) challenge – from materials and devices to ICs and modules – at ITF Beyond 5G at SEMICON Europa 2022, Nov. 15-18 in Munich, Germany.

More than 4,000 participants convened in person at the four-day SEMICON Europa Expo in Munich, November 16-19. Attendees gathered at the Executive Forum for insights into the latest trends in the semiconductor industry and heartily welcomed the long-awaited return to in-person networking.

In the span of a few short months earlier this year, Mentor Graphics became Siemens EDA and introduced a suite of integrated hardware-assisted verification tools, the first product launch under the new Siemens EDA brand. Jean-Marie Brunet, senior director of marketing, product management and product engineering at Siemens EDA, orchestrated the launch and connected with me for a discussion about the chip design verification space. As he pointed out, verification and validation of systems is a fast-growing and important market segment to the electronic system design ecosystem. Smith: What trends do you see in chip design? What is driving these trends? Brunet: Chip verification costs continue to grow faster than design costs because of factors such as increasing design complexity, rising computing power, surging I/O traffic activity, increasing energy consumption and the widespread use of peripherals. These dynamics are being driven by new data center networking, communications/5G, autonomous driving, artificial intelligence (AI) and machine learning (ML), and storage applications. These trends also indicate the need for more powerful verification tools and expanded verification objectives that include power and performance analysis. Hardware-assisted verification tools are perfect for meeting these demands. Smith: Chip design verification consumes the most time in a project cycle. Why is this so? Brunet: The verification of designs reaching multi-billion gates and supported by voluminous software stacks is fraught with challenges. To exhaustively check every possible state in a billion-gate design with simulation alone would require up to trillions of verification cycles. That’s why hardware-assisted verification is one of the fastest-growing technologies in EDA. Given the complexity of today’s SoC design, it’s no surprise that verification is the largest undertaking in the entire project design cycle, consuming more than 50% of it. It also has the greatest impact on quality, cost and schedule because it prevents designs from failing at first silicon. While a respin of a large design taped out at a node below 10 nanometers could cost more than $10 million, delaying delivery of a new product for a few months in a highly competitive market may cost hundreds of millions of dollars. Smith: What other challenges do engineers face trying to verify a chip design will work as intended? Brunet: Verifying an SoC design is a massive undertaking and, in parallel, verification teams are trying to streamline and optimize verification cycles. SoC design groups are tasked with completing full system-level verification prior to creating production masks by thoroughly vetting all hardware blocks, interactions between those blocks, and the software developed for the end application before the chip is built. To alleviate this enormous pressure, they are starting to adopt a shift-left methodology for early functional verification as soon as individual blocks of a SoC design become available. It helps jump-start embedded software validation before full system validation is completed to save time and allow engineers to work in parallel, not serially. While it is an effective approach, it creates the need for a complete and integrated suite of hardware-assisted verification tools to verify and validate a design’s hardware and software components. Smith: How do you define hardware-assisted verification and how does it help solve these challenges? Brunet: A typical definition of hardware-assisted verification is special purpose hardware to accelerate verification. In other words, hardware emulation and FPGA prototyping. Hardware-assisted verification is a mandatory investment as single-die or multi-die chips get larger with more complexity and more interfaces, making hardware and software code integration critical early in the design cycle. Because software performance defines a chip’s success, the need to perform software workload-based analysis is acute, not just analysis of chip functionality, but also accurate performance and power consumption in the context of real-world applications. Hardware-assisted verification is the only option when hardware and software meet. By combining emulation, desktop FPGA prototyping boards and enterprise FPGA prototyping platforms to work on the same SoC design, a verification group can assemble a complete hardware-assisted verification system for thorough and exhaustive verification and validation. Smith: Where are the big opportunities for hardware-assisted verification? Brunet: New end-user applications are coming from computing and storage, AI/ML, 5G, networking and automotive. Recently released market data from the ESD Alliance shows that in 2020, hardware-assisted verification revenues exceeded $700 million. It is reasonable to assume that revenues of $1 billion will be within reach in the next few years given the amount of chip design activity at advanced nodes below 10nm. Smith: With the design/verification and manufacturing phases of the semiconductor supply chain more closely aligning, what role does hardware-assisted verification play? Brunet: Semiconductor manufacturing and the supply chain that supports it benefits greatly from the continued innovation in verification and validation tools and methodologies. With this innovation, designs are delivered to the manufacturing flow with a much greater chance of passing first silicon with success. This reduces friction in the semiconductor supply chain since IP and chips are available when anticipated. Hardware-assisted verification is a quick-moving, highly leveraged resource that helps a design and verification team to ensure chips are manufacturable and meet the functionality, power and performance requirements for the end-product application. Jean-Marie Brunet is the senior director of product management and engineering for the Scalable Verification Solutions Division at Siemens EDA. He has served for over 20 years in application engineering, marketing, and management roles in the EDA industry, and has held IC design and design management positions at STMicroelectronics, Cadence, and Micron, among other companies. Jean-Marie holds a Master's degree in Electrical Engineering from I.S.E.N Electronic Engineering School in Lille, France. Jean-Marie Brunet can be reached at [email protected]. About Bob Smith Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community. He is responsible for the management and operations of the ESD Alliance, an international association of companies providing goods and services throughout the semiconductor design ecosystem.

With the CAGR for switches in cell-phone RF front-end modules running at 9% for the next five years, new players want to get in on the action, and established players want to up the ante. The specialists at Incize help wafer suppliers, foundries and fabless companies maximize switch performance starting at the substrate level. CEO Mostafa Emam explains how.SOI News (SN): Can you tell us about the role Incize plays in the RF-SOI ecosystem? [caption id="attachment_32519" align="alignright" width="140"] Incize CEO Mostafa Emam. (Photo courtesy: Incize)[/caption] Mostafa Emam (ME): Our clients are wafer suppliers, foundries and fabless companies. The services we offer are testing and modeling of substrates, with the vision of what will happen in the value chain. Based on what the customer will do with the substrates, we do testing and modeling to improve the technology and tune their processes. Although the big players have teams devoted to this, we can add a layer of characterization that they have no expertise in. Some of our customers are foundries that have been using bulk silicon, but now see opportunities in RF-SOI. But they’re starting from scratch and we help them to adopt the technology. We help them understand the physics behind the technology so they can migrate from bulk to SOI. We help them develop test structures and evaluate their technology. Then we create models for both fully-depleted and partially-depleted SOI with PD-SOI 130 nm or 60 nm technology dominating the RF front-end module market. We believe RF is an art and you need to see the whole picture. SN: Can you tell us a bit about the history of Incize? ME: The RF-SOI story started in the 1990s. Then came trap-rich RF-SOI wafers from Jean-Pierre Raskin’s team at UC Louvain, industrialized by Soitec. Our lab at UC Louvain became known for our expertise in RF-SOI, and in 2011 we created Incize as a spin-off. [Editor's note: for more background, see this SOI Consortium article about the birth of trap-rich substrates and the company’s founding.] At first our characterization services were very diverse, but by 2014 we focused mostly on RF-SOI because of the big demand. In 2015 we started doing radiation hardness tests for space applications and a new business unit was created. In 2016 we started our modeling and PDK activity, followed the next year by work on GaN on Si. In 2018, we started offering full support to RF-SOI newcomers, who were starting from scratch, usually smaller players in the RF market. It takes about two years to fully train the engineers, support the technology enhancements, design test vehicles, measure them and finally do the modeling and PDK. So some of these players are now fully established in the RF-SOI market and have contracts in place with big customers. SN: In your presentations, you often say there is room for all. What do you mean by that? ME: There is a big market for RF-SOI in the coming years. It can offer the low-power, the low-cost and the high performance. RF-SOI is the only mature technology that combines all of this today. It successfully competes with traditional III-V technology. More foundries want to employ RF-SOI. We show to them that it’s not black magic – you just need to know how it works. [bctt tweet="There is a big market for RF-SOI in the coming years. More foundries want to employ #RFSOI. We show them that it’s not black magic – you just need to know how it works. - Incize CEO Mostafa Emam #5G #semiconductors" username="@soiconsortium"] On our side, we have the knowledge and the infrastructure. Our added value is that we can do advanced tests the customers can’t do. So the foundry says there’s opportunities in switches, we’ll do this and develop it all with optimization for specific Ron and Coff [the figure of merit for RF switches]. The foundry develops an RF switch and aiming at certain performance (RonCoff). We help our customers during this development phase. Once the performance target is reached we start developing a model and a PDK. There is enough demand for RF-SOI, as even entry-level cell phones have SOI chips. Some opt for a fast and low-cost solution. Many target “good enough”, although some target to compete against the big players – it’s a question of their business strategy. And this is where our added value comes in. SN: Can you provide some more insight into how you see the RF market? ME: The Front End Module (FEM) is a fast growing market, with increasing demand in terms of volume and performance. This includes antenna switches, LNAs, tuners, filters, etc. Historically, III-V materials have been used for their high performance and high power handling. However, RF-SOI has become the material of choice, and the biggest driver is integration of the RF switch and LNAs in one chip. It’s not easy to integrate the power amplifiers (PAs) on the same chip (still being on III-V substrates). But as it decreases footprint and cost, there are those who’ll do it. There is no viable competition for SOI – nothing will replace it in the short term. There are other technologies, but they are long term. It’s a stable market with high demand. SN: For those of us who are not RF experts, can you help us understand the technology? ME: The switch is sort of the traffic light of the FEM, receiving and transmitting. The simplest RF switch can be composed of only four transistors. Transistors leak power so you need to determine your Ron Coff performance. [Editor's note: Resistance on vs. Capacitance off, the RF switch figure of merit, is measured in femtoseconds and should be as low as possible. Psemi has a good video explaining it.] When the Coff capacitance is small, the switch is really off. When the On resistance Ron is small, it means low losses, and the switch is turned On. Ron and Coff is a compromise. And as there are many frequency bands and antennas, the FEM becomes very complex. Another issue is power handling, since the switch is the first stage behind the antenna. And finally, there is the question of switch linearity. Trap rich SOI wafers suppress harmonics so you have less distortion originating in the substrate. You have to model this – the designer needs to know. In addition to single tone harmonics you also get intermodulation, where, two or more high power signals at two different frequencies create distortion at other frequencies. The danger is that these parasitic signals can be so close that the filter can’t reject them and the useful signals get distorted. This was a killer for the switch created on the bulk substrate. Trap-rich RF-SOI fixed this. So now 100% of switches are on trap-rich SOI substrates. While it’s still a niche market, there is demand from customers for increasing the number of bands – that’s driving this market. SN: And what happens as we move to 5G? ME: There’s more and more pressure on the specs. It’s an art when anything changes. Moving from 3G to 4G required complete upgrade of the [foundry’s] models. With 4G, the specs are severe and the FEM must be built on trap-rich substrates. But 5G is not well defined, so the RF industry is taking their best shot. What is clear: the performance requirements get more challenging. Once the technology is understood, it can be implemented. But the foundries and the fabless need our help to do it fast and do it well. We create more value working together. SN: How do you see things evolving? ME: The number of foundries today doing switches on RF-SOI is increasing, and this will continue for the next few years. We saw this opportunity and invested in it. Our company is just ten people, and we are self-funded. We are swimming in business, but we have fun. And we’re getting recognition. Any company with CMOS in place could adopt RF-SOI. But it’s a different mindset. We help with the transition. ~ ~ ~Click here to read more feature articles in SOI News.

The chip design ecosystem finally has the book it’s been clamoring for: The Fourth Terminal - Benefits of Body-Biasing Techniques for FDSOI Circuits and Systems. [bctt tweet="The FD-SOI Chip Design Book: Yes, It’s Finally Here!" username="@soiconsortium"] The editors (who have also contributed chapters) are Andreia Cathelin, Sylvain Clerc and Thierry DiGilio, all world experts from STMicroelectronics. As Cathelin and Clerc note in the introduction: “The aim of this book is to introduce to the design community the straightforward design solutions in any modern FD-SOI planar CMOS technologies, by taking full advantage of body biasing techniques to efficiently modulate on the fly SoC solutions from high performance operation to energy efficiency mode. All design techniques are based on the classical pillar of regular planar CMOS devices. As the first fully industrial solution has been the 28nm FD-SOI CMOS technology from STMicroelectronics, all the design examples in this book have been demonstrated within this process integration frame.” [bctt tweet="The Fourth Terminal...taking full advantage of (FDSOI) body biasing techniques to efficiently modulate on the fly SoC solutions from high performance operation to energy efficiency mode" username="@soiconsortium"] The folks at ST were really the first to get into FD-SOI in a big way – in fact they’ve been at it for over two decades (!) so you’d be hard pressed to find experts at a company with deeper expertise. [caption id="attachment_29610" align="alignnone" width="535"] The Fourth Terminal team friends sporting Tour de Fourth Terminal t-shirts at ISSCC 2020. From left to right: MIT Prof. (and Series Editor for Springer's Integrated Circuits and Systems) Anantha Chandrakasan; Charles Glaser, Springer Editorial Director; Laurent Le Pailleur, ST; Andreia Cathelin, ST Fellow; Sylvain Clerc, ST; Stanford Prof. Boris Murmann (Photo courtesy Springer STMicroelectronics)[/caption] The Fourth Terminal is structured to cover three major areas: a technology overview (including body biasing for digital, analog and SRAM); a selection of circuits that illustrate body biasing in various fields; body bias deployment in mixed-signal and digital SoCs. The initial response has been tremendous. Editor Andreia Cathelin reports that posts she's made about it on LinkedIn were quickly viewed 10k times and more. Then came the book review by the eminent Stanford Professor Boris Murmann, who heralded its tour de force status in a clever turn of phrase: “With the help of a renowned international team of experts from industry and academia, the editors have distilled everything you need to know about FD-SOI circuit design into a 16-chapter "tour de fourth terminal". (Read his complete review here).[bctt tweet="Stanford Professor Boris Murmann calls this book a #Tour_de_Fourth_Terminal. #FDSOI #lowpower #chipdesign" username="@soiconsortium"] EETimes journalist Junko Yoshida blogged about it as Body Bias Gets Its Own Book (read that here), which generated lively discussions on LinkedIn (and underscored just how necessary this book is!). The Fourth Terminal - Benefits of Body-Biasing Techniques for FDSOI Circuits and Systems is part of the Springer Integrated Circuits Systems Series -- considered by many to be the most prestigious in the industry. Weighing in at 431 pages, The Fourth Terminal is available in both e-book and hardcover versions. See the Springer website to order this must-have addition to your library.

The SOI Consortium’s Japan Symposium this past fall covered a wide array of topics over two days. The first day was devoted to IP and products for RF and ultra-low-power (ULP) on SOI. The second day covered high voltage and photonics. It will take several posts to summarize all the presentations. In this post, we’ll cover presentations related to 5G. In the next posts we’ll cover IoT/ultra-low-power/automotive and photonics. (BTW, if your company is a member of the SOI Consortium, you can now access most of these presentations on our website.) The Japan SOI Symposium was organized for the 4th time at the Yokohama Landmark Tower (from which there was a fabulous view of Mount Fuji). It was a great success, with both days well attended. The event followed the day after (and in the same location as) Silvaco’s SURGE user event, so there were plenty of opportunities for synergy there. (Samsung Foundry talked about their partnership with Silvaco, for example, and their work together on RF and eMRAM on 28nm FD-SOI.) STMicroelectronics [caption id="attachment_27068" align="alignnone" width="589"] From “5G Deployment Driving RF and SOI Technology Opportunity” (Courtesy: ST SOI Consortium)[/caption] As noted in the ST presentation, 5G standards are getting a big push in the Asia-Pacific region, and by China in particular, which is leaping ahead especially in sub-6GHz. It’s a complex standard, noted John Carey, the company’s director of Digital RF for the A-P region, and it’s disruptive, demanding new silicon architectures and technologies. Next year’s premium phones, he said, will include over $30 in RF components, 40mm2 of which will be based on SOI. ST has been working on RF-SOI for over two decades, and offers a range of technologies and foundry services supported by three high-volume fabs. The key benefits with RF-SOI, he explained, stem from RF FEM integration of switches, LNAs and PAs. RF-SOI technologies are here now and are successful in the markets: ST has a long-term technology roadmap and is making continued strategic investments, he concluded. Toshiba [caption id="attachment_27069" align="alignnone" width="410"] From “RF-SOI Switch LNA for Mobile Applications” (Courtesy: Toshiba SOI Consortium)[/caption] Another long-time RF-SOI user is Toshiba, although this marked their first participation in a recent Consortium event. As Group Manager Kazuyuki Uchida talked about RF techology trends, there was lots of note- and picture-taking in the audience. He pointed out that the character and size of the switch LNA modules are particularly important in the move to 5G. They’ve been leveraging their TaRFSOI(tm) process, which he said achieves the industry's lowest insertion loss, for about a decade now. The latest version, TaRF11 will be launching in Q1 of 2020. TaRF10 integrated the LNA with the switch and control circuitry in a single chip. TaRF11 will feature performance improved by about 25%. Incize [caption id="attachment_27065" align="alignnone" width="405"] From “RF Characterization” (Courtesy: Incize and SOI Consortium)[/caption] During the Incize presentation, the company’s CEO Mostafa Emam affirmed that RF-SOI is a very good business opportunity. Incize works with the complete supply chain. For foundries and wafer suppliers, they measure harmonics and output with very high precision, which is especially critical for switches. For the wafer suppliers, it’s predictive. For the foundries, it’s measuring noise for models and PDKs. While RF may be an art, second tier foundries using Incize services are now able to compete with the first tier players, he noted. He sees trap-rich RF-SOI wafers as being especially important for 5G. GlobalFoundries [caption id="attachment_27064" align="alignnone" width="599"] From “RF Reliability for SOI CMOS Si-based Power Amplifier for 5G applications” (Courtesy: GlobalFoundries SOI Consortium)[/caption] The focus of the GlobalFoundries talk was reliability in RF processes. In 5G, you need technologies that are viable for both mmWave and sub-6GHz across handsets, wifi and automotive, noted Purushothaman Srinivasan (who goes by SP and is a senior member of the company’s technical staff). In SOI, you can stack FETs (which you can’t do in bulk) for PAs, which is a big advantage in mmWave. However, delivering scalable, linear, efficient and reliable RF power technology is more challenging than digital, and requires a holistic, collaborative approach that includes the foundry, the customers and the test equipment suppliers. GF has used its RelXpert simulation tool on aging simulations and lifetime predictions for both their 22FDX and 45RFSOI processes. They have observed good RF model-to-hardware correlation, and have built Safe Operating Maps that provide guidance to RF designs. This first-in-industry RF reliability evaluation provides “highly differentiated” solutions for GF. Silvaco [caption id="attachment_27066" align="alignnone" width="606"] From “RFSOI TCAD Solution” (Courtesy: Silvaco and SOI Consortium)[/caption] Silvaco is a leading EDA provider of software tools used for process and device development and for analog/mixed-signal, power IC and memory design. Their presentation began with a review of recent updates to their TCAD simulation framework, including the TCAD design flow, Victory ProcessTM simulation for speeding up 2D/3D process simulations, and Victory DeviceTM simulation. Under Silvaco’s DTCO – Design Technology Co-Optimization – semiconductor physics are connected to circuit design, recognizing that each technology has specific requirements that need to be taken into account at every stage of the flow. Applications Engineer Sun Tao then continued by showing useful TCAD simulations and analysis of SOI for RF applications. In trap-rich substrate simulations, for example, the Silvaco tools can predict the harmonic balance from the active device, device biasing and substrate, all of which can be co-optimized using Victory Process and Device. SITRI [caption id="attachment_27067" align="alignnone" width="305"] From “NB IoT FEM based on SOI” (Courtesy: SITRI SOI Consortium)[/caption] Shanghai Industrial μTechnology Research Institute – aka SITRI – is an international innovation center, focused on globally accelerating the innovation and commercialization of “More than Moore” technologies to power IoT. SITRI Director Wenwei Yang’s talk focused on their narrowband front-end module for IoT (NB IoT FEM). NB-IoT is especially meant to handle small amounts of data from remote places over long periods. There are a lot of players in this market, so taking a “good-enough” approach to performance wherein cost is primordial is key. SITRI’s low-cost NB-IoT FEM integrates everything on a single chip, including the power amplifier (PA) and integrated passive devices (IPD), so packaging costs are low. Putting it on SOI (either trap-rich or high-resistivity) gives them better isolation and simplifies integration. ~ ~ ~ Our next post will continue our coverage of the Japan Symposium. Note: 2019 marks a decade of SOI Consortium events – yes, our first one was in 2009! Because a lot of the presentations in the past were so forward-looking, many of them are still of great interest today. Currently the presentations from 2015 through to the beginning of 2019 are available freely to everyone – and are well worth perusing.

The SOI Industry Consortium awarded two luminaries of the semiconductor industry for pioneering advances in RF-SOI, a technology now found in all cellphones. Jim Cable (shown on the left in the photo above), Chairman and CTO of pSemi, a Murata Company, and Herb Huang, CEO and GM of Ninbo Semiconductor received the awards during a gala following the SOI Consortium's 2019 RF-SOI Workshop in Shanghai. "Thanks in large part to the innovation, dedication and perseverance of men like Jim Cable and Herb Huang, RF technology based on SOI is now ubiquitous," said Carlos Mazure (on the right in the photo), Chairman and Executive Director of the SOI Consortium. "Jim Cable drove the development of SOI and RF switches that are now in every cellphone, and Herb Huang has been a key contributor to SOI technology and a champion of the SOI foundry ecosystem in China. We are happy and honored to recognize the contributions they have made to advancing RF-SOI globally." Jim Cable joined pSemi (formerly Peregrine Semiconductor) in 1996 and held technical leadership roles before serving as CEO from 2002 to 2017. An early pioneer of SOI technology, Cable believed SOI would ultimately replace other technologies in the RF front end, and he pushed his team to innovate. Cable is a co-inventor on more than 70 semiconductor and technology patents, including breakthroughs in SOI-based processes for CMOS RF switch linearity and integration that are used by all smartphones today, and will become even more mission-critical in 5G and millimeter-wave markets. He received his B.S. in physics from UC Riverside and his master's degree and Ph.D. in electrical engineering from UCLA. Herb Huang is CEO of Ningbo Semiconductor International Corporation (NSI), which is based in Ningbo, China. A driver of the RF-SOI ecosystem in China, he spent much of his career at SMIC, the largest semiconductor foundry company in mainland China. In 2016, SMIC created NSI as a joint venture subsidiary with China IC Investment Fund, Ningbo Economic Development Zone Industrial Investment Company, Ltd. and other IC investment funds. Under Huang's leadership, NSI optimized the process and model of a 0.13um RF-SOI technology platform transferred from SMIC. Now in mass production, the RF-SOI technology platform supports customers in IC design and product development for new generations of radio communications. Huang holds both a Ph.D in Materials Science and Engineering and an MBA from the University of Minnesota.

The 2019 International RF-SOI Workshop in Shanghai was packed to overflowing, with over 500 attendees, noted SOI Consortium Chairman Executive Director, Carlos Mazure. There were 16 presentations over the course of the day – every one of them excellent – so it will take two posts to cover them all. We covered Danni Song's compelling keynote in a previous post – see it here. In this post, we’ll cover the remaining keynotes and the morning session, which was dedicated to 5G deployment. In the next post, we’ll cover the afternoon sessions, which were dedicated to the China RF-SOI ecosystem, and the RF value chain. PDFs of the presentations are not yet posted, and then they will only be available to those whose companies belong to the SOI Consortium. But we’ve summarized them all for you, so read on! KeynotespSemi: 30 Years of RF-SOI – Past, Present and Future (Jim Cable, Chairman and CTO, pSemi (a Murata company))The keynote by RF-SOI legend Jim Cable chronicled his always-innovating journey from digital to RF via sapphire then SOI. (Cable's work was recognized in an award that evening.) His original vision back in the early days was for a RF front-end module (FEM) + CMOS transceiver. At the time, doing it on sapphire (an insulator) rather than bulk made it much easier, as sapphire eliminated the non-linear capacitances. That was the beginning of their UltraCMOS technology, and though it did very well, sapphire was only available in 6” wafers. So pSemi (or Peregrine, as it was known at the time), engaged with Soitec on bonded-SOS. “It was a killer technology, and the marketshare we won was staggering,” he recalled, and helped convince Soitec RF-SOI was worth looking at. The goal is to handle high RF power levels: you can use SOI to handle higher voltages than you'd think were possible. They added an invention they called HaRP, that dealt with accumulated charges and enabled them to hit the linearity specs on silicon. With that, he explained, they came to completely dominate the switch industry. UltraCMOS evolved, getting 60% smaller with 20x better linearity – but now of course you have 50 switches, not six. He heralded the great partnership they have with GlobalFoundries, noting, “We were pioneers in this field.” In fact, in 2017 they were in the top 10 for IP generation in semiconductor manufacturing. Now comes mmWave, where he says, “We see everything we believed and more.” They're currently sampling an 8-channel mmWave RFFE (RF Front End). Soitec: 5G-on-Insulator: the 5th Gear In Mobile Radio (Michael Reiha, GM, Soitec)Michael Reiha's talk centered on how SOI wafer-leader Soitec is positioning itself on 5G, which, he explained, demands a wider portfolio. Soitec looked at what they could do to make 5G ready for sub-6GHz. Massive MIMO (mMIMO) is an efficient technique to improve throughput. With SOI, you can reduce the power it takes, making it a good choice for urban environments. RF-SOI is a candidate for power amplifiers, and FD-SOI is enabling more users to be added. The concept of network sharing is an opportunity for compact, low-cost filters that can meet the requirements with simpler, lower-cost, higher-efficiency filters. That's why they've just announced a new substrate called piezo-on-insulator (POI). However, total cost-of-ownership is not just how much a product costs, but how much it costs to run it.. Currently, RF and mechanics dominate the bill-of-materials, so you need to decrease the number of RF FEM components and get savings scaled with the array size. The main challenge of SOI is in efficiency, but the advantage is that it can be used in integrating digital with analog sensing and RF. Then you can use AI sensing for tracking temperature, for example, and control for 5G optimization. In short, with RF-SOI, you apply AI to the radio head, especially for things like mMIMO. And btw, he added, Soitec currently has capacity of two million wafers per year. SESSION 1 – 5G DeploymentYole: 5G is ON. Which Impact for RFSOI Technologies? (Cederic Malaquin, Technology Market Analyst)There are over a thousand 5G networks available today worldwide, said Cederic Malaquin. Adoption is accelerating, driven by 5G cloud gaming, AR/VR/XR, 5G multi-video calling and stadiums. However, carriers need better ROI. 5G should address this so that customers are better served. MIMO and carrier aggregation (CA) are the main techniques supporting network capacity and coverage improvements. 5G NR will bring more spectrum. With each generation putting more content in phones, new spectrum is happening in sub6 and mmWave. The impact of 5G on mobile phones is huge in terms of both content and complexity. Some phonemakers (like Apple and Samsung) are moving towards increased integration. Others (like Huawei) are going more for discretes. Yole sees tuners, switches / LNA as addressable by RF-SOI, but they are less convinced about power amplifiers. They also see SiP (system in package) as prevailing over integration. The 5G mobile and base station markets will really build up in 2022-25. RF-SOI will remain the mainstream technology for switches and antenna tuners through at least 2025: they don't see anything else replacing it. There is still increasing demand for 8” wafers. 12” wafers growth comes from integrated switch/LNAs, which comes from the Tier 1's. In the front-end space, Murata leads in dollars by far, followed by Skyworks and others. Though mmWave is not yet clear, there are opportunities for RF-SOI. ST: 5G Deployment Driving RF and SOI Technology Opportunity (Laura Formenti, Sr. Director)STMicroelectronics has a long history in RF-SOI, noted Laura Formenti, dating back to 2000 when they started collaborating with Soitec and Leti. An IDM, ST also offers foundry services. For 5G, their foundry offering includes H9SOIFEM, C65SOIFEM and SOI mmW for high-performance analog, dedicated RF processes for RF switches, LNA, PA plus RFFEM. Then they have FD-SOI for RF, mixed signal and digital integration. From antennas to transceivers there's an opportunity for full integration. For infrastructure, it depends on the customer preferences. 12” C65SOIFEM was introduced in 2019, and 12” SOIMMW will be introduced in 2020. Both their fabs at Crolles and Rousset, France, are in production. H9SOIFEM is for 4G and 5G sub-6GHz RF FEMs, enabling monolithic integration of the PA, LNA and switches, which is especially good for wifi. The C65SOIFEM is high-performance. Panel: 5G Deployment in China, Jeffrey Wang, CEO, Simgui Technology, moderatorWith Danni Song (China Mobile), Jim Cable (pSemi), Peter Rabbeni (GF), YangYang Pen (SmarterMicro), Paul Hurwitz (TJ), Michael Reiha (Soitec)Q: Why sub-6GHz and not mmWave?Danni Song said its a question of available spectrum. In sub-6, you get the same level of coverage with fewer base stations; also, sub-6 is much more mature. When will mmWave be ready? It depends. In the US, yes, but in China the spectrum allocation for mmWave has not yet been done. So it's a wait and see for the industry to be ready. Peter Rabbeni agreed, adding that in the US sub-6 is crowded and conflicts with military bands. Paul Hurwitz added that mmWave is for fixed wireless access. Michael Reiha added that mmWave has advanced a lot even in the last few months (Verizon in Washington, DC, for example), so there is momentum.Q: Does China lead in the sub-6GHz opportunity?Jim Cable said that at pSemi they have two business models: mobile and infrastructure. He sees massive MIMO in base stations as huge (though in mobile their role is more supporting Murata). Peter Rabbeni added that they're working with innovative partners in China, and that GF also offers skills in services and packaging. Yangyang Peng sees big opportunites with 5G for SmarterMicro and China. Paul Hurwitz has seen an increase in the capabilities of RF companies in China, and that the market in China moves faster than elsewhere. Michael Reiha sees China as strategic, and because there is central deployment, they can plan with the right partners.Q: Data usage will be huge – what will it cost to individual users?Danni Song said 5G phones will be expensive, but consumers want them, so we need to bring down costs and increase performance – but what about power consumption? Power needs to come down, maybe levering things like sleep mode more. For 3G 4G, she noted, they had lots of time. People are pushing hard for 5G, but there's a need for patience. Yangyang Peng said he didn't want to pay more than for 4G. In summary, Jim Cable noted that mmWave will demand huge amounts of silicon, to which Paul Hurwitz agreed, and Michael Reiha said Soitec will be ready. Everybody agreed that 3D packaging would be very important, especially for mmWave. And that's it for our coverage of the morning. Next up we'll cover the presentations given during the afternoon.

Join us! In partnership with our members, the SOI Consortium is co-organizing and participating in two key SOI events coming up in China over the next few weeks. On May 18th, we’ve put together an SOI Forum at the World Semiconductor Congress (WCS) in Nanjing. And on May 23rd 24th, we’ve teamed up with our members SIMIT, Sitri and Leti for another in our series of SOI Academies, including an FD-SOI Training Day. (The last one this past winter was a terrific success – read about that here if you missed our coverage at the time.) QR code for WCS, Nanjing '19At WCS, the SOI Forum (sub-forum #8) is part of the afternoon Innovation Summit. We’ll cover the broader SOI ecosystem, including both RF-SOI and FD-SOI – from wafers to design through manufacturing. Presentations will be given by members of the SOI Consortium team, and by leaders from our membership, including Simgui, NXP, Incize, ST, IBM, Cadence and Xpeedic. Click here or scan the QR code for the full program and registration information. Also at WCS, SOI Consortium member VeriSilicon will be participating in a morning session on AI and IoT Wireless Communications (sub-forum #4). They’ll be giving a presentation on their low-power Bluetooth design platform for GlobalFoundries 22FDX, and their CEO Wayne Dai will be moderating a round-table discussion. You can get more information on that (in Chinese only, tho) here, or follow VeriSilicon on WeChat. QR code for SOI Academy and FD-SOI Training, Shanghaid 2019The SOI Academy in Shanghai is an opportunity for experienced designers to gain solid expertise in FD-SOI. The event begins in the afternoon of May 23rd with a series of informative plenary talks by members of the SOI Consortium team, and by experts from our members Leti, Soitec, VeriSilicon, GlobalFoundries and NXP. The FD-SOI Training starts the next morning, on May 24th.. This is a hands-on event lead by top experts from Leti. The morning is devoted to digital design in FD-SOI, and the afternoon to RF design (including for 5G) in FD-SOI. Attendees will get a comprehensive understanding of design techniques for low-power chips leveraging the multiple benefits and flexibility of FD-SOI technology. Get more information here, or from the WeChat QR code.We've got a busy schedule! To keep up to date with where we and our members will be promoting the SOI ecosystem, be sure to check our Events page regularly.