SEMI Standards

The semiconductor industry continues to push the envelope to meet demands of key applications such as advanced computing, consumer electronics, and defense, as well as environmental sustainability. There remain several critical challenges that our industry is working diligently to address, but how can these issues be tackled more effectively and at a pace that can keep up with this ever-evolving landscape?SEMI sat down with Supika Mashiro, Advisor at Tokyo Electron, where she shares her perspective on the importance of strengthening industry collaboration and what SEMI is doing through its first-ever SEMI Global Standards Summit – “Innovating Tomorrow: Standards for Future Factories” – of which she chairs the Planning Committee responsible for organizing this Summit.Trio: What is the SEMI Global Standards Summit and why is this event timely?Mashiro-san: Topics such as advanced packaging, cybersecurity, as well as supply chain and materials innovation (and their impact to the environment) are considered strategic areas requiring more industry collaboration. Many of these areas also greatly benefit from standards, and the next generation specifications and guidelines will need to be engineered to meet the technical challenges we face today and in the future. The magnitude of these standardization efforts will require engagement from all stakeholders in the design-to-manufacturing value chain as well as multiple Standards Developing Organizations (SDOs) coordinating and collaborating with each other.This is the driving force behind the Summit, and the need to bring together industry stakeholders to identify standards-critical areas and align on developing an industry standardization strategy for the next 3- and 7-year time horizons. We are excited to host this inaugural event on December 12, 2024, in conjunction with SEMICON Japan 2024. Trio: What is the focus of the Summit?Mashiro-san: The Global Standards Summit will cover three main themes: Smart Manufacturing for Future Factories, Packaging Architectures Materials, Environmental Sustainability.Factories are increasing their use of digital twins, predictive maintenance, and AI/ML to improve productivity and yield across the entire manufacturing environment. To take full advantage of these approaches, factories must reduce cybersecurity risks and secure the transfer of “smart” data across the entire supply chain while protecting IP. There is a need for standards to address these risk areas, as well as help diverse advanced analytics systems interoperate to assist personnel in increasing factory productivity. In the Smart Manufacturing for Future Factories session, we will be focusing on autonomous fabs, cybersecurity, and flow-oriented manufacturing.Similarly, packaging technologies have been progressing since the early stages of semiconductor device development more than 70 years ago. More recently, where packaging occurs in the semiconductor process has evolved, and some of the packaging processes are now done as an extension of front-end manufacturing. Moving forward, packaging architecture and materials are becoming increasingly important, driven by the adoption of heterogenous integration to address demands for more complex functionality and reduced power consumption as well as enabling chiplet integration. In the Packaging Architecture Materials session, we will discuss what kind of standardization our industry requires for copper-copper (Cu-Cu) direct interconnection, hybrid bonding, and panel-level packaging. We will also explore glass substrates as well as standards needed to enable semiconductor assembly and test automation.Our third session recognizes that the semiconductor industry is heading into an era of NetZero, in which quantification of environmental performance can have meaningful financial impact. The methods of measuring and accounting the environmental impact such as carbon emissions and the presence of substances of concern in manufacturing and products are not uniformly consistent across the industry. In order for the semiconductor industry to better navigate and make a positive impact in this arena, a consistent set of standards will be crucial. In the Environmental Sustainability session, thought leaders will present on communicating substance of concern (SOC), reporting of process emissions from factories, as well as lifecycle assessment of materials and substances used in semiconductor manufacturing, including equipment.Last but not the least, we will feature a panel session where we will explore all of these topics in a discussion with our panelists.Trio: Who should attend the Summit and why?Mashiro-san: The Summit is intended for leaders who are interested in these standardization topics to come and engage. Attendees will hear and learn about the issues critical to the future advancements of semiconductor manufacturing, what’s happening to address them, as well as new standards development. Attendee engagement is critical as we want our participants to influence and be able to contribute to the direction of standards development by providing valuable insights to help optimize future factories. To facilitate industry collaboration, we have organized networking events with other stakeholders from suppliers and solutions providers to end customers. The Summit is just one of many compelling reasons for industry stakeholders and thought leaders to come to SEMICON Japan. There are several sessions on many related topics that we are covering in the Global Standards Summit. Ultimately, at the conclusion of the Summit, we expect to have identified lists of critical standards areas, and we would like for those leaders to be able to assign and dedicate resources to these standardization efforts.For more information about the inaugural SEMI Global Standards Summit, please visit the SEMICON Japan 2024 site and register today!Supika Mashiro works as an Advisor for Strategic Planning of Industry Initiative Group at Tokyo Electron Limited.She has been involved in Factory Integration (FI) IFT of IRDS since its inauguration in 2016 and a co-chair since 2017. Her area of interest and involvement encompasses “smart” technology applications in manufacturing equipment, its co-optimization with Fab operation as well as ESH/S (Environment, Safety, and Health/ Sustainability) road-mapping and related industry standard development. For the latter, she has taken a couple of leadership roles in SEMI Standards Program as well as IEC TC/44.Paul Trio is Director of the SEMI Standards program.

With product/die the focus in the test environment, SEMI is developing a suite of standards for the test industry built upon SEMI E183 – Specification for Rich Interactive Test Database (RITdb), which defines a data and event sharing and streaming methodology.

The inaugural CHIPS Research and Development (R&D) Standards Summit will bring together thought leaders from industry and academia across the globe to help shape the future and drive innovation of semiconductor and microelectronics standards.

In January 2022, SEMI Taiwan released SEMI E187 – Specification for Cybersecurity of Fab Equipment. What cybersecurity pain points does SEMI E187 ultimately address?

In Jan, SEMI published SEMI E187, a specification designed to help protect semiconductor manufacturing data. The publication marks the first time that SEMI Taiwan has led the development of an international standard and reflects the vital need for cybersecurity in Taiwan’s semiconductor industry.

At July's SEMI Standards Information & Control North America Technical Committee Chapter Meeting, several ballots passed procedural review and await publication. Among them are the Equipment Data Acquisition (EDA) Standards, which use the Freeze concept to identify a specific set of SEMI Standards.

Even for someone who has been in this industry since the days of the TI Datamath 4-function calculator and the TMS1100 4-bit microcontroller (yes, that’s been a LONG time – the movie Grease premiered the same year!), it is sometimes hard to grasp the scope and complexity of what happens in today’s leading-edge semiconductor gigafabs. In fact, the only way to comprehend the enormous volume of transactions that occur is to consider what happens in a single minute – this is illustrated in the infographic we have labeled “The Gigafab Minute.”* It’s amazing enough to think that a single factory can start 100,000 wafers every month on their cyclical journey through 1500 process steps… and have 99%+ of them emerge 4 months later to be delivered to packaging houses and then on to waiting customers. It’s quite another to realize that all of this happens continuously (24 x 7) and automatically. “How is this possible?” you ask.Well, a big part of the solution is the body of SEMI standards which have evolved since the early 80s to keep pace with the ever-changing demands of the industry. From an automation standpoint, many of these standards deal with the communications between manufacturing equipment and the factory information and control systems that are essential for managing these complex, hyper-competitive global enterprises.A significant characteristic of these standards is that they have been carefully designed to be “additive.” This means that new generations of SEMI’s communications standards do not supplant or obsolete the previous generations, but rather provide new capabilities in an incremental fashion. To appreciate the importance of this in actual practice, consider how the GEM, GEM300, and EDA/Interface A standards support the transactions that occur in a single Gigafab Minute.Starting at 1:00 o’clock on the infographic and moving clockwise, you first notice that 2.31 wafers enter the line. Of course, these are actually released in 25-wafer 300mm FOUPs (Front-Opening Unified Pod), but 100K wafers per month translates to 2.31 per minute. Since these factories run continuously, once the line is full, it stays full. And with an average total cycle time of 4 months, this means that there are 400K wafers of WIP (work in process) in he factory at any given time. This number, and the total number of equipment (5000+), drive the rest of the calculations.GEM (Generic Equipment Model) – SEMI E30, etc.The GEM messaging standards were initially defined in the early 90s to support the factory scheduling and dispatching applications that decide what lots should go to what equipment, the automated material handling systems that deliver and pick-up material to/from the equipment accordingly, the recipe management systems that ensure each process step is executed properly, and the MES (Manufacturing Execution System) transactions that maintain the fidelity of the factory system’s “digital twin.”Every minute of every day, GEM messages support and chronicle the following activities: 240 process steps are completed (i.e., 240 25-wafer lots are processed), 300 recipes are downloaded along with a set of run-specific adjustable control parameters, and 600 FOUPs are moved from one place to another (equipment, stockers, under-track storage, etc.). For each of these activities, the factory’s MES is notified instantaneously.GEM300 – SEMI E40, E87, E90, E94, E157With the advent of 300mm manufacturing in the mid-to-late 90s, a global team of volunteer system engineers from the leading chip makers defined the GEM300 standards to support fully automated manufacturing operations. Starting at 5:00 o’clock on the infographic, the number of transactions per minute jumps almost 3 orders of magnitude, from the monitoring of 900 control jobs across 4000 process tools to the tracking of 360,000 individual recipe step change events. This level of event granularity is essential for the latest generation of FDC (Fault Detection and Classification) applications, because precise data framing is a key prerequisite for minimizing the false alarm rate while still preventing serious process excursions. In this context, more than 6000 recipe-, product- and chamber-specific fault models may be evaluated every minute.Simultaneously, the applications that monitor instantaneous throughput to prevent “productivity excursions” and identify systemic “wait time waste” situations depend on detailed intra-tool wafer movement events. In a fab with hundreds of multi-chamber, single-wafer processes, 75,000 or more of these events occur every minute. EDA (Equipment Data Acquisition) – SEMI E120, E125, E132, E134, E164, etc.Rounding out the SEMI standards in our example gigafab is the suite of EDA standards which complement the command and control functions of GEM/GEM300 with flexible, high-performance, model-based data collection. The EDA standards enable the on-demand collection of the volume and variety of “big data” required from the equipment to support the advanced analysis, machine learning, and other AI (Artificial Intelligence) applications that are becoming increasingly prevalent in leading semiconductor manufacturers. As EUV (Extreme Ultraviolet) lithography moves from pilot production to high-volume manufacturing at the 7nm process node and beyond, the litho process area will become a major source of process data by itself, generating 10 GB of data every minute. This is in addition to the 100 GB of data collected from other process areas. The End ResultThe final wedge (12:00 o’clock) in our infographic highlights the real objective – which is producing the millions of integrated circuits that fuel our global economy and provide the technologies that are an integral part of our modern way of life. Assuming a nominal die size of 50 square mm (typical of an 8 GB DRAM), the 2.31 wafers we started at 1:00 o’clock result in almost 3200 individual chips. But none of this would be possible without the pervasive factory automation technology we now take for granted. So, as you finish reading this posting on whatever device you happen to be using, take a micro-moment to acknowledge and thank the hundreds of standards volunteers whose insights and efforts made this a reality!You may not be responsible for running a gigafab anytime soon, but the SEMI standards used in this setting are no less applicable to any Smart Manufacturing environment. Give us a call if you’d like to know more about how these technologies can benefit your operations for many years to come.Alan Weber is Vice President, New Product Innovations, at Cimetrix Incorporated. Previously he served on the Board of Directors for eight years before joining the company as a full-time employee in 2011. Alan has been a part of the semiconductor and manufacturing automation industries for over 40 years. He holds bachelor’s and master’s degrees in Electrical Engineering from Rice University. For more information on SEMI Standards, please click here.

The arrival of Fan-Out Panel Level Packaging (FO-PLP) appears to be at a perfect time: This technology will leverage processes developed for Three Dimensional Stacked Integrated Circuits (3DS-IC) as well as panel processing technologies developed for industries such as solar panels and large-screen TVs. In this combination, FO-PLP promised the improved performance of 3DS-IC, without the expense. There was just one problem…That problem is the size of the panels to be processed. As different companies developed FO-PLP processes, they chose panels sized to meet certain technical or business goals, or chose a size based on familiarity. So, processes were being developed for more than ten sizes, each of which had one or more companies championing them. For people in the wider semiconductor industry, the development of many processes, each with a unique panel size brought a feeling of déjà vu, reminding them of the 1970s, when each device manufacturer created their own specification for wafer size, forcing them to manufacture their own wafer processing equipment since no external manufacturer was willing to produce tools usable only by a single customer.SEMI responded by developing an industry consensus silicon wafer standard – which described basic parameters, including diameter and thickness – to resolve the issue. Almost overnight the landscape changed, and new tool manufacturers sprung up, enabling the incredible growth that has persisted over more than 40 years.Recently, Cristina Chu (TEL NEXX) presented the state of FO-PLP to the North America Chapter of the SEMI Three-Dimensional Packaging and Integration (3DP I) Technical Committee, suggesting that the Committee develop a single standard dimension that would enable the technology to move into high-volume manufacturing.The Committee began by surveying the industry to determine the interest level in such a standard as well as its contents. A key finding came in response to the question “Would you support a standardized panel size?” Overwhelmingly, over 70 percent of the respondents supporting the idea for the standard, with less than 2 percent opposed. The survey also asked if other parameters should be standardized and, if so, which parameters. Majority responses pointed to edge profile, flatness, and warp, prompting the 3DP I Committee to immediately form the FO-PLP Panel Task Force (TF) to develop such a standard. Chu and Richard Allen (NIST) agreed to chair the TF and respondents to the survey were asked to participate as TF members.The TF initially decided to follow the model of SEMI M1, Specification for Polished Single Crystal Silicon Wafers, and write the document as a purchase specification. The purchase specification would indicate a limited number of mandatory parameters, identified as those that serve as bottlenecks to the development of a FO-PLP ecosystem. Parameters that were not perceived as bottlenecks but might be useful for implementing a FO-PLP process would be included as optional.Working under the SEMI Standards umbrella allowed the TF to take advantage of work done in the development of other standards, without having to recreate it from scratch. In particular, Flatness and Shape were repurposed from SEMI M1, ensuring consistent definitions of these parameters.The TF could not come to consensus on how the other parameters should be categorized, so the decision was made to move the ordering table to a new Appendix as optional.The TF will be balloting its first specification for panel substrate in the upcoming cycle, which opens September 5, 2018 (Cycle 7). The voting is open to all industry experts. Based on the feedback, the task force will continue to refine and otherwise improve the specification by incorporating other parameters that are critical to making FO-PLP a reality.SEMI Standards development activities take place throughout the year in all major manufacturing regions. To get involved, join the SEMI International Standards Program at: www.semi.org/standardsmembership.For more information regarding FO-PLP Panel Task Force activities, please contact Laura Nguyen at [email protected] Allen is a physicist in the Nanoscale Metrology Group in the Engineering Physics Division of the Physical Measurement Laboratory (PML) at the National Institute of Standards and Technology (NIST).

Did you miss the SEMI International Standards Reception at SEMICON West 2018? Not to worry, here are the highlights.SEMI honored two Standards industry leaders for their outstanding accomplishments in developing Standards for the electronics and related industries.Two awards were given recognizing the efforts of each member. The Technical Editor Award recognizes the efforts of a member to ensure the technical excellence of a committee’s Standards. This year’s recipient is Sean Larsen of Lam Research. Mr. Larsen has led the North America EHS Committee and multiple EHS task forces for over a decade. His knowledge of the Regulations, Procedure Manual, and Style Manual, combined with his vast experience in the industry, ensures that complex safety matters are explained in a clear, consistent manner, and ballot authors frequently rely on him for his technical skills in preparing ballots.In addition to co-chairing the North America EHS Committee, Mr. Larsen is currently the co-leader of the SEMI S22 (Electrical Design) Revision TF, the SEMI S2 Non-Ionizing Radiation TF, the SEMI S2 Korean High Pressure Gas Safety TF, and the Control of Hazardous Energy TF.The Corporate Device Member Award recognizes the participation of the user community and is presented to individuals from device manufacturers. This year’s recipient is Don Hadder of Intel. Mr. Hadder has been actively involved in the Standards Program for several years, and currently leads the Chemical Analytical Methods Task Force and chairs the North America Liquid Chemicals Committee. He has successfully re-energized the committee, which is now focused on enabling continued process control improvements for advanced nodes. He recently drove the development of a critical new standard: SEMI C96, Test Method for Determining Density of Chemical Mechanical Polish Slurries, the first document in a series of SEMI Standards that will be devoted specifically to CMP slurry users, IDMs, slurry suppliers, metrology manufacturers and OEM equipment suppliers.Mr. Hadder has worked at Intel for 23 years, where his experience and system ownership has been in Diffusion, Wet Etch, Planar-CMP, Ultra-Pure Water, Waste Treatment Systems, Abatement and Vacuum Systems, Bulk and Specialty Gas, Bulk Chemical Delivery and Planar Chemical Delivery.James Amano, Sr. Dr. International Standards, opened the reception with a few words. He noted that the total number of published SEMI Standards is nearing 1000, and that these documents serve as the backbone of modern day semiconductor manufacturing. SEMI president and CEO Ajit Manocha, speaking at the SEMI International Standards Reception at SEMICON West. Ajit Manocha, President and CEO of SEMI, reminisced how he was an active Standards Member, and how much he got out of SEMI Standards as a young engineer at Bell Labs. He passionately emphasized that SEMI Standards remain critical in this era of new materials and disruptive architectures and processes, calling them the "oxygen of the industry."Laura Nguyen is coordinator, International Standards, at SEMI.