metrology

The Advanced Lithography TechXPOT at this year’s SEMICON West will explore progress in extreme ultraviolet lithography (EUVL), its economic viability for high-volume manufacturing (HVM) and other lithography solutions that will address the march to 5nm and onward to 3nm.As a prelude to the event, SEMI asked Neeraj Khanna, Global Head of the Patterning Customer Engagement Team at KLA-Tencor, a speaker at the TechXPOT, for insights about the readiness of inspection and metrology tools for EUVL applications at 5nm and 3nm. For a full list of speakers and program agenda, visit http://www.semiconwest.org/programs-catalog/lithography-5nm-and-below.Neeraj Khanna, Global Head of the Patterning Customer Engagement Team at KLA-TencorSEMI: In general, how would you characterize the readiness of inspection and metrology tools intended for EUVL applications at 5nm and 3nm? In particular, what are some of the remaining research and development challenges that need to be addressed for each of these nodes?Neeraj Khanna: KLA-Tencor is working closely with its customers to qualify and ramp EUV. Our suite of inspection, metrology and data analytic solutions are being implemented to enable EUV infrastructure readiness including, for example, new reticle and resist qualification, scanner qualification, and EUV ramp preparation. These EUV integration activities require process control systems that support a wide range of applications, including hotspot discovery, lithography modeling, focus/dose process window qualification, reticle print check, mask blank inspection, and process and tool monitoring.As with any major technology inflection, it is critical to understand sources of process variation to enable ramp at optimal yield. For example, stochastics result in random pattern variations, which have a major impact on EUV yield. To manage stochastics, IC manufacturers are deploying process control solutions that support fast modeling of stochastic variations coupled with high-sensitivity, high-coverage wafer defect inspection. Another example is a methodology called hybrid scanner utilization whereby, when EUV scanners are implemented in production, they will only be used for a few layers, while all other layers will be patterned with 193i scanners. This technique requires tighter control and monitoring of overlay budgets.SEMI: How are you able to achieve this tighter control and monitoring?NK: To understand why hybrid scanner utilization requires tighter control and monitoring of overlay budgets, it’s important to outline how this differs from current scanner implementation. For critical layers in current process flows using 193i lithography, pattern layers for a given wafer are printed using the same stage/chuck on the same scanner. The overlay performance achieved using this lithography strategy is called dedicated chuck overlay (DCO). Use of a dedicated scanner and chuck for lithography reduces inter-scanner and inter-chuck distortion effects, resulting in DCO overlay error of less than 1nm. When EUVL is first implemented in production, it will be used for a few layers – likely, cut masks and contacts with eventual migration to metal 1 layers. All other layers will be patterned with 193i scanners. This hybrid scanner operation eliminates any possibility of using a dedicated scanner and dedicated chuck to support tight overlay performance specifications. Instead, fabs will be forced to optimize mix-and-match overlay (MMO), with the overlay performance obtained using different scanners for printing different layers on a given wafer.With overlay specifications for advanced DRAM and logic at ~2.5nm, fabs will need to implement strict 193i-to-EUV scanner matching strategies or risk consuming 60 to100 percent of the overlay budget on just MMO. To achieve tighter overlay control and monitoring required for MMO, fabs need to implement dense, in-field overlay error measurements that feed into scanner fleet management systems. KLA-Tencor’s ATL™ overlay metrology system supports a high measurement speed and the use of small in-die targets, enabling dense in-field overlay measurements with high accuracy. Our 5D Analyzer® data analytic and management system includes scanner fleet management capability that enables automatic product-based corrections to minimize MMO error, helping fabs reduce the risk to yield loss associated with a 193i-EUV mixed scanner implementation. SEMI: What other challenges do you see coming to the fore at 5nm and 3nm?NK: Overall, the 5nm and beyond design nodes will face challenges associated with new lithography technology, potential new device structures and smaller pattern pitches. IC manufacturers will require process control solutions that not only identify process windows, but also monitor patterning parameters and defectivity at multiple points to identify process shifts. To monitor dynamic processes at these advanced nodes, inspection and metrology tools will need to have both sensitivity to critical parameters/defects and robustness to process variation in order to provide IC engineers with smart feedback for efficient control of their processes.SEMI: Could you elaborate on what will be required to monitor patterning parameters and defectivity at multiple points? How different will the techniques be at 5nm/3nm vs. at say, 7nm or 10nm?NK: As an example of monitoring at multiple points, consider the transition to EUV lithography. With EUV, the cost per scan goes up dramatically. Thus, IC manufacturers will monitor parameters at multiple points to maximize yield and minimize risk: EUV reticle qualification requires inspection and metrology throughout the entire flow from mask blank manufacturing, to the mask shop, to the IC fab. For the advanced design nodes associated with EUV, wafer qualification requires monitoring and control of wafer defectivity, shape and geometry throughout the wafer manufacturing process. It also requires control of fab incoming wafer qualification while ensuring that fab-wide processes are meeting defect and shape standards necessary for printing smaller feature sizes. EUV resist characterization and qualification requires comprehensive lithography simulation, wafer defect inspection, and film thickness and uniformity measurements to help reduce development time and prepare the litho stacks for production ramp. As EUV scanners are ramping, fabs are faced with finding any unknown particle sources within the new scanner chambers. This situation is driving the need for tighter and more frequent PWP (particles per wafer pass) chamber monitors to ensure scanner cleanliness. In addition, EUV scanner qualification requires reticle front and backside particle checks, and hotspot discovery and process window qualification using optical wafer defect inspection and e-beam review. EUV process monitoring encompasses overlay error monitoring, focus/dose monitoring, critical dimension (CD) and 3D device shape monitoring, and continuous process window monitoring. EUV inline defect monitoring and tool monitoring is important for reducing baseline defectivity in the litho cell for faster ramp, and for early identification of litho excursions in production. A critical part of this monitoring strategy is inline after develop inspection (ADI) monitoring, which is defect inspection on patterned wafers after printing and development of the resist ADI. Inline ADI innovations that find yield-critical defects allow fabs to reduce process issues, prevent at-risk wafers early in the process, and enable rework when excursions are found in production. As with past technology transitions, the implementation of multiple monitoring steps as part of a comprehensive process control strategy will be critical for a fab’s successful ramp of EUV.Debra Vogler, SEMI

New metrology and inspection technologies and new analysis approaches made possible by improving compute technology offer solutions to finding the increasingly subtle variations in materials and subsystems that meet specifications but still cause defects on the wafer. More collaboration across the supply chain is helping too. SEMICON West programs on materials and subsystems will address these issues. New metrology approaches needed to deal with process margin challenges As device process margins shrink and subtler materials variations cause unwanted deviations, the need for better monitoring of both surface and sub-surface material variations is driving a trend towards “metro-spection” – the convergence of metrology and inspection. “Device process margins have eroded to the point that traditional metrology strategies and techniques are no longer viable for controlling yield and parametric performance,” says Nanometrics Vice President Robert Fiordalice, who will speak in the materials program at SEMICON West. “Limited sampling capability, low throughput, insufficient sensitivity or the destructive nature of the techniques can often become problems. What’s more, deviations in material characteristics are not always determined by the initial quality of the material, but often arise from variations during the integration of the materials.” One new type of inline tool or line monitoring technology is Fourier Transform Infrared (FTIR) spectroscopy, traditionally used in quality control or tool characterization. Better sensitivity and higher throughput now enable rapid analysis and feedback for on-the-fly detection of subtle deviations in film properties that may compromise device performance or yield. More advanced analytics will help extract new information from old metrologyMore expensive metrology may not be required to identify subtle variations in in-spec materials that cause wafer defects. Today’s advanced compute capabilities now enable more sophisticated analysis of existing data and the identification of small but significant variations in raw materials and finished goods. The figure of merit (FoM) values presented in certificate of analysis (CoA) reports miss subtle variations in raw material properties. Of particular note is the reduction of molecular weight distributions to a mean, and standard deviation, whereas variations in the tails are associated with pattern defects. Advanced compute capabilities now allow the industry to step beyond the FoM in favor of more holistic measures, enabling predictive analysis of resist chemical variations associated with specific pattern defects. Source: JSR Micro“We often don’t need to find a new measure, but just a new way of looking at what we measure now,” says Jim Mulready, vice president of global quality assurance at JSR Micro. Mulready will speak in the SEMICON West program on materials defectivity issues. “The certificate of analysis reduces multiple measurements to a single figure of merit. But if we ignore all that raw data, we miss a chance to learn. One of our sayings in quality is ‘Customers don’t feel the average, they feel the variation.’ In many electronic materials, the quality of the raw material can have a big impact on the final performance, but the types of analysis needed to look at the tails of the distribution of these measures (such as molecular weight) in detail used to be really hard to do. Now it’s becoming increasingly straightforward and affordable.” Mulready says tools now available in the data processing sector enable the identification of subtle variations in materials that can cause defects on the wafer. These tools use methods like detailed subtractions of chromatography curves of polymer raw materials or analysis of tails of distributions of molecular weights. “Our job now is to drive these kinds of more sophisticated data analysis back into our chemical supply chain as well,” says Mulready. “We must work more closely with our suppliers to integrate their raw materials into our products. The reason the JSRs of the world exist is as a safety valve to reduce the variation from the chemical industry before it gets to the fab.”Continued collaboration with equipment suppliers required While the industry has been talking about the need for tighter collaboration between materials suppliers and equipment manufacturers for years, it still doesn’t always happen. “The material supplier and the equipment maker are tied together like kids in a three-legged race when we deliver an integrated system for consistent on-wafer performance,” says Cristina Chu, TEL/NEXX director of strategic business development, another speaker in the materials program. “When we introduce changes to the tool hardware, we need to make sure it doesn’t upset the system. Similarly, we need the material supplier to send a bottle over when a new chemistry formulation is under development. If a new chemistry runs into problems in the field, it will take much more time for both of us to fix it at the customer site. The toolmaker can provide a slightly different perspective on applications, while being more objective than a customer on how the formulation performs compared to earlier versions.”Regular and ongoing collaboration between chemistry suppliers and toolmakers enables the highest quality system solution to reach the customer. Chu notes that her team tries to maintain consistent collaborations with material suppliers across changes in organizations as the business environment changes. “For consistent on-wafer capabilities, we need a consistent collaboration process with chemistry suppliers. We need to meet with materials providers at a regular cadence throughout their development process. We need to check back with them as we scale up results from the coupon to the wafer level and to work out the kinks in the integrated solution together. The quality and consistency of our combined performance at the customer depends on ensuring the quality and consistency of our development and evaluation process as well.”Fabs and subsystems suppliers look to pilot data sharing program to improve process margins With ever tighter process margins, subtle variations in parameters that don’t appear in the specifications are also compromising results on the wafer, and neither the fab nor the supplier alone has the full information needed to improve performance. To help, a SEMI standards group is developing a protocol for a pilot program to standardize and automate some data sharing.The fab knows that performance is best with a particular parameter value, and knows when performance fluctuates, but often faces a black box problem with no way of knowing what exactly is wrong. In the rush to get the tool back up, the fab engineers may not get around to emailing the supplier about the issue for some time. The subsystems supplier, on the other hand, may know the cause of the variation, but likely has no way of knowing the critical parameters or ideal target values for the fab’s process. “In order for engineers to have constructive conversations about how to improve performance, we all need to exchange more information,” says Eric Bruce, Samsung Austin diffusion engineer, and co-chair of the SEMI Standards initiative addressing the issue, who will speak in the subsystems program at SEMICON West. A potential solution could be to create a standard and automated process to share particular data, agreed to in the purchasing contract, whereby the subsystems supplier shares more information about their parameters with the fab, and the fab in return gives feedback on what parameters work best to drive improved performance. The best place to start will likely be on parts that do not contain core yield-related IP, but where usage and lifetime information is useful.“We’re looking for people to participate in a pilot program to work together with suppliers to try sharing some information to improve performance,” says Bruce. “There’s a lot of this sharing in the backroom anyway, but this could make it fast and automated, and make everyone’s engineering job a lot easier.”Paula Doe, SEMI

What’s next for smarter, more connected electronics manufacturing - Part 3 The fast-maturing infrastructure now enabling analysis of exponentially larger data volumes brings the microelectronics industry to an inflection point, where the winning companies will be the first to master the use of this data to solve the industry’s emerging challenges. SEMI expands its coverage of these vital issues with a Smart Manufacturing Pavilion and three days of talks SEMICON West, July 10-12 in San Francisco. While deep learning is starting to be applied to image recognition for wafer inspection, it is also being considered for sequential pattern recognition in order to evaluate equipment parameter traces. The next emerging applications will start to use those learned patterns to predict outcomes, and then use those predictions to automate process control. One early application of deep learning is IC process development. “People don’t think of research and development as the first place to automate, but it’s where applying our digitization and simulation has first had impact,” says David Fried, Coventor vice president of Computational Products. He noted that insertion is easier in the lab than in the fab. Technology at 10nm and beyond is now so complex that companies at the leading edge must use process modeling to understand the effect of process variation on their designs. Learning cycles can now be accelerated during development by simulating 10,000 digital wafers instead of running 25 actual wafers during screening, Fried says. Applying structured analysis and machine learning to the data simplifies optimization across the 500 or more interrelated process steps. Coventor has recently introduced a statistical analysis package that aids the design and analysis of process variation experiments by using large volumes of data from its models. Fried says these models are next being used to accelerate the yield ramp in manufacturing. Digital simulation also could speed development of high-mix, lower value products While digital twins are best known for their use in complex, high value products like jet engines, the simulation technology could also enable the electronic manufacturing services (EMS) sector to reduce the time, cost and risk of developing its high mix of products. “The EMS sector’s use of digital twins will be vital for it to smooth the move of CAD/CAM digital design data for so many different products into manufacturing, and to accelerate validation testing of designs and products by doing more of it in the virtual world,” says Dan Gamota, vice president of Engineering and Technical Services at Jabil. Gamota also highlights the push for traceability from the automotive and healthcare markets, where the digital models could be used to quickly assure that the design was built exactly as specified. “In the past year, traceability has evolved from just ‘nice to have’ to ‘how to achieve,’” he adds. “Companies are expecting it, but aren’t willing to accept the cost and risk of doing it alone. We need the community to discuss realistic implementations, identify the most critical elements and bring together the ecosystem partners to build baseline reference architectures for key digital building blocks. The community also needs to assure the reliable flow of data among the electronic manufacturing segments from semiconductor to OSAT to EMS.” Predictive maintenance and virtual metrology applications could mature in next few years While predictive maintenance initially seemed a likely early application of machine learning in factories, it remains a challenge for the electronics sector. “The difficulty is that it’s not clear where to get the most bang for the buck,” says Tom Ho, president of BISTel America, noting that it may make the most sense to track the failure performance of a single expensive part, like an electrostatic chuck, since predicting the failure performance of a whole complex system like an etcher is much harder. “Collecting enough data from all failure types, including especially the rare events, is difficult unless you have a long history of a lot of tools,” adds Doug Suerich, PEER Group product evangelist. “The gain from collecting performance information from many tools across the industry could be big, but many companies still need to overcome concerns around exposing their IP.” Another big opportunity for prediction is virtual metrology – predicting the wafer outcome from the process or sensor data with enough accuracy to replace the physical metrology. “Virtual metrology is improving, and since metrology can be slow and expensive, any reduction could mean a huge potential savings,” says Suerich. “But it is still seen as too scary for many companies. Two to three years from now, companies will expand the practice from lower risk areas into processes that require more confidence in the results.” Moving beyond prediction to automated control needs digital models Once the results are predicted, the model can be used to control or automatically optimize a process and enable the system to learn by itself, usually by reinforcement learning on a digital model. The model can then independently make adjustments to optimize the manufacturing process. “Automated process development is getting close now. Instead of smart guys turning the knobs, deep learning is automating the smart tuning,” says Suerich, suggesting the industry could see widespread adoption in as little as two to three years. This type of machine learning needs a good digital model, and masses of data for learning. One approach uses human experts to build a physics-based model of the clearly understood parts of the process, then turns to deep machine learning to optimize the lesser-understood variables. The alternative, the data-first approach, runs a computer algorithm to suggest the solution purely from data, without human input, and then relies on the human to evaluate the usefulness of the results. Modeling digital twins of wafers could enable automated process control, chamber matching, and fleet matching, says Fried. If every wafer had its own virtual twin with all the upstream metrology and structural information needed to make equipment control decisions, it could feed forward that information to enable the seamless transition from one step in the process to another based on understanding their complex interrelationships. This could potentially improve uniformity across wafers and equipment, and reduce the need for metrology, he argues. Moving metrology sensors into the chamber will also require model-based algorithms to enable dynamic process control in close to real time, says Fried. These algorithms will be needed to acquire, parse, and process the data at high speed, and then to choose how to adjust the controls. “There will be a model behind collecting and interpreting the metrology data,” he notes. “That’s a really rich vein for improvements in process control.” “The end goal is to collect equipment data in real time, analyze it with AI, and send back controls to optimize manufacturing processes,” Jabil’s Gamota says. “This requires a robust architecture for communication between equipment and consistent formats for data collection and analysis. But the cost and complexity of this heavy lifting is too great for any one company to do alone. We need a consensus-based architecture for ingesting, analyzing and acting on the data.” SEMI tests data transfer protocols, benchmarks best practices SEMI is launching a smart data project to identify the various data transfer protocols needed for inter-company communications. The project will feature a proof-of-concept model in a development fab to produce verifiable results so SEMI can better understand how different approaches meet member needs. SEMI’s smart manufacturing technology communities and the Fab Owners Alliance are also benchmarking current smart manufacturing practices in the microelectronics industry to help SEMI members better understand the path forward and potential return on investment. Speakers over all three days at SEMICON West addressing these issues include Active Layer Parametrics, Applied Materials, Applied Research Photonics, ASML, Bosch Rexroth, Cimetrix, Coventor, ECI Technologies, Edwards Vacuum, Final Phase Systems, GE Digital, Infineon, Jabil, Lam Research, Osaro, Otosense, PEER Group, Qualcomm, Rockwell Automation, Rudolph Technologies, Schneider Electric, Seagate, Siemens, Stanford University, TEL, TIBCO Software. See semiconwest.org. What’s next for smarter, more connected electronics manufacturing - Part 1 What’s next for smarter, more connected electronics manufacturing - Part 2 Paula Doe, SEMI

What’s next for smarter, more connected electronics manufacturing - Part 2The fast-maturing infrastructure now enabling applications for big data and artificial intelligence means disruptive change not just at individual companies but also in data connections among companies across the microelectronics manufacturing value chain. SEMI checked in with some leading players on the changes they see coming in the next several years for this article series. The trade group is expanding its programming on smart manufacturing to address these industry-wide developments at SEMICON West, July 10-12 in San Francisco.“The ramp of EUV, and the smaller geometries and smaller process margins, will drive an exponential increase in the amount of metrology data to manage,” says Neal Callan, ASML vice president, Silicon Valley. Callan notes that moving to multibeam e-beam inspection will increase data volume from megabytes per second to gigabytes per second and from thousands of data points to millions of data points. “The process is so tight and the margin so small that stochastic variation, or noise, becomes more dominant – at least it’s noise until we can learn to understand and control it. And understanding and controlling this variation will be key to delivering 5nm patterning,” he says.Single-beam e-beam inspection is already driving large increases in data as engineers extend the slow technology to broad, high-speed defect metrology applications by more intelligently instructing the system where to look for problems. Callan says ASML is now using the scanner data on wafer focus, alignment and leveling. The company is also using the computational lithography model from the design to identify the smallest process windows in the pattern that are most likely to see problems. The model then quantifies the number and significance of those instances.“The collection of all this diverse data means that tools will need to be plug-and-play so all tool data is instantly available to all systems and software,” says Doug Suerich, PEER Group product evangelist. “We need tools that can be discovered automatically by the network so it can start slurping up data immediately. The adoption of the Interface A (EDA) standard is accelerating and fabs are starting to ask for it. The proliferation of sensors also needs to self-discover. If you are going to add thousands of new sensors into a facility, you can’t afford a time-consuming integration process.”“We are now seeing that engineers are greedy for more data – if they can get the data, it’s becoming a need-to-have,” adds Tom Ho, BISTel America president. “Getting more data from more sensors, from the sensors on the tool that are not being fully utilized, and from untapped data sources like vibration is another big coming opportunity.” Process complexity drives demand for feed-forward between silos with computational models ASML co-optimizes its scanner process with etch and reticle process steps. Source: ASML In addition to the drive for trace-back of data, the increasing complexity of interrelated processes is also driving demand for feed-forward of data. “Feed-forward is becoming more important,” notes Ho. He points to the example of 3D NAND features, now getting so deep that identifying the layer being measured is a challenge unless the signal at the step before can be recognized. “We need partnerships with our peers to understand how to take advantage of the sensors they use, integrate them with our data, and then feed-forward corrections to the other systems,” concurs Callan. “To drive the best CD uniformity and overlay, we need to co-optimize litho and etch,” agrees Henk Niesing, ASML director of product management. He notes that the company is working with etcher makers to measure the overlay and CD, decompose the finger prints, and then use models to steer automated control that best adjusts both the scanner and the etcher. ASML is also working with Zeiss on co-optimization between the scanner and the reticle to make even higher-order corrections by locally modifying the reticle.These higher-order corrections, applied on each exposed field, drive the need for even more data, and at higher speed but without higher cost, notes Jan Mulkens, ASML senior fellow. These corrections increase demand for computational metrology, which combines various metrology sources with physics and deep learning models trained on real data to predict and control process results in real time. “We’re working on computational metrology to ideally use all the knobs we have in the fab,” he says. So far this effort has largely involved linking data between two companies. More consistent data formats would enable data exchange to be extended to more companies. “The software versions also need to be managed for upgrades so they still match after one party updates the system on its tool,” notes Niesing. Speakers on these issues of smart manufacturing and data handling at SEMICON West include Active Layer Parametrics, Applied Materials, Applied Research Photonics, ASML, Cimetrix, Coventor, ECI Technologies, Edwards Vacuum, Final Phase Systems, GE Digital, Infineon, Jabil, Lam Research, Osaro, Otosense, PEER Group, Rockwell Automation, Rudolph Technologies, Schneider Electric, Seagate, Seimens, Stanford University, TEL, TIBCO Software. See semiconwest.org.What’s next for smarter, more connected electronics manufacturing - Part 1What’s next for smarter, more connected electronics manufacturing - Part 3Paul Doe, SEMI

The Scaling Technologies TechXPOT at this year’s SEMICON West (Scaling Every Which Way! – Thursday, July 12, 2:00pm-4:00pm) will explore traditional scaling as the industry marches toward 3nm and beyond, as well as technologies that enable 3D architectures, die stacking, and interconnect scaling. The session will also provide an update on how the various players (foundry, IDM, fabless, and application developers) are jockeying for innovation leadership. As a prelude to the event, SEMI asked Priya Mukundhan, director, Technology Development and Applications, at Rudolph Technologies, and a speaker at the TechXPOT, to provide her insights into challenges associated with metrology and inspection.For a full list of speakers and program agenda, visit http://www.semiconwest.org/programs-catalog/scaling-every-which-way. Priya Mukundhan, director, Technology Development and Applications, Rudolph TechnologiesSEMI: What are the key challenges that need to be addressed to provide the kind of metrology and inspection solutions that will be needed by the industry as scaling – in all its forms (e.g., traditional, 3D ICs, interconnect, and different transistor architectures) – is pursued at 5nm and then at 3nm? Priya Mukundhan: With respect to metrology needed to scale FinFETs, the following will be key: Gate critical dimension (CD) at the fin sidewall, gate height, gate profile Fin CD, height and profile Dopant profiles Stress measurement in the fin Composition in thin film and interface These challenges are currently being handled using in-line CD solutions, CD scanning electron microscopy (CD-SEM) and CD atomic force microscopy (CD-AFM), along with optical critical dimension (OCD) measurements. There is no single technology that can take all of these measurements, and determining the right solution is application-dependent[1].Issues associated with inspection and scaling include the following: Bright-field inspection lacks the sensitivity to detect defects smaller than those found at the 20nm node Detecting defects that are 5nm or smaller is achieved using electron beam inspection tools, but these single-electron beam inspection systems are prohibitively slow and cannot meet the high-volume manufacturing (HVM) requirements for defect inspection Buried defects Void detection in 3D SiP structures, front and backside inspection Sidewall crack detection in packaging SEMI: Can you provide a summary of the R D roadmap for metrology/inspection tools that you see emerging in order to get to 3nm? PM: Hybrid metrology is currently in use, especially for CD metrology. To support the development efforts, techniques that provide complementary information as well as those that eliminate uncertainties will be required. Researchers at imec[2] have started exploring technology combinations to gain insight into how new structures function. Some of the findings in imec’s study include the following: The combination of transmission electron microscopy (TEM) and scanning probe microscopy (SPM) provides a unique approach of imaging combined with a functional analysis capability In situ SPM could potentially determine composition (SIMS) as well as functional properties (electrical) Fast Fourier transform scanning spreading resistance microscopy (FFT-SSRM) is a novel technique that measures carrier profiles in semiconductors. This overcomes the current SSRM limitations of signal distortions due to parasitic resistances while measuring on small volumes such as FinFET and nanowires Multi-electron beam inspection can be used for HVM for sensitivity to smaller SEMI: How will metrology and inspection be impacted beyond 3nm? What kinds of tools will be needed by that point in time?PM: There are several different transistor options that have been identified by leading edge wafer fabs and consortia looking beyond the 5nm node roadmap[3,4]. Some of the options on the table include the following: 1) Extension of the current FinFET in the form of gate-all-around FET2) Creating them with new materials by adding ferroelectrics (e.g., negative capacitance FET, or NC-FET) 3) Complementary FET4) Vertical nanowires and nanosheet FETsThese possibilities bring new challenges and require characterization at the material level. Also, the industry as a whole will have to redefine what it means to do composition at the nanometer level. This could be the beginning of a trend towards array-based metrology, i.e., measurements on an array of devices to gather statistically significant data[2].Regarding metrology needs at 3nm, it is too early to determine what kind of tools would be needed only for R D and how many of them would need to be extended to high-volume manufacturing (HVM). From an inspection perspective, there will be a continued migration towards computer aided design (CAD)-based inspection, as well as having the ability to deal with large image data sets (petabyte, big data). Furthermore, inspection algorithms should be improved, along with better staging for better image stitching.References Bunday, E. Solecky, A. Vaid, A. F. Bello, X. Dai, “Metrology capabilities and needs for 7nm and 5nm logic nodes,” Proc. Of SPIE, Vol. 10145, 101450G, pp. 1-41, 2017. Imec roadmap and imec magazine. Intel roadmap. https://semiengineering.com/transistor-options-beyond-3nm/ Debra Vogler, SEMI

This year’s Advanced Lithography TechXPOT at SEMICON West will explore the progress on extreme ultra-violet lithography (EUVL) and its economic viability for high-volume manufacturing (HVM), as well as other lithography solutions that can address the march to 5nm and onward to 3nm. Several session speakers offered their insights into the readiness of EUVL for 5nm and how other lithography solutions will enable 3nm. See the full list of speakers and program agenda at http://www.semiconwest.org/programs-catalog/lithography-5nm-and-below.Diverging viewpoints on EUVL readiness for 5nmMike Lercel, Director of Strategic Marketing at ASMLASML expects its first customer to start volume manufacturing with EUV at the 7nm logic node and the mid-10nm DRAM node in the 2018/2019 timeframe. “EUV will replace the most difficult layers that require multiple patterning, and many layers will continue to be allocated to immersion tools for the foreseeable future,” said Lercel. “For the 5nm logic node, more layers are expected to migrate to EUV.”Three ASML customers have early-access versions of the next-generation TWINSCAN NXT:2000i for the development of advanced logic and DRAM nodes. “This system delivers 2.0nm cross-matched on-product overlay, achieved through several hardware advancements,” noted Lercel. “It is also significant because this mix-and-match use with EUV features a significantly different hardware platform.” TWINSCAN NXT:2000i features a new alignment sensor and improved wafer table flatness, endurance, and clamping mechanism to enhance matching to EUV.ASML has achieved good industrialization progress of its pellicle, with tests confirming that pellicles can withstand 245W source power and an offline power lifetime test indicating 400W capability. Compared to the 7nm logic node, the requirements for EUV masks will become tighter at 5nm, but Lercel noted that ASML sees good progress with the industry infrastructure to support 5nm in areas such as reducing mask blank defects. “We will continue to improve pellicle transmission for enhanced throughput, but there are no fundamental changes in pellicle requirements for 5-3nm logic nodes. We see no infrastructure showstoppers for the introduction of EUVL at the 5nm node.”Stephen Renwick, Director of Imaging Physics at Nikon Research Corporation of AmericaRenwick said that the 7nm logic node is expected to be fabbed mostly using 193i lithography. “EUV will struggle to be ready for 5nm, limited by yield issues caused by stochastic effects in the resist,” said Renwick. “Ready or not, though, it will be used.” Renwick suggests that introducing multiple-patterning with EUV may be needed but would increase costs. “193i lithography will continue to be used with quadruple-patterning and in combination with other techniques – there is no single solution.”Figure 1. Normalized cost/layer vs. lithography method. SOURCE: Nikon Research Corporation of America When choosing between immersion lithography and EUV for different customer segments at 5nm, Renwick noted that the cost depends on the layer. “Some time ago, we calculated that the costs of either 193i triple-patterning or 193i SADP with two cuts were roughly equal to single-patterning with EUV,” explained Renwick (Figure 1). “That agreed with chipmakers' public estimates and meant that the choice of lithography method depended more on the performance tradeoffs involved, such as 193i's better line-edge roughness. At the 5nm node, we are probably faced with quad-patterning from 193i, double-patterning from existing EUV tools, or single-patterning from as-yet undelivered high-numerical aperture (NA) EUV tools.” Renwick believes that the competition between low-NA EUV double-patterning and 193i quad-patterning will be similar to the current situation (i.e., comparison of 193i triple-patterning or 193i SADP with two cuts vs. single-patterning with EUV), but for high-NA EUV tools he believes it's too early to say.Other challenges Renwick sees on the horizon for EUVL at 5nm are stochastic effects in EUV resists. “They cause yield problems on contact arrays and unacceptable line-edge roughness on line/space patterns,” said Renwick. “It's unlikely that these effects will go away without increasing the litho dose, which will further challenge throughput performance.” He also questions whether EUV pellicles, though under development, will be “ready for prime time.”Harry Levinson, Sr. Director of Strategic Lithography Technology and Sr. Fellow at GLOBALFOUNDRIESLevinson said additional fundamental engineering work is needed to ready EUV lithography for 5nm. “Among the top problems are stochastics-induced resist defects, which increase significantly as dimensions shrink below those for 7nm,” explained Levinson (Figure 2). “Higher exposure doses will be required to address these issues related to stochastics at 5nm, which will require higher source output” (than 7nm).Levinson said there will be greater motivation to use EUVL at the 5nm node vs. at 7nm to offset the large number of exposures associated with 193nm immersion multiple-patterning solutions. “The primary application of EUV lithography at 7nm will be for contact, via and cut layers,” Levinson noted. “It will be important to enable EUVL for metal masks at the 5nm node, which increases the need for an ample supply of very low defect EUV mask blanks.” Levinson added that the 7nm node is already stressing defect inspection capabilities, and no actinic defect inspection system is yet available for patterned masks. “This situation becomes more problematic with widespread application of EUVL to metal layers.” Mask development for 5nmChristopher C. Progler, CTO Strategic Planning at PhotronicsProgler said that the basic infrastructure for delivering EUV masks is available, especially for dark field layers and near in nodes. “The interconnected or more open frame patterns will need refinements to the processes and two to three nodes out will need certain new infrastructure,” said Progler. Overall, the main challenges for initial insertion are about creating a cost-effective and rapid-turn EUV mask process, he said. “The industry can certainly deliver EUV masks in some form. It is more a question of doing it efficiently and productively to match the stated value proposition of EUV over other lithographic methods. We don’t want a pick two of ‘cost, cycle time, capability’ sort of mask solution.” More specifically, Progler explained that after the initial EUV mask development for 5nm focused on contacts and block layers, the major push for N5 switched to delivering single-exposure EUV metal patterning as early as possible. “This has opened some new challenges for masks given the resolution, critical pattern density and tight pitch defect requirements of the re-aggregated single-layer metal mask designs,” said Progler. “For example, on the resolution side, we are accelerating the insertion of higher dose photoresists and also driving patterning module improvements in CD control, mask LER and sidewall angle.” Progler added that at N5, the mask 3D structure itself – including the sidewall – will have a greater impact on lithography because it is tied to stochastic error rates on the wafer.“Reliable, wide-area metrology for some of these 2D and 3D mask parameters is currently hard to come by. We may see an evolution of the blank structure at some point in N5, including hard mask options for pattern stability and expect earlier insertion of EUV mask process correction with model-based hot spot detection and rule checking as well. We also hope mask-scanner dedication is not needed, but there are some indications process sensitivity may push us earlier in this direction.” He added that to reduce metal layer defects, more attention needs to be devoted to advanced repair and model-based validation. “We are, unfortunately, still in a situation of blurry vision and high native defect counts alongside possible in situ contamination during mask changes.” Figure 2. Resist stochastics-induced defects. Graph courtesy of Peter DeBisschop, imec; SOURCE: GLOBALFOUNDRIES Progler pointed out that, with the advent at 5nm, metal masks will require some level of actinic blank inspection for yield, increasing the cost of an already expensive mask technology. “So, unless we want to contend with double and triple photomasks’ starts to deliver a single metal layer, it will be very important to tighten the multi-sensor inspection, defect abatement, and repair loops,” said Progler. He does see some clouds forming around high-volume manufacturing pellicles for metal layers. “This remains an open question, mainly for thermal and materials reasons, not to mention cost and cycle time,” Progler said. “We may be pessimistic, but we do not see an HVM pellicle solution converging in the required timeframe, which means leaning even more on a wafer-level inspection in the validation loop.” He believes that streamlining validation will be a differentiator. “I can imagine one losing most of the EUV cycle time benefits by endlessly circling masks around if this is not done well.” How does the industry get to 3nm? ASML plans to ship its first high-NA EUV prototope/pilot systems between 2020 and 2023 to support 3-2nm process development. “System designs are now being finalized and the platform is starting to come to life,” said Lercel. ASML supplier ZEISS is building a high-NA cleanroom for optics production. ASML believes that EUV, high-NA and DUV systems will be used together at the most advanced nodes and is designing to account for this mixed environment. “As chipmakers drive toward smaller geometries in the most advanced nodes like 3nm, they face unprecedented challenges in devices and materials. This will make the process control requirements even more challenging.” ASML is tackling these challenges with its YieldStar metrology platform, e-beam metrology (HMI) and computational lithography solutions that are designed to expand the process window, enhance process control, and improve patterning defect detection. “This ‘Holistic Lithography’ approach will become increasingly important to ensure throughput and yield at the most advanced nodes.”Levinson said that the issues he projects for 5nm will need to be addressed further at 3nm. “The challenges associated with resists at 3nm dimensions are such that it isn’t clear that chemically amplified resists will be capable of meeting requirements,” said Levinson. “If true, we would be seeing the most significant change in resist platforms in a quarter of a century. Potentially cost-reducing technologies such as directed self-assembly (DSA) are always welcome, but EUVL will be the lithographic workhorse through the 3nm node, and likely beyond.”At 3nm, mask makers will confront the realities of higher EUV NA tools. “We will need to implement thinner mask absorbers, new films, and perhaps hard masks,” Progler said. “This puts us in a new materials regime for masks, and history has shown us the mask industry takes a long time to refine processes and tools for new mask materials.” He explained that the small scale of the mask ecosystem and the small number of large suppliers available to address the challenges accounts for this lengthy time frame. Still, looking ahead, Progler noted that Photronics has already done a few studies on the impact of proposed half-field, high NA anamorphic optics on masks. "We uncovered some challenges that need to be addressed, particularly at boundaries and within the overall mask flow,” said Progler. As mask resolution continues to scale down, the industry will need fundamentally higher resolution mask making and inspection processes, requiring next-generation multi-beam mask writing and electron beam inspection, he explained.At 3nm and below, Progler noted that the metrology needs for masks, while not as severe as that for wafers at these nodes, will test the mask equipment infrastructure in ways that could challenge the relatively small mask industry. “Of course, EUV multi-patterning comes into play as well, and with that, the SRAF sizes will drop below 20nm, requiring an asymmetric compensation over a much wider influence area than the OPC people are used to considering.” With EUV multi-patterning, Progler explained that it will be increasingly important to match or pair EUV masks and to consider how 3D effects and stochastics will drive new technology to enable new requirements for high-speed metrology and simulation components. “All the justifiable hand-wringing over EPE with ArF multi-patterning today gets introduced to the EUV scene when masks are ganged together to make a single device layer,” said Progler.Debra Vogler, SEMI