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Emerging applications powered by 5G and artificial intelligence (AI) are expected to be a boon to the semiconductor industry, but only once chipmakers overcome a key challenge: Architecting chips that meet the exacting performance, power consumption, size and cost requirements of devices for mid- to high-end applications. One technology – heterogeneous integration – promises to meet these demands and help drive future leaps in semiconductor innovation in the post-Moore era. To help the industry better grasp the technology challenges and business opportunities associated with deploying highly integrated chip and packaging technologies, SEMI and AI on Chip Taiwan Alliance recently gathered industry leaders from organizations including ASE, Unimicron, Dialog Semiconductor, Cadence and AITA to discuss technology trends and the vital importance of building a cross-industry exchange platform to advance next-generation manufacturing processes critical to heterogeneous integration. Following are key takeaways from the forum, Heterogeneous Integration Enables 5G and AI. Overcoming Heterogeneous Integration Technology Challenges Key to Advances in Taiwan High-End Semiconductor Manufacturing The introduction of the Heterogeneous Integration Roadmap (HIR) by the International Technology Roadmap for Semiconductors team in 2016 was an important first step, Dr. C.P. Hung, Vice President of ASE Group, noted in his opening remarks. The HIR is designed to stimulate pre-competitive collaboration to advance heterogeneous integration technology development and accelerate electronics innovation. The roadmap provides a long-term vision for the electronics industry, identifying future technology requirements and potential solutions. Today, the HIR working group focuses on high-performance computing (HPC), 5G and other leading-edge technologies.Dr. Hung predicted that heterogenous integration will reshape traditional collaborations between the semiconductor ecosystem and supply chain in order to clear I/O bottlenecks that hamstring high-performance applications. The retooled industry connections will also need to enable high I/O pin counts, ultra-thin devices, and high-frequency signal shields. In an important step forward, the chip industry today is developing a platform that enhances wafer-level advanced packaging services and deepens cooperation with Oversea Assembly and Testing (OSAT) and substrate supply chain partners. Overcoming the current limits of IC substrates – the connection between IC chips the PCB – is one key for heterogeneous integration technology to flourish, said Dr. Yu-Hua Chen, Vice President, Carrier SBU, RD Division of Unimicron. He noted that the industry must tackle limits to PCB thickness, substrate density, fine pitch and automation to meet the needs of high-end packaging customers. Another barrier the industry must be surmounted is to make the currently inscrutable confidentiality requirements for patents of foreign materials – key to improving chip yields – easier to access and understand for substrate engineers. Chen said partnerships across the entire industry will be necessary to break through this and other technology breakthroughs. Supply Chain and Cross-Border Ecosystem to Strengthen Partnerships for Further DevelopmentTaiwan has long invested heavily in advancing semiconductor manufacturing and application engineering technologies to become a top global chipmaking hub and, in the process, has been behind significant leaps in optimizing chip functionality, said Leroy Liu, General Manager, Asia Headquarters, of Dialog Semiconductor (Germany). With its semiconductor manufacturing prowess, Taiwan can also play a central role in maturing advanced heterogeneous integration packaging technology while managing development costs by partnering with its international supply chain community to overcome technical challenges more effectively, Liu said. The region can also help forge partnerships, even among competitors, to build the ecosystem essential for heterogeneous integration technology to shine.EDA tools will be critical in understanding and resolving heterogeneous integration technical issues since IC substrate, packaging and chip design all pose interdisciplinary engineering challenges, said Julian Sun, Product Marketing Director at Cadence. To help the industry navigate these challenges, Cadence has launched intelligent system design products – solutions that address a wide range of design problems with semiconductor nanometers, micrometers on packaging and testing, and PCB level micro/millimeters to Pin/Pitch, I/O models, and thermals and electricity. By supporting various technical designs, Cadence helps customers shorten the design cycle to strengthen design quality and reduce costs.Sun also pointed to the vital importance of overcoming the significant challenge of designing silicon interposers for heterogeneous integration. Today’s EDA tools are capable of optimizing the design of complex structures including 5GAiP and HBM and are instrumental in aiding Taiwan’s semiconductor ecosystem players to quickly adapt to shifts in the evolving heterogeneous integration market.Heterogeneous Integration Enables 5G and AI speakers (L-R): Julian Sun, Product Marketing Director at Cadence, Dr. Yu-Hua Chen, Vice President, Carrier SBU, RD Division of Unimicron, Dr. C.P. Hung, Vice President of ASE Group, Leroy Liu, General Manager, Asia Headquarters, of Dialog Semiconductor (Germany), Dr. Shih-Chieh Chang, AITA Executive Secretary Designing AI chips is particularly difficult as semiconductor makers struggle with high costs and low yields, said Dr. Shih-Chieh Chang, AITA’s Executive Secretary. That’s why the chip industry now uses FPGAs for small-volume production of AI chips, which makes it easier to improve manufacturing yield through redundant design. For its part, AITA has formed a special interest group (SIG) to help form connections among the chip industry, academia and research institutes. The association’s goal is to build a platform for mass production of AI chips.To get involved in SEMI Taiwan Heterogeneous Integration related events, please contact Ula Huang, outreach senior specialist, at [email protected] Fang is a coordinator and Ashley Huang is a specialist in marketing and public relations at SEMI Taiwan.
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What’s next for smarter, more connected electronics manufacturing - Part 2The fast-maturing infrastructure now enabling applications for big data and artificial intelligence means disruptive change not just at individual companies but also in data connections among companies across the microelectronics manufacturing value chain. SEMI checked in with some leading players on the changes they see coming in the next several years for this article series. The trade group is expanding its programming on smart manufacturing to address these industry-wide developments at SEMICON West, July 10-12 in San Francisco.“The ramp of EUV, and the smaller geometries and smaller process margins, will drive an exponential increase in the amount of metrology data to manage,” says Neal Callan, ASML vice president, Silicon Valley. Callan notes that moving to multibeam e-beam inspection will increase data volume from megabytes per second to gigabytes per second and from thousands of data points to millions of data points. “The process is so tight and the margin so small that stochastic variation, or noise, becomes more dominant – at least it’s noise until we can learn to understand and control it. And understanding and controlling this variation will be key to delivering 5nm patterning,” he says.Single-beam e-beam inspection is already driving large increases in data as engineers extend the slow technology to broad, high-speed defect metrology applications by more intelligently instructing the system where to look for problems. Callan says ASML is now using the scanner data on wafer focus, alignment and leveling. The company is also using the computational lithography model from the design to identify the smallest process windows in the pattern that are most likely to see problems. The model then quantifies the number and significance of those instances.“The collection of all this diverse data means that tools will need to be plug-and-play so all tool data is instantly available to all systems and software,” says Doug Suerich, PEER Group product evangelist. “We need tools that can be discovered automatically by the network so it can start slurping up data immediately. The adoption of the Interface A (EDA) standard is accelerating and fabs are starting to ask for it. The proliferation of sensors also needs to self-discover. If you are going to add thousands of new sensors into a facility, you can’t afford a time-consuming integration process.”“We are now seeing that engineers are greedy for more data – if they can get the data, it’s becoming a need-to-have,” adds Tom Ho, BISTel America president. “Getting more data from more sensors, from the sensors on the tool that are not being fully utilized, and from untapped data sources like vibration is another big coming opportunity.” Process complexity drives demand for feed-forward between silos with computational models ASML co-optimizes its scanner process with etch and reticle process steps. Source: ASML In addition to the drive for trace-back of data, the increasing complexity of interrelated processes is also driving demand for feed-forward of data. “Feed-forward is becoming more important,” notes Ho. He points to the example of 3D NAND features, now getting so deep that identifying the layer being measured is a challenge unless the signal at the step before can be recognized. “We need partnerships with our peers to understand how to take advantage of the sensors they use, integrate them with our data, and then feed-forward corrections to the other systems,” concurs Callan. “To drive the best CD uniformity and overlay, we need to co-optimize litho and etch,” agrees Henk Niesing, ASML director of product management. He notes that the company is working with etcher makers to measure the overlay and CD, decompose the finger prints, and then use models to steer automated control that best adjusts both the scanner and the etcher. ASML is also working with Zeiss on co-optimization between the scanner and the reticle to make even higher-order corrections by locally modifying the reticle.These higher-order corrections, applied on each exposed field, drive the need for even more data, and at higher speed but without higher cost, notes Jan Mulkens, ASML senior fellow. These corrections increase demand for computational metrology, which combines various metrology sources with physics and deep learning models trained on real data to predict and control process results in real time. “We’re working on computational metrology to ideally use all the knobs we have in the fab,” he says. So far this effort has largely involved linking data between two companies. More consistent data formats would enable data exchange to be extended to more companies. “The software versions also need to be managed for upgrades so they still match after one party updates the system on its tool,” notes Niesing. Speakers on these issues of smart manufacturing and data handling at SEMICON West include Active Layer Parametrics, Applied Materials, Applied Research Photonics, ASML, Cimetrix, Coventor, ECI Technologies, Edwards Vacuum, Final Phase Systems, GE Digital, Infineon, Jabil, Lam Research, Osaro, Otosense, PEER Group, Rockwell Automation, Rudolph Technologies, Schneider Electric, Seagate, Seimens, Stanford University, TEL, TIBCO Software. See semiconwest.org.What’s next for smarter, more connected electronics manufacturing - Part 1What’s next for smarter, more connected electronics manufacturing - Part 3Paul Doe, SEMI
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