IronLattice

IronLattice is a Houston based fabless semiconductor company building nonvolatile ferroelectric memory that runs at DRAM speed, keeps its data with the power off, and writes at roughly a thousandth of the energy of a DRAM row access, with zero power to retain. One cell replaces DRAM, HBM, NAND, and embedded memory. We design the chips and contract out manufacturing. The cell is a single transistor with no capacitor and is fully CMOS compatible with standard ALD tooling. It can be manufactured in the 300 plus logic fabs that already exist, rather than requiring a dedicated memory fab. The result is roughly 10× the DRAM equivalent output of the memory oligopoly without the CapEx, and at least 30% more density modeled. No exotic materials, no rare earth elements, no conflict minerals, 100% American sourced. Cofounded by Dr. James Tour out of his lab at Rice, license closed. Over 10^10 cycles with the on and off ratio held above 10^5, under 10 ns switching, and under 0.1 pJ per bit, all measured on device. Two leading OEMs and a few hyperscalers are evaluating our architecture, we closed a $3M pre seed round, and our first 300 mm wafers run this fall in a commercial R&D fab, with short loop lots and first electrical measurements following immediately and array demonstration targeted (more...)