Session 3: Technology
Logic Leadership in the PPAC Era
Founder and President
Logic scaling is facing unprecedented challenges in an age where the industry has recognized that power, performance, and area scaling (PPA) is no longer sufficient, and process development needs to target power, performance, area, and cost (PPAC). Against this backdrop FinFET scaling is coming to an end with a transition to horizontal nanosheets (HNS) on the horizon, and a further transition to CFETs not far behind. Cost and risk for process development and the ability to ramp the resulting processes into production are enormous challenges.
The result of these challenges is that in recent years we have seen the number of companies pursuing leading edge logic reduced to just three. Also, where Intel was once the clear logic technology leader, TSMC is now the leader and Intel is exploring increased outsourcing with some saying they could even go Fabless.
In this presentation we will explore the current state of leading-edge logic technology comparing the providers as well as presenting expected roadmaps. We will discuss all the elements of PPAC for each provider and discuss what we think the industry landscape will look like over the next decade.