SoC

Product lifecycle management is a well-adopted methodology used in mechanical design. Until recently, it was not widely used in the semiconductor industry. That all changed when Methodics created intellectual property lifecycle management for tracking and analysis of semiconductor IP and design.

“Virtual platform environments that combine the verification capabilities of emulation with the pre-silicon functionality insights available through verification intellectual property (VIP) are an increasingly popular way to get designs verified ahead of the curve of new standards,” Browy says.

Three-dimensional integrated circuits (3D-ICs) are revolutionizing the semiconductor industry. Manufactured by stacking and interconnecting dies so they perform as a single device, 3D-ICs deliver more capabilities by offering higher performance and bandwidth — while also reducing power consumption, package size and costs. However, 3D-ICs present tough design challenges to engineers. Significantly larger than a single-chip system on a chip (SoC), these assemblies have more components, more integration points and longer interconnects, that translate to new risks for high-frequency signal failure, reliability, and other performance issues such as thermal buildup. As the lines between silicon and system continue to blur, engineers must conduct concurrent, multivariate analysis to assess every possible failure mode ― not only at the component level, but also across the entire 3D-IC assembly ― a technical obstacle for many development teams accustomed to applying a series of single-physics engineering simulation tools in a sequential approach. 3D-ICs are assembled in a complex package using a serial analysis approach that doesn’t take into account system-level interactions, as well as the many thousands of bump connection points where something can go wrong. By contrast, concurrent, multivariate simulation and analysis takes into account all physics simultaneously from the earliest prototyping stages of design. Most semiconductor development teams not only lack the technical tools to perform this complex simulation and analysis, but they also face cultural obstacles as they undertake system-level analysis. Diverse teams working with disparate tools simply aren’t equipped to perform seamless handoffs and collaborate effectively on a complex 3D IC design from an early stage. Instead, they scramble to address system-level issues later when launch delays are likely, the cost of rework is high and their positive contributions to the design are diminished. The Value of a True Multiphysics, Multivariate Approach As market demand for 3D-ICs increases, semiconductor development teams need a single simulation platform that enables simultaneous multiphysics analysis — including power integrity, reliability, electromagnetics (EM), thermal, computational fluid dynamics (CFD) and mechanical studies ― across the entire assembly. A unified simulation platform that brings together best-in-class solutions for every physics enables semiconductor engineers to collaborate across functions, seamlessly hand off analysis tasks between engines, and partner to optimize 3D-IC designs across every performance parameter. Costly surprises from signal integrity to thermal conductivity and structural strength are far less likely when the team reaches physical assembly to help ensure on-time, cost-effective product launches. An example of simultaneous multivariate analysis of a chip stack showing both thermal gradients and mechanical stress/warpage of the package at an early prototyping stage. By contrast, applying multiple physics sequentially can lead to ongoing and expensive setbacks. For example, as one team resolves signal integrity issues, another team could discover that timing failures or thermal risks have arisen. It’s not only back to the drawing board, but back to a series of time- and resource-intensive handoffs across disconnected simulation and analysis tools, as well as across functional boundaries. The Importance of Considering Novel Physics Because the pressure is on to launch innovative 3D-IC designs rapidly, development teams might be tempted to focus on existing signoff metrics ― which are complicated enough, across today’s multi-die assemblies — but overlook the application of more novel physics. This is a mistake that can result in failures in the field, product recalls, warranty expenses and lasting damage to the brand reputation. To achieve full product confidence across the entire 3D-IC system, semi engineering teams need a solution set and associated best practices that make it fast and intuitive to not only optimize performance and cost, but to concurrently analyze novel physics that will impact electrical reliability, mechanical stability and thermal failure modes. The number of physical effects that need careful simulation has risen in lockstep with Moore’s Law and has increased even more for 3D-IC design. The use of a single, connected platform enables this kind of true multiphysics analysis. A multiphysics platform should interface with popular design systems, and be extensible by Python API's to the user and to other vendors. For example, engineers can check the thermal behavior and the likelihood of melting and local failures of each solder bump based on the electrical current it carries. The engineers can apply computational fluid dynamics to evaluate how well airflows generated by fans and heat sinks work to cool down the assembly. They can maximize system reliability by examining unfamiliar effects like low-frequency power oscillations on the distributed power supply network. Best of all, a unified and purpose-built simulation platform enables semiconductor development teams to conduct all these studies simultaneously to rapidly reveal design trade-offs that arise when many elements are brought together in a complex assembly. Only this type of multiphysics, multivariate, concurrent approach enables engineering teams to reach all their goals for speed, confidence, innovation and product performance as 3D-IC designs take over the global market. Supporting a Culture of Vertical Integration Global leaders in the semiconductor and electronics industries benefit from a culture and organizational model based on vertical integration, which supports high levels of design collaboration. It can be tough for horizontally integrated, smaller companies to establish this depth of collaboration. Customers require open and extensible platforms that support a broad range of analysis tools across many different abstraction levels – from device to chip to board to system. The right simulation technology platform can significantly help. A shared platform that brings cross-functional engineering teams together for simultaneous, not sequential, multiphysics design can make it easy and seamless to collaborate across functional boundaries and support excellence in every aspect of power, performance, reliability and cost. By balancing these foundational performance aspects with simultaneous optimizations of temperature, mechanical stress and other subtle effects, semiconductor engineering teams can position themselves as leaders, not followers, in the 3D-IC revolution. Learn More at the Ansys IDEAS Digital Forum Register for Ansys IDEAS Digital Forum on demand to learn more about 3D-IC best practices from leading industry experts (www.ansys.com/ideas). John Lee is General Manager of the Electronics and Semiconductor Business Unit at Ansys.

Throughout the current millennium, System-on-Chip (SoC) has been the gold standard for optimizing performance and cost of complete electronic systems. By incorporating practically all the phone’s digital plus analog capabilities onto a single, giant chip, the mobile phone processor serves as a near-perfect exemplar of SoC. But today’s leading integrated circuits (IC) are pushing up against the upper limit of a chip’s size which is limited by the manufacturing equipment’s optical reticle size. This has proven difficult to increase and has grown only slowly over the years. Yet market pressure continues unabated for bigger, more capable electronic systems with more integrated memory, more digital logic, and more analog/mixed signal circuitry. An emerging solution to this tension is 3D and 2.5D multi-die chip assemblies – often referred to as 3D-IC. The key technology breakthrough of 3D-IC is that it makes it possible to spread a system out over multiple, smaller chips that are then assembled close together and interconnected with high-speed, low-power interconnect technologies. By abandoning the need to integrate an entire system on a single SoC and instead allowing it to be disaggregated over multiple chips, 3D-IC enables Moore’s Law to break through the reticle size barrier, improves yield by shrinking the size of individual chips, and makes it possible to mix different process technologies optimized for each function. The Four Engines Driving Semiconductor Design The road forward is not without its challenges, however, and we are seeing design companies making significant efforts to adapt and come to grips with the following four technology and market drivers: The requirement for concurrent multiphysics analysis to ensure reliable and efficient electronic systems The blurring of the lines between silicon and system The need for open and inclusive multiphysics platforms that interoperate with the multitude of design platforms The need for, and value of, bespoke silicon for hyperscalers and system companies Blurring of Silicon and System Design The advent of 3D-IC opens up new horizons for solutions that can be implemented in silicon. But it also forces a closer integration between two distinct technology markets that have co-existed symbiotically for many decades: IC design and printed circuit board (PCB) design. These markets use different tools, different data formats, different manufacturing back-ends, operate at different computational and geometric scales, and focus on different physical concerns. Yet, 3D-ICs share many aspects of both markets: They include monolithic chips but also board-like substrates to stitch the chips together. And in between the two disciplines is packaging, a completely different domain that is requiring companies to re-imagine their design capabilities and flows, as well as their organizational structure. Open, Extensible Multiphysics Platforms The siloed isolation of chip design from PCB design and package design means that each of these markets has developed insular data structures that are ill-suited to deal with the breadth of multiphysics analysis for 3D-IC design. Many different physical disciplines, including computational fluid dynamics, mechanical stress, and electromagnetic radiation, all need to work together based on open and extensible multiphysics platforms. These platforms must embrace the modern cloud compute paradigm and enable an ecosystem by allowing individual design platforms to connect for comprehensive multiphysics analysis. Bespoke Chips Today’s market-leading companies are heavily dependent on technology for their continued success and market differentiation. Everybody from online retailers to telecommunications to social networking companies and hyperscalers are moving away from off-the-shelf solutions and turning to custom-built silicon to give them an edge. Many of these companies are seeking to gain market share by leveraging proprietary AI/ML algorithms trained on their extensive troves of market data – but this requires huge amounts of compute power and specialized chips. Access to high-quality silicon solutions is vital in today’s world and the demand is for continually more complex and powerful electronics. 3D-IC an Inflection Point in Electronic Design To be sure, 3D-IC design is at an inflection point in electronic design and presents major challenges that are realigning the electronic design industry around this new reality. For more insights on this topic from a semiconductor industry leader, please view the Keynote Address 2.5D and 3D – The Road Ahead by Vicki Mitchell, VP Engineering, Arm Central Engineering Systems Group presented at the latest Ansys IDEAS Forum. And for an EDA perspective, please view Successful 2.5D and 3D Multi-die Silicon System Design Using Synopsys’ 3DIC Compiler and Ansys’ Multiphysics Analysis from Synopsys SNUG World 2021. About John Lee John Lee is general manager and vice president of the Ansys Electronics and Semiconductor Business Unit. Lee co-founded and served as CEO of Gear Design Solutions (now Ansys), developer of the first purpose-built big data platform for integrated circuit design. He cofounded two other startups (Mojave Design and Performance Signal Integrity), which successfully exited into companies now part of Synopsys. He holds undergraduate and graduate degrees from Carnegie Mellon University.

New system-on-chip (SoC) devices are driving new memory architectures and photonic interfaces, while specialized new intellectual property (IP) requires analysis down to the nanometer and atomic levels because of single nanometer process nodes. According to Babak Taheri, CTO and EVP of products at Silvaco, a leading EDA Software, semiconductor IP company, a member of SEMI and the ESD Alliance, a SEMI Strategic Association Partner, design technology co-optimization and proven IP are required for this analysis.Taheri recently discussed atoms to systems in next-generation SoC designs with Nanette Collins ahead of ES Design West, co-located with SEMICON West, July 9-11 at the Moscone Center in San Francisco.ESD Alliance: For years now, the assumption is that each new chip design is more complex than the last. Why are the latest SoC designs even more complex than before?Taheri: New SoC devices for mobile phones, automobiles, intelligent edge nodes, big data compute and storage are adopting artificial intelligence and machine learning technologies. This is driving new compute, data flow, as well as memory architectures that are bandwidth-limited and some require photonic interfaces.One common denominator in present SoC design are the numerous blocks of IP. On average, over 85% of these blocks are reused. It’s cost-prohibitive to make these chips over and over again with new IP. According to some estimates, 90% of IP used in an SoC design by 2025 will be reused – only 10% is new technologies. That 10% is significant.ESD Alliance: How so?Taheri: Complex new technologies including flash memory, other advanced non-volatile memory technologies such as MRAM, RRAM and SoCs such as NVIDIA’s Xavier and Apple’s A12 use and reuse design IP at the architectural level.New technologies mean new materials and new processes. Single nanometer process nodes require specialized new IP that needs to be simulated and analyzed down to the nanometer and atomic levels.ESD Alliance: Does the atomic level changes the design equation?Taheri: Yes, it does. Designers need to be able to simulate at the atomic level and understand properties of these materials, and how they behave in at-process and at-device levels. They need be able to simulate the material's nanometer geometries, how molecules behave and how they interact for device operations. When they put together a process and a device, they need to know how the pieces behave and simulate before production.In other words, they run quite a few design experiments and quite a bit of simulation before they finalize the circuits and devices to silicon to save money.ESD Alliance: It’s obvious design automation will continue to have a vital role in design.Taheri: Yes, absolutely. Design technology co-optimization (DTCO) using TCAD solutions and proven design IP are needed to address the span from architecture to device and process physics. The importance of simulation, emulation and design technology co-optimization, along with fully verified and proven IP for SoC design, cannot be overstated. As designers generate devices and processors, they take that up to circuit-level simulation and high-level simulation, schematic capture, extractions and back annotation. They can go from atoms to simulating systems to the ability to do that under the same umbrella in order to get better chips, better yield and lower cost.Taheri’s talk Next Generation of SoC Design: From Atoms to Systems will be part of the Meet the Experts More than Moore session Tuesday, July 9, at 11:30 a.m. at the ES Design West SMART Design Pavilion. SEMICON West attendees are invited to Moscone Center’s South Hall to learn more about electronic system and semiconductor design and its links to the electronic product manufacturing and supply chain. Register for ES Design West or SEMICON West.Babak Taheri is Silvaco’s CTO and EVP of products, has more than 25 years of design experience. His current role managing Silvaco’s Technology CAD (TCAD), electronic design automation (EDA) and IP product divisions makes him an expert on what’s needed for the design of next-generation system-on-chips (SoCs). Previously, he was the CEO and president of IBT working with investors, private equity firms, and startups on M A, technology and business diligence. Babak received his Ph.D. in biomedical engineering from the University of California Davis with Bachelor of Science degrees in Electrical Engineering and Computer Science and Neurosciences. He has published more than 20 articles and holds 28 issued patents.Nanette Collins is a public relations representative for the Electronic System Design Alliance.

SEMI met with Gerald Beyer, program manager at imec, to discuss the co-existence of various 3D interconnect technologies and their need for new materials and integration solutions. The two talked in the runup to his presentation at the Advanced Packaging Conference at SEMICON Europa 2018, 13-16, November 2018, in Munich, Germany. To register for the event, click here. SEMI: Can you confirm this trend towards heterogeneous integration and do you think it will be a long-term development trend?Beyer: We consider heterogeneous integration as a scaling booster for functional partitioning and as a fashion method to create systems, which would not be possible or economical on such as a single chip. As you can apply it to numerous systems, we expect it to stay for the long term.SEMI: What are the new critical challenges for the combination of different technologies into one package?Beyer: When you create a complex system, there is usually more than just one challenge. On one side, you need to be able to design such a system. If you disintegrate a large chip, you need to decide how to reconstruct it, i.e. which function goes into which strata. You would like to do that not manually but with a set of tools supporting the designer. Only recently EDA (Electronic Design Automation) and design houses have started to support this idea.On the technology side, interconnections between some strata of such a reconstructed chip will require small pitch interconnects of the order of 1µm pitch and less. Today, wafer-to-wafer bonding technologies have sufficient overlay margins for 1µm pitch. Wafer-to-wafer bonding technologies, however, have a number of constraints such as equal die size and the necessity to realize chip stacking rather in a fab environment than in a traditional packaging house. Die-to-wafer assembly technologies still need to bridge the gap to deep sub 10µm pitch in terms of alignment and cleanliness.SEMI: What kind of new materials or integration solutions do you expect to be developed? Are you working on it already?Beyer: As explained above, die partitioning requires sub 1µm pitch interconnects. We are investigating fine pitch wafer-to-wafer and die-to-wafer (direct) bonding. For the latter, not only new alignment capabilities but also die cleaning and thin die handling technologies need to be developed. To build a complete system with data processing, memories etc., novel integration schemes such as Flip Chip – Fan Out Wafer Level Packaging with high density 2D and 3D interconnect capabilities are being investigated. These new systems differentiate from current ones by high density Through Package Vias (TPV), Si bridges and sub 2µm line/spacing RDL. The new integration approaches push the materials such Temporary Bond Materials (TBM), Wafer Level UnderFill’s (WLUF), photo patternable polymers for fine Line/Spacings to name a few, to the limits. Hence, development of new materials is a key aspect.SEMI: What trends and developments do you expect in the near future and why would you recommend attending the Advanced Packaging Conference?Beyer: The development and commercialization of products using heterogeneous integration is a big effort drawing on resources from EDA vendors, materials and packaging tool suppliers, OSATs, foundries, memory suppliers and IEDMs and academia alike. The agenda of the Advanced Packaging Conference at SEMICON Europa reflects this diversity and I am looking forward to interesting discussions with all participants. Gerald Beyer has been working in the field of 3D Technologies since 2012 as the technology program manager of the 3D System Integration Program of imec. Prior to this role, he was the interconnect program manager and group leader of BEOL integration. He received a PhD in materials science from Imperial College, London and a MSc from Thames Polytechnic, London.Serena Brischetto is a marketing and communications manager at SEMI Europe.