semiconductor manufacturing

D-SIMLAB Technologies, a Singapore-based provider of simulation-based business analytics and optimisation software solutions, recently joined SEMI. I spoke with Peter Lendermann, the company’s co-founder and Chief Business Development Officer, about the company’s role in the smart manufacturing movement, how customers are benefiting from D-SIMLAB solutions, and what the future holds for smart manufacturing. Ng: What is D-SIMLAB’s mission?Lendermann: Our mission is to develop, market, and deliver high-performance simulation-based decision support solutions that enable corporations to enhance their performance in a sustainable manner leading to significant cost savings. In particular, we focus on semiconductor manufacturing material flow planning and optimisation but also do business in aviation where we help customers optimise their spare parts support operations. What these two domains have in common are three important attributes: They are capital intensive, their underlying operations are complex, and operations are also heavily affected by random, i.e. unpredictable events, which makes both planning and execution of manufacturing operations very challenging. D-SIMLAB is a spin-off from the Singapore Institute of Manufacturing Technology (SIMTech) under the Agency for Science Technology and Research (A*STAR). Our head office is in Silicon Island Singapore. We also have representations in Germany and the U.S. Most of our staff are industrial and computer engineers with up to 20 years of operations experience in their respective industry domain, as well as vast data analytics and software development capability.Ng: What solutions does D-SIMLAB offer to optimise semiconductor manufacturing?Lendermann: In the three-pillar smart manufacturing framework of Connect, Sense and Predict advocated by SEMI, our focus is on Predict though we emphasise the equal importance of the subsequent Act: Our solutions can Predict, for example, WIP waves or usage-based preventive maintenance due dates. But much more value-add can be realised once some decisions with regard to how to Act can be derived from such a prediction. The ability to pro-actively adjust action plans in a timely manner is essential to overcoming challenges arising from changing customer due dates, mix profile changes, untimely production line issues, and production capacity to be shared with R D lots effectively, so that ultimately our customers can enhance capacity, reduce cycle times and improve the due-date performance of their factories.To that end, our D-SIMCON solution suite spans the full spectrum of decision-support tools required to forecast, manage and optimise material flow – from operational scheduling and dispatching, WIP forecasting and dynamic and static capacity planning all the way to specific applications for fab load mix optimisation or for the enhancement of the product/layer dedication and resist allocation in the lithography area. Our solutions are implemented in numerous 6-, 8- and 12-inch wafer fabs operated by both IDMs and foundries worldwide with capacity ranging from 40,000 to 200,000 wafers per month.Ng: What are the key enablers of D-SIMLAB’s success?Lendermann: Our success lies in deploying production-ready solutions for our customers, allowing them to extract immediate value. Our solutions enable the portrayal of many domain-specific characteristics such as queue time constraints or specific equipment behaviour, which is absolutely essential to generating operationally feasible plans or schedules in order to be able to Act in the best possible manner according to what has been Predicted. Moreover, we have modules for automatic generation, calibration and maintenance of the underlying capacity model, including resolution of data inconsistencies as well as verification and validation of the model, to allow near real-time responses to continuously changing operations. And the associated optimisation approaches focus on creating maximum possible value with as few iterations as possible and within minimum time through smart heuristics and parallel computing infrastructure – a paradigm that is as powerful as it is cost-effective.Ng: What are a few of your more notable customer successes?Lendermann: As a result of the first implementation of our novel, multi-objective based Scheduler cum Dispatcher, a tool capacity gain of 8%, a transportation capacity gain of 10%, and an operator workload reduction of 25% were concurrently realised at one of the critical equipment groups in our customer’s fab. At another set of equipment groups in the same fab, a 7% increase of lots within the critical queue time limiting area was achieved.Another use case we successfully realised is fine-tuning of Preventive Maintenance plans: Based on a seven-day lot arrival forecast at each equipment generated with our WIP Forecaster, a recommendation is made when PM would be best possible without causing too much disruption in the WIP flow. The effect of this synchronisation of the PM plan with material flow enabled a dramatic reduction of the average queue lengths at critical equipment groups and the associated cycle times without incurring any capacity loss. Reduction of average queue length as a result of synchronising preventive maintenance with material flow. Ng: What challenges has D-SIMLAB been facing in the COVID-19 world?Lendermann: Obviously, software delivery projects have become more challenging for the time being since our engineers cannot be on-site frequently. But it also turned out that more and more services can be delivered remotely, which has the nice side effect of making the services more cost-effective for customers. Overall, we are confident that our solid customer base will enable us to sail steadily through these challenging times.Ng: Where does D-SIMLAB see the technological development heading?Lendermann: In the future, enriching decision support and manufacturing execution solutions with machine learning and other AI techniques will be critical in reducing dependency on human experience. This path is essential to making manufacturing operations fully Industry 4.0-compliant. D-SIMLAB will certainly be at the forefront of this development. Bee Bee Ng is president of SEMI Southeast Asia.

Semiconductor process development is no easy task, with each generation of devices more difficult and expensive to create. Traditional cycles of build-and-test development are becoming obsolete, since they are too expensive and time-consuming for the most advanced processes.The High Cost of Process DevelopmentMost chip designers developing new products rely on existing manufacturing processes, but someone had to create those processes to make the designs possible. The goal of process development is to create new semiconductor manufacturing processes that provide high yield while achieving the required device performance. In contrast to new chip design, however, it requires an entirely different set of engineers and skills.The traditional approach to process development involves building multiple test wafers to determine the ideal process for a given device. After one set of wafers is fabricated and analyzed, insights from the previous round help to refine process steps for another round of fabrication. Due to smaller feature sizes, each new process generation is more sensitive to variation. This adds even more complexity because smaller feature sizes and parasitic effects require more measurements and testing as well as additional fabrication. The cycle is repeated many times before the entire process flow can be finalized, making it time- and cost-intensive, especially for the most advanced technology nodes.Testing Virtual Wafers Instead of Real WafersToday, there is an alternative to this slow, expensive way of doing things. Virtual fabrication lets computers simulate all of the processing that occurs when real wafers are built. These virtual models allow semiconductor process engineers to test manufacturing equipment settings with far greater variation than is possible in a physical fab. Designers can simulate the entire process flow, running the equivalent of thousands of wafers in days instead of months. Designers can quickly see graphical animations to visualize process steps, modify process recipes and device geometries, and measure how these changes affect electrical behavior.Improving Yield Using Statistics in Virtual Wafer FabricationBecause of the high volume of data generated, designers are turning to statistical analysis to provide greater confidence in their choice of process settings. Defects and random variations can be modeled in a virtual fab in a way that’s not possible in a real fab, letting developers test the sensitivity of the device structures against the unpredictable aspects of processing.There’s more than one approach to optimizing the process settings used in a new memory or logic fabrication sequence. The simplest one involves taking a single variable and exploring its effects. Critical dimensions (CDs), for example, establish those feature sizes of a device that ensure desired electrical performance. A particular dimension can be swept from low to high values – developers can then measure the effects of that range on device behaviors such as threshold voltage. This allows developers to ensure that the electrical behavior of their device design addresses the range of expected feature sizes and variability. The interactions with intersecting process steps can also be tested for further validation, since these interactions can lead to unanticipated device performance.But, in reality, this approach isn’t sufficient for studying the complex web of interactions between process steps and the resulting structures.A second approach leverages Monte Carlo analysis, randomly varying a wide range of process and device parameters and calculating the resulting device geometry and performance. This data can be used to automatically identify the process and design settings needed to achieve yield and performance goals. It’s an area where simulation shines, providing a useful way to test the interactions between many different processes.Statistical experiments using virtual fabrication illustrate step-by-step methodology to optimize process and design settingsVirtual Fabrication PlatformSEMulator3D is a virtual fabrication platform created by Coventor, a Lam Research company. It allows the definition of all process steps, the modeling of devices, the collection of metrics, electrical and device analysis, the statistical analysis of results, and the visualization of process steps through graphical animation. Today, semiconductor companies use it for both optimizing and scaling leading process nodes and for developing advanced new technologies like GAA (Gate-All-Around) transistors.The ability to do this work virtually is the future of semiconductor process development. Virtual fabrication accelerates new process time-to-market by months, opening up market opportunities worth hundreds of millions of dollars for semiconductor companies.Visualization of process steps of a Gate-All-Around transistor shows 3D construction in SEMulator3D. To learn more about virtual fabrication and how it’s changing the future of semiconductor technology development, download our whitepaper Speeding Up Process Optimization with Virtual Fabrication.Lam Research is a longtime member of MEMS Sensors Industry Group®, (MSIG), a SEMI technology community that connects the MEMS and sensors supply network in established and emerging markets, enabling members to grow and prosper. Visit us today.David M. Fried, Ph.D., is vice president of Computational Products at Lam Research, where he is responsible for the company’s strategic direction and implementation of virtual process solutions, including the Coventor SEMulator3D virtual fabrication 3D process modeling solution. Fried leads the execution of technology strategy for technology platforms, partnerships, and external relationships. His expertise touches upon such areas as Silicon-on-Insulator (SOI), FinFETs, memory scaling, strained silicon, and process variability.Fried is a well-respected technologist in the semiconductor industry, with 60 patents to his credit and a notable 14-year career with IBM, where he was involved in successive process generations from 65-nanometer and lower. His most recent position was 22nm chief technologist for IBM’s Systems and Technology Group. He holds bachelor’s, master’s and doctoral degrees in Electrical Engineering from Cornell University.Republished with permission from Lam Research.

Part 1 of 2Read Part 2. While companies navigate the ongoing COVID-19 crisis, corporate leaders should be evaluating a number of key business continuity issues as well as steps they can take to not only react to business disruptions but also reshape their business and recovery plans.We spoke with Dan Steele, Senior Director and the APAC Head of Environmental, Health, Safety, and Security (EHS S) at GLOBALFOUNDRIES (GF) Singapore, via teleconference for insights into the best practices he and his team have implemented from their Business Continuity Plan (BCP) to guide them through the health crisis.SEMI: How did GLOBALFOUNDRIES Singapore first respond when the country reported its first COVID-19 case?Steele: Since the early days of our company, we have had a Business Continuity / Crisis Management (BCCM) team in place that is responsible for business continuity planning for the site. At the beginning of this journey with the coronavirus, we believed in two truths: maintaining the safety and well-being of our employees and consistently communicating precautionary measures the company has taken to protect them and our business. These actions are critical to keeping our employees safe, while keeping the anxiety level low. By informing and updating employees in a timely manner, we ensure that they are well-educated about the crisis as it unfolds and the foreseeable circumstances that could be ahead of us. Once the world was well into the coronavirus outbreak, our CEO declared in a message to all employees that “we entered this pandemic crisis together, and we will exit it together.”We have also established links to pertinent government websites and made them conveniently available to ensure employees have access to the latest available information for their personal lives.SEMI: What actions has GF Singapore taken in response to the crisis so far?Steele: On January 29, our BCCM team activated the first line of defense by initiating temperature checks at all building entrances for every individual including employees, contractors, visitors, and customers who come into our facilities. We asked each to declare their state of health and travel history and issued a temperature card to every employee and resident contractor. They are all required to record their temperature twice daily – once before coming to work and again at midday – and they present the temperature log to security upon their arrival.The following week, our teams split into an A/B work arrangement to ensure continuity of our operations. We proactively pared down our teams to the staff essential for our on-site operations, while enabling the rest to work from home. We also advised our most vulnerable employees with impaired immune systems or who are pregnant to work from home. Concurrently, we moved all meetings of 10 or more people to virtual communications and only allowed meetings with fewer than 10 to be held in rooms with participants sitting at least one meter apart. We informed our customers of our efforts and moved all planned on-site visits to online visits.In line with Singapore’s efforts to curb the spread of COVID-19 within the community, GF restricted site access of people who had recently traveled to countries with sustained community transmission and regularly updated the restriction list. To conduct contact tracing, we created our two degrees of separation list that we used to track employees with families and close associates who were linked to a COVID-19 case. Employees provided the information voluntarily. On our campus, we enforced strict safe distancing measures by limiting access to meeting rooms, marking off-limits tables and removing chairs in the cafeteria, limiting the number of elevator riders to no more than four, and placing boxes or other spacing indicators at smoking zones, bus stops and temperature-taking lines. We also initiated a daily log of employees taking the company buses tagged to the bus number, time, and employee identification numbers in anticipation of the need for contact tracing.Most recently, when the Singapore-Malaysia border closed, we activated the next phase of our BCP that was already in place – housing over 450 Malaysian employees in Singapore hotels.Throughout this crisis, we continuously monitor and evaluate possible impacts to our supply chain to ensure the continuity of our business. This is a standard element of our ongoing business continuity management system.Most importantly, we frequently communicate with our employees and tell them everything the company is doing and why we are doing it. We encouraged employees to monitor their health, stay home if they are unwell, and seek immediate medical treatment if necessary at one of our panel clinics or other medical facilities.SEMI: What are your top concerns amidst this health crisis?Steele: At GF, we are managing through the crisis with an unwavering focus on two guiding principles: the safety and well-being of our worldwide team, their families and communities; and delivering on our commitments to our clients. As the world’s leading specialty foundry, GF has a unique role in the global supply chain. Our semiconductor technology is vital to a range of industries including health care, communications, infrastructure and security. With these priorities in mind, the company undertook unprecedented steps and has adapted to the crisis by dynamically adjusting its protocols, health and safety measures, and business processes to protect its teams while maintaining manufacturing excellence.We are committed to safeguarding the well-being of our employees while supporting and sustaining our on-site operations and protecting customers’ products. A major concern is the impact on our employees. We understand that COVID-19 can be infectious even if an individual is asymptomatic – we are always concerned that temperature screening alone is not sufficient. This is the reason that from day one we have encouraged our employees to monitor their health, follow all government advice for proper hygiene and seek medical attention if unwell as early as possible, and not come to work.Dan Steele has over 25 years of experience in environmental, health and safety, and security operations. He has also held other leadership roles in facilities engineering, quality, reliability and assurance, and risk management.Bee Bee Ng is president of SEMI Southeast Asia.

Sapphire is a precious gemstone, consisting of aluminum oxide (α-Al2O3) with occasional traces of other elements such as iron, titanium, chromium, vanadium or magnesium. While sapphire stones found in nature mostly go to jewelry applications, the lab-grown sapphire – produced in a scale of up to several hundred tons per year – is widely used by the electronic industry. Now one can hardly find a branch of technology where this crystal is not used.Sapphires are mainly applied in infrared optical components, high-durability windows, wristwatch crystals, and the very thin electronic wafers used as the insulating substrates of solid-state electronics. High thermal conductivity, low reactivity, and appropriate unit cell size make sapphire an ideal material for a wide range of such electronic substrates for manufacturing of components such as LEDs and CMOS chips.SEMI spoke with Ivan Orlov, CEO of Scientific Visual, after his presentation at SEMI Strategic Materials Conference at SEMICON Europa, 12-15 November, 2019 in Munich, Germany, to learn more about the future of sapphire.SEMI: Why is sapphire an ideal material for a wide range of electronic substrates? Orlov: Sapphire undoubted advantages are its chemical inertness and ability to withstand high temperature, radiation and mechanical loads. In addition, it exhibits low dielectric loss and very good electrical insulation that makes sapphire a good candidate for substrates for LEDs and laser diodes or wafers for epitaxial growth. However, the most important advantage is that sapphire crystal lattice does very well matching semiconductor materials deposited to its surface, in particular nitrides of group III elements. To plainly benefit from these features, the grown sapphire must have as few macro- and micro-defects as possible, as substrate defects are inherited by semiconductors layers grown on the substrate surface. Hence the importance to detect defects in the raw sapphire material. This is the area where our team at Scientific Visual contributes. SEMI: Flaws are usually identified only after costly wafering and polishing steps, because rough surface of raw crystals prevents detection of the defects. What can be done to prevent defects?Orlov: Today, major players are investing in growing larger crystals without mastering in depth the growth process. Let’s face it, the semiconductor substrate industry, which is primarily based in Asia, is using empirical research methods. The raw sapphire boules are still inspected manually, and this qualitative assessment is exploited in two folds. The first step is to further process the boule. Furnace operators then adjust the growing parameters depending on the results of the manual inspection.Due to the lack of visibility into internal crystal defects, the crystal growth and its downstream processing remain an art rather than a science. The primary reasons are the difficulty to measure, locate and quantify precisely the defects in the full crystal volume. Scientific Visual equipment enables defects in raw boules to be fully quantified and categorized. With such objective measurements and knowing the full set of growth parameters, the Process Engineering (PE) team can, with the assistance of deep learning algorithms, considerably improve the growing process. Our quality control tools give Process Engineering team the “eyes” to see complete defect distribution in raw crystals, enabling it to make minor modifications in the growth process to improve yields, reduce costs and shorten the time to market for products.SEMI: What lead to those advancements and what problems did your team set out to solve? Orlov: Breakthroughs in immersion tomography, machine vision and parallel computing drove advancements in automated quality control technology. Previously crystal inspection accuracy was limited by the acuity of the operator’s eye and subjective bias. Light distortion and the diffusion of crystals made it impossible to accurately identify internal defects.Scientific Visual equipment give operators an undistorted 3D view of all defects in a crystal boule or ingot. However, only deep learning technology can correlate a hundred thousand growth data points to identify a final defect pattern.Defect pattern in non-processed item cored from EFG sapphire plate. Well visible is a typical wavy pattern of surface layers and sandwich structure in the volume. Color code marks sapphire defect density: from deep blue (non-defective material) to deep red (highest defectiveness.) SEMI: What challenges are addressed by your approach? Orlov: Increasing the yield of semiconductor substrates like Sapphire, Gallium Nitride and Silicon Carbide is paramount to reducing the price of wafers while increasing their quality. The upstream growth and downstream wafering processes are not deterministic. So far, most of the producers can only determine the quality during the late stages of the process. This condition creates huge constraints for teams in charge of production and processing. Automated Quality Control (QC) at the early stage of the production chain relieves all the unknowns, ultimately reduce the cost of material.SEMI: And what are the main opportunities?Orlov: There are massive opportunities to increase the yield and to ease the full processing chain from growth to the wafering process. Objective Quality Control (OQC) paves the way to industry-wide standards that categorize crystal quality at each step of growth to enable full certification of the defectiveness of the material and facilitate its trade and exchange.SEMI: What’s one of your predictions for the future of new materials?Orlov: The explosion of e-mobility and electric vehicles and the development of other green technologies will drive rising demand for low-defect sapphire, silicon carbide and gallium nitride substrates thanks to the streamlining of the full processing chain. Manual quality control will soon give way to full automation as quality control in sapphire and other raw crystals production is the only missing link in a fully automated semiconductor production chain. I believe that in five years, automated raw crystal inspection will become standard in the industry. Our mission is to empower every crystal grower to achieve this important milestone.Dr. Ivan Orlov obtained a Ph.D. in Crystallography from the Federal University of Technology in Switzerland EPFL and an MSc in Solid-State Physics in Moscow, Russia. Ivan co-founded Scientific Visual in 2010 to answer the challenge of the synthetic crystals industry struggling with high defect yield. Prior to this he worked in a company specialized in diamond optics. He has more than 10 years of experience in R D with focus on optical materials, industrial crystals and non-destructive quality control technologies. Dr. Orlov was a SEMI Task Force member for sapphire standard development in China and collaborates with ISO committee in Switzerland to establish industry-wide sapphire quality standards.Serena Brischetto is senior marketing and communications manager at SEMI Europe.

Semiconductor, electronics and equipment manufacturers today face a number of logistics and supply chain challenges that could be overcome by systems providing a secure, tamper-resistant, single source of truth. Chief among these challenges is limited data sharing due to data security barriers among suppliers, shippers, manufacturers and test houses, an impediment to achieving optimal product quality and regulatory compliance. Additionally, inefficient and inadequate processes for tracking goods make it more difficult to isolate shipping problems, track faulty parts and verify product authenticity. Counterfeiting has become a serious problem that costs US-based semiconductor manufacturers $7.5 billion annually.How Blockchain Can Help Clear Data Sharing BottlenecksBlockchain functions could help alleviate many data sharing pain points in manufacturing. Blockchain’s distributed functionality, bundled security measures, and associated features such as smart contracts have the potential to help manufacturers quickly trace goods, manage records transparently, and automate supply chain processes and payments. No isolated blockchain platform would solve all of these problems on its own. But, when combined with other solutions and applied to particular use cases, blockchain has the potential to optimize operations and foster an environment of trust and collaboration among consortium members. Three core features of blockchain make it a valuable technology for manufacturing: Distributed and immutable system of record. With a distributed system of record in the blockchain network, there is no "central" data store controlled by one organization. The distributed ledger provides all participants with a view into the data, thus increasing transparency, data distribution timeliness, information sharing, and data access. Security also improves as there is no single central data store open to external attacks. Once data is inserted onto the chain, it cannot be easily changed. Security and Trust. Blockchain integrates best-of-breed cryptographic mechanisms to guarantee the digital identity of the network participants and secure the privacy of the data stored to enable role-based data access. It brings trust to a potentially trustless environment without the need for a centralized third party. Smart Contracts. Smart contracts are embedded business logic that can be added to a blockchain. They enable the automation of many processes and the secure handling of contracts. Blockchain Use Cases in ManufacturingIn each stage of manufacturing, blockchain could be applied in a variety of use cases to expedite processes and alleviate security issues. A few examples that merely scratch the surface of what may be possible follow.In pre-production, manufacturers may implement blockchain solutions for Collaborative Planning, Forecasting and Replenishment (CPFR). These systems monitor inventory levels, enabling suppliers to replenish supplies before they run low. The expensive, proprietary B2B networks used today could be replaced with blockchain as the common sharing protocol, using non-proprietary or public networks.Suppliers may also combine blockchain with IoT sensors on shipping containers to provide a tamper-resistant record of shipping conditions. This could be used to ensure that temperature and humidity tolerances for chemicals and equipment are not exceeded during transit from the supplier. The identity and materials in components and subcomponents of manufacturing equipment could be collected on a blockchain to verify compliance with environmental and health regulations. During production, a manufacturing process machine can be registered on a blockchain with a unique identity; its performance and maintenance history can be recorded. A maintenance service provider could then be automatically notified, via a smart contract, when a predictive maintenance alert is written, allowing repair of machines before they fail. In the distribution stage, customers could search the ledger for a product’s complete history, reducing counterfeiting and solidifying the origin of properly sourced goods. When faulty product is identified, the manufacturer may search the ledger to quickly locate the faulty supplier or bad test results and alert all receivers of the defective product.ConclusionWith blockchain, manufacturing can become a more collaborative process among suppliers, manufacturers and customers. Blockchain can help streamline the supply chain and inventory replenishment, improve tracking and regulatory compliance, and reduce counterfeiting. Augmenting blockchain with IoT enables use cases like predictive maintenance and monitoring of goods during transit. Blockchain is not yet mature and its business value still needs to be proven. However, it is poised to help manufacturers decrease costs and fraud, and provide customers with faster, more secure delivery, increased visibility, and consistency.More Resources on Blockchain and ManufacturingTibco is an active member of SEMI’s Smart Manufacturing Technology Community, which holds regular meetings on this and other topics. Join now to help shape the future of Smart Manufacturing. For more information on blockchain use cases in manufacturing, please see these resources. Read this Whitepaper: Blockchain and Manufacturing: A Match Made in the Factory Watch this Webinar: Blockchain and Manufacturing - A Match Made in the Factory Visit the TIBCO Blockchain Solutions page Mike Alperin is a TIBCO principal manufacturing industry consultant embedded in the Data Science team where he applies analytics, machine learning and big data technology to current industry problems. Prior to this he was the product manager for a leading commercial yield management application. He has worked at start-ups and global semiconductor manufacturing companies as a yield manager, device engineer, process engineer and failure analyst. Mike is based in Austin, Texas.

SEMI met with Jay Zhang, business development director at Corning Incorporated, to discuss recent innovations at Corning that allow fine granularity CTE engineering as well as high Young’s modulus. We also talked about the impact of this work on in-process warp control, as well as the associated production methodology that provides rapid prototyping and high-volume manufacturing. We spoke ahead of his presentation at the 3D Systems Summit, 28-30 January, 2019, in Dresden, Germany. To register for the event, please click here.SEMI: What is Corning’s mission and vision and your role within the company?Zhang: Corning is one of the world’s leading innovators in materials science with a track record of 165+ years of life-changing innovations. We excel in glass science, ceramics science, and optical physics and succeed through sustained investment in RD E. Our products include Corning® Gorilla® glass, a durable material used on more than six billion mobile devices worldwide, and industry-leading LCD glass for display applications. We have recently dedicated a unit of the company called Precision Glass Solutions to address the emerging need for glass in the semiconductor industry. Here we apply Corning’s long history of glass science expertise and deep customer relationships in consumer electronics to support cutting-edge applications like wafer-level optics for precise 3D sensing and carrier solutions for temporary bonding applications in semiconductor manufacturing. It’s our most recent work in the Carrier Solutions product line that I’m excited to present: a new carrier glass product optimized for fan-out, called Corning Advanced Packaging Carriers.SEMI: What projects are you currently working on that you think will make a difference in 2019?Zhang: My team is excited to introduce Corning Advanced Packaging Carriers this year. This is a new line of product within our portfolio of Carrier Solutions. These ultra-flat glass carriers are specially developed to reduce customers’ challenge of in-process warp by up to 40 percent, which in turn helps advanced packaging customers achieve better yield.Corning Advanced Packaging Carriers feature high-stiffness properties and are available in a wide range of coefficients of thermal expansion (CTE) in fine granularity. These attributes help customers select an ideal glass carrier that will minimize in-process warp for their package. Furthermore, we make sample quantities of these carriers available in just four to six weeks to help maximize efficiency during customers’ R D process.My team is excited about the potential of this new product, but also encouraged by our results. We have already supplied this product and have heard from one of the largest semiconductor companies in Taiwan that it has reduced in-process warp by as much as 150μm.SEMI: Your presentation at the 3D Systems Summit will focus on Agile Manufacturing of Glass Carriers for Advanced Packaging. What exactly will you be sharing?Zhang: There is a lot of interest right now in using glass as a carrier substrate in temporary bonding applications in advanced semiconductor packaging – especially in fan-out processes. We also know that in-process warp is a significant challenge to companies pursuing advanced packaging because different CTE materials are added during the process. My team has done a lot of work to understand the impact that an ideal CTE glass carrier substrate can have on minimizing in-process warp. We have studied the available levers – both theoretical and in real-life fab environments – that can help address this challenge. I will present our findings on how it is possible to select a glass carrier with the ideal CTE and Young’s modulus to reduce in-process warp by up to 40 percent, and how Corning has developed an agile manufacturing platform to support customers with these ideal carriers from their R D stage through mass production.SEMI: What do you think will be a hot topic in the next few years?Zhang: We expect high-end fanout technology to address more applications beyond just mobile APs. There is also an interesting dynamic playing out between wafer-level and panel-level fan-out technologies. Corning is active in both areas. In developing and offering high performance glass carriers, we hope to help enable our customers to expand the fan-out applications space.SEMI: What are your expectations regarding the summit in Dresden, and why do you recommend your members and other industry leaders to attend the 2019 3D Systems Summit?Zhang: Europe is where some of the most advanced packaging technologies are born. Fan-out also saw early commercialization there. I hope to meet many scientists and technologists at 3D Systems Summit and exchange technical and business ideas. We also hope to get early feedback from other attendees about the value of our new product offering. Serena Brischetto is a marketing and communications manager at SEMI Europe.

SEMI met with Erez Halahmi, vice president at 0eC SA, to discuss a new way to transfer information not only between chips but also between servers to reduce power consumption while boosting performance. The two spoke ahead of his presentation at the 3D Systems Summit, 28-30 January, 2019, in Dresden, Germany. To register for the event, please click here.SEMI: What is Zero energy connection’s (0eC) mission and vision and your role within the company?Halahmi: Prof. Naaman of the Weizmann institute of Science (Israel) and I founded OeC SA and invented the Zero energy connection (0eC) technology. OeC SA offers a completely new and innovative solution for interconnections, which dovetails with the current technological trend of “less is more.” In fact, we constantly search for a reduction in energy consumption in favor of capacity, all while simplifying manufacturing processes. We try to look at things differently. This is why our technology is so out of the box. It is a completely new way to transfer information, not only between chips but also between servers.SEMI: What projects are you currently working on that you think will make a difference in 2019?Halahmi: I am working on several diversified exciting projects including the development of a planar field emitter and a rechargeable battery with energy density higher than 1KWh/Kg. Planar field emission is a field emitter made with standard FAB processes that enable a pixelized matrix of emitters at the resolution of photolithography. The rechargeable battery is a novel battery type that delivers unprecedent energy density.SEMI: Your presentation at the 3D Systems Summit will focus on a new way to transfer data. Why is this a key topic?Halahmi: Metals have been used to transfer data since the realization of the first integrated circuit by Jack Kilby in 1958. What happened next? Photonics slowly entered the market supported by huge investments, and the global market grew over the years. However, even with such enormous growth, photonics is not easily integrated with CMOS processes and the market also faces the conversion energy issue on top of the rising costs of process change. Integrating photonics with CMOS requires converting an electrical signal to a photonic signal and back. This costs energy and adds circuitry complexity. What to do? We identified a need to create something out of the box – on one hand using the same CMOS processes without conversion, and on the other hand significantly increasing performance. More details will be released at my presentation at the 3D Systems Summit in Dresden. I am certain that you will find our invention very intriguing. SEMI: What do you think will be the main focus in the future?Halahmi: My belief regarding many aspects of our life is that history repeats itself. Look for example at the comparison Gallium Arsenide (GaAs) versus Silicon (Si). GaAs was never able to defeat the simplicity of Si. The same applies to data transfer. However, for a solution to overtake the metal interconnect, it is not enough to offer many advantages, but the same order of production simplicity should apply. Consequently, big companies will continue to focus on metal solutions for transferring data, though some smaller companies might adopt our technology due to its relative simplicity of production and great benefits.SEMI: What are your expectations for the summit in Dresden, and why do you recommend other industry leaders to attend the 2019 3D Systems Summit?Halahmi: The summit is a great opportunity to learn about new technologies and meet the people behind these innovations. It is a unique chance to meet and question the inventors themselves and learn more about your competitors. See you soon in Dresden!Serena Brischetto is a marketing and communications manager at SEMI Europe.

SCIS is a SEMI Technology Community that tackles critical component defectivity for the semiconductor manufacturing industry. The organization develops test methods for measuring defects in these critical components. Originally, this SEMI community was looking at challenges surrounding sub-10nm process nodes, but our constituents – Integrated Device Manufacturers (IDMs), capital equipment OEMs, and (sub)component suppliers – felt that the immediate need was for standards that would apply to process nodes that are already being used for volume semiconductor device manufacturing.IDMs need ways to tell their supply chain how defects attributable to these critical components factor into the overall process-node defect budgets and wafer-contamination limits. Chipmakers and IDMs needed to start with a baseline: How problematic are existing critical components in the overall fab systems and how do these contaminants contribute to defects and how do they affect overall process yields?These questions must be answered for every component in the fab’s process line including the drums that hold the fab chemistries, fluid delivery systems, and components used in the wafer-processing chamber. All of these critical fab-line components come into contact with each manufactured wafer, in one way or another, and each is a suspect with respect to contamination, defects, and yield problems. SCIS develops test methods for these fab-line critical components testing that are used to identify the defects caused by these components and for establishing baselines.SCIS has seven working groups dealing with various critical components. Each is developing various test methods for many critical fab-line components. There are many facets with respect to testing each of these critical components.Take something as simple as a seal, such as an FFKM (perfluoroelastomer, made from polymers) seal. These seals are ubiquitous in fab lines. In harsher environments, such as inside of a processing chamber, these seals are exposed to high temperatures and harsh chemistries. Different FFKM seals will have different characteristics such as thermal resistivity and chemical resistance, depending on customer specifications, and can also vary from one manufacturer to another. In addition, these characteristics can change depending on environmental conditions – or just the passage of time.SCIS looks at defect traits from the perspective of each component in the fab line and decides which of the components’ parameters contribute most to process defects. Initially, the SCIS Seals Valves Group collected a list of seal-related issues or parameters. The working group then cross-checked these parameters against different manufacturing processes used in the fab including ALD (atomic layer deposition) and CVD (chemical vapor deposition). Some processes are harder on seals than others. Then the working group prioritized these various parameters according to their contribution to the overall process defect budget. IDMs provided important input during these steps because they work with these seals on a daily basis. At this point, the SCIS working group had a prioritized list of parameters, vetted by various stakeholders in the semiconductor manufacturing industry. The group then set to develop standardized measurement methods for these critical parameters.Based on this work, the SCIS Seals Valves Group has already published two documents. The first is a standard that specifies methods for testing seal-induced impurities such as ashing (analysis of metals content of the ash) and TOC (total organic content).The second document published by the Seals Valves Group is a guide that documents BKMs (best known methods) for handling seals – from the moment they’re cured in an oven to packaging, shipping, handling in a fab, and installation – to reduce contamination problems during use. For example, some seals are sensitive to light. Some polymer seals degrade when they come into contact with IPA (isopropyl alcohol), which is often used for prepping. A degraded seal can emit contamination particles during processing, which will cause yields to fall. (This latter bit of information came directly from a major IDM, which demonstrates the invaluable role that users of these components can play in the development of testing standards.)The Seals Valves Group’s current work focuses on developing a standard for measuring seal leak rates. This standard will define test methods for evaluating a seal’s ability to maintain pressure under vacuum. Although there are well-established standard for testing seal CSR (compressive stress relaxation) in the aerospace industry, there’s no such standard for the semiconductor industry. So originally, the Seals Valves Group tried to tackle that challenge by developing a similar standard for SEMI’s constituents. However, a more practical and immediate parametric challenge turned out to be seal leakage rates.Installed seals are exposed to high temperatures and harsh chemistries in the semiconductor fabrication process. The Seals Valves Group decided to develop a test method that would determine how well seals perform over time with respect to leakage rates as the seals are exposed to cyclic harsh conditions. The goal is to simulate the working conditions for these seals, as closely as possible and in a repeatable manner.There are, of course, some challenges associated with this work. For example, IDMs and equipment OEMs don’t want to reveal their exact process conditions as they are proprietary. So the Seals Valves Group took a step back and focused on developing a test method based solely on exposure to elevated temperatures.Development of this thermal test requires the design of a standardized test jig to help ensure consistent, repeatable tests, shown in Figure 1. Figure 1: Elastomer seal test jig developed by the SCIS Seals Valves Group.The seal under test, shown in red in Figure 1, sits at the center of the jig. A second seal, shown in green, is used to seal the actual test environment. Two thermocouples in the jig’s top and bottom monitor of the temperature inside of the jig. There are gas and purge lines for controlling the ambient pressures on either side of the seal under test.Figure 2 illustrates how the jig is connected to the gas sources. Figure 2: The Seals Test Jig is connected to helium and nitrogen gas sources and to a calibrated leak (vacuum) line. The seals leak test is based on a helium leak test. Helium is one of the smallest atoms so it will leak through just about any small gap and, with time, permeate through the material as well. In addition, helium is inert, and testing for helium using a mass spectrometer is a well-established technique for leak testing. Helium leak testing can be one thousand to one million times more sensitive than using mechanical, pressure-decay test techniques. The jig’s nitrogen lines serve to purge the test chambers of helium between leak tests.Developing just a test jig is not sufficient. The Seals Valves Group also developed a test sequence for using the jig. There were no existing standard, so the group needed to use its knowledge of the seals’ composition and operating conditions to develop certain test parameters. For example, the group elected to use 200°C as the maximum temperature for the high-temperature portion of the test because FFKM seals start to degrade at 250°C.At this point, the Seals Valves Group has gone through several iterations of a proposed test sequence. There was some initial reluctance to provide detailed inputs, but after a few iterations of the proposed method (and an understanding that this would become an industry standard to hold suppliers accountable), inputs have become more forthcoming.This is an excellent example that demonstrates why it’s so important for SCIS working groups to get chipmakers, IDMs, component vendors, and even feedstock materials vendors to participate in these standardization efforts. Standards are far more useful if they’re based on real-world conditions.Currently, the SCIS Seals Valves Group is working towards finalizing the seals-leak test sequence. The jig has been designed in AutoCAD and a prototype will soon be manufactured. Although the test and jig have been developed with significant industry participation, the validity of the test has yet to be determined. The validity will be verified though Alpha testing before the jig design and test method are incorporated into a standard.However, SEMI is not a test house. It’s a facilitator. The testing will therefore be performed by a neutral third party capable of carrying out the test under fab-like conditions. SEMI’s role is to work with different testing entities such as SUNY Polytechnic Institute in Utica, New York or IMEC in Belgium.SEMI will solicit bids for this work through its SCIS Executive Advisory Committee, which consists of C-level executives from device makers, semiconductor capital equipment OEMs, and major critical component suppliers. This project has leveraged many of the relationships that SEMI has developed over the years and has broken new ground in standards making for SCIS and for SEMI.For those looking to learn more about SCIS or engage in ongoing efforts, please contact Paul Trio, senior manager of Strategic Initiatives at SEMI, at [email protected].

The Single Device Traceability Task Force emerged from SEMI CAST’s identification of the need for device traceability through the supply chain — not just traceability for devices but for component parts such as semiconductor die, lead frames, epoxy, bond wires, and printed circuit boards. Eventually the work led to a draft document and preparation for SEMI’s standardization process.The Single Device Traceability Task Force’s charter is “To develop standards enabling traceable device-level identification (ID) throughout the IC manufacturing, test, and assembly processes to the point of use in the final system.” The scope of this work is to develop standard(s) focusing on key concepts, behaviors, and requirements as well as standards for enabling device ID and traceability, with considerations for various types of implementations. In addition, the Single Device Traceability Task Force is looking at anti-counterfeiting, which is closely associated with traceability.The motivation for this particular traceability standard comes from systems companies that purchase and use semiconductors in boards and systems. These companies need the ability to track devices through the supply chain for various reasons. They do not want an ad hoc situation where each system vendor develops its own requirements and specifications for device traceability. They want a standard to reduce traceability’s cost and complexity.In effect, customers want a standard that can be cited in a purchase order to their suppliers. This will require the supplier to mark (ECID, 2D code, RFID, etc.) their products with an ID unique for that supplier. The customer will verify the ability to read the ID and will reject devices that cannot be read, or disagree with the shipping information. This arrangement should propagate throughout the supply chain. As a result, the traceability draft standard developed by the Single Device Traceability Task Force looks at traceability from a system integrator’s perspective.Figure 1 captures the business problem for device traceability. Figure 1: Single Device Identification and Traceability Needs Permeate the Semiconductor Industry.Each time that a company ships product to the next company in the supply chain, it’s desirable to have traceability for the products being shipped while preserving the security of the information associated with those products. Initially, the only information that should be transferred is the device identification. In other words, the device traceability ID should not identify what the device is, nor should it provide any additional information relating to the device or its manufacture. In addition, the Traceability ID should not specify the number of devices shipped, the lot number associated with the devices, or any other information that might be of value to hackers or competitors. There is quite justifiable paranoia about the security of this information based on lessons learned.However, the whole point of traceability is to be able to backtrack a device through the supply chain when there’s a problem. Ultimately, any QA effort will need to know where the device was manufactured, when it was manufactured, the conditions under which it was manufactured, and other details that might help to discover the root cause of any problems.To get the additional information needed to troubleshoot a quality or manufacturing problem, a business relationship and NDAs (shown in Figure 1) must be in place between the various member companies in the supply chain. Traceability IDs based on the Single Device Identification and Traceability Standard will not carry that sort of information. They will simply allow analytic data to be obtained through appropriate business relationships.Figure 2 illustrates the types of fact finding that a Single Device Identification and Traceability standard would enable. Figure 2: Types of fact finding enabled by a Single Device Identification and Traceability standard. In this example, a Fabless or System manufacturer (shown in the center of the figure) might make an assembly that incorporates an MCM (multi-chip module) obtained from an OSAT (outsourced assembly and test) vendor. The MCM would bear a traceability ID on or inside the package. If a failure occurs in the MCM, the Fabless vendor contacts the OSAT, using an existing business relationship and NDA, and requests a comprehensive manufacturing report for the specific device using the traceability ID to identify the device in question. The OSAT then supplies a report to the Fabless company that provides the requested manufacturing data and any additional traceability IDs for the component parts in the MCM.The component traceability IDs in the OSAT’s report provide the Fabless vendor with the ability to track the MCM’s component die and package back to the semiconductor foundries and packaging vendor where these components were manufactured. These traceability IDs allow the Fabless vendor to request manufacturing reports for the components in question from the supplying foundries and the package vendor. Note that the reason that the reports go directly from the semiconductor foundries to the Fabless vendor as shown in Figure 2 is that the OSAT may not have comprehensive information about the function of these die and the Fabless vendor may want to keep that information private.The proposed new standard is called the “Specification for Single Device Traceability for the Supply Chain” and is SEMI Draft Document #6450. It addresses the first part of the systems integrators’ desire of being able to hold their suppliers accountable for having an established traceability scheme that would permit data analysis should the need arises. As of the end of November, the ballot proposal passed Technical Committee review and will undergo a procedural review process as part of the SEMI Standards development requirements. Once, these approval requirements are met, the specification will be prepared for publication and ready for industry adoption. Meanwhile, SEMI’s CAST Working Group and Standards Task Force will continue standardization efforts for device security and anti-counterfeiting. To join SEMI Standards activity, visit SEMI Standards or go directly to the Standards Membership Application.Dave Huntley is in business development at PDF Solutions.

Gas plasmas have become a fundamental building block in many semiconductor manufacturing processes. Plasma torches used to create these gas plasmas have three components: an induction coil, a plasma confinement tube, and a gas distributor or torch head that introduces multiple gases into the torch. RF generators supply the high-frequency electrical energy needed to transform the plasma-forming gases flowing through the torch, typically oxygen or a fluorine-bearing gas, into a plasma. The RF generators used for semiconductor manufacturing typically operate in the low megahertz or tens of megahertz frequency range and are expected to output high RF power at those frequencies for long periods. For example, ALD and CVD processes use RF generators with output powers on the order of a few kilowatts.About three years ago, a major semiconductor device maker experienced a recurring problem with its RF generators. The company found that more than half of the RF generators it deployed in its manufacturing lines were failing within the first two years of service. Further, the same model RF generators obtained from the same RF generator vendor simply were not behaving similarly when used for exactly the same processes under exactly the same conditions. Nor were these supposedly identical generators operating for consistent lengths of time before failing. Clearly there was variation from one generator to the next, even within the same model.A further complication occurred during procurement of these RF generators. Procurement people were acquiring generators using general specification requirements and these requirements were, at times, opaque to the intended process application. In some cases, equipment was being purchased in bulk quantities and then assigned to different processes on the semiconductor manufacturing lines. When these generators were deployed, they had not been designed or optimized for the specific task to which they were assigned, exacerbating the reliability problem.The RF generator suppliers felt that they would be able to supply more reliable generators if they could collaborate with their customers so that they could purpose-build their generators for the intended uses. However, the semiconductor makers preferred to keep the specifics of the manufacturing process applications for these generators proprietary, for obvious reasons. To make matters worse, customers did not always return failed units to RF generator vendors for analysis. Instead, the RF generators were sometimes sent out to be refurbished by third parties or repair depots, and then redeployed. As a result, failure analysis proved challenging to obtain.This is exactly the type of situation that SEMI’s Semiconductor Component, Instrument and Subsystem (SCIS) technical community exists to address. SCIS develops test methods aimed at measuring component defects for the greater semiconductor manufacturing community. SCIS tackled this RF generator problem and developed a standard test method for measuring specific RF generator characteristics. Using this test method, RF generator manufacturers can publish results for their generators in a standardized way that allows their customers to make fair, application-specific comparisons among models and vendors.Many aspects of an RF generator needed to be considered. A key aspect that interested integrated device makers (IDMs) and capital equipment OEMs was a transient-response test for RF generators.A transient-response test standard established by the SEMI-E135 standard did exist, but its tests were run only with 50-ohm RF output loads. SCIS decided to expand this transient-response test by adding high- and low-impedance load tests to the existing 50-ohm load test.The initial response to this plan was not enthusiastic. The semiconductor makers feared that this simple expansion of an existing test standard would not produce a test regimen that would help solve what they considered to be the real problem: RF generator reliability. However, a major semiconductor equipment OEM differed, and felt that the two additional load conditions would provide a much better understanding of an RF generator’s capabilities. A second major semiconductor equipment OEM also got involved by providing additional, valuable feedback on the developing RF generator testing standard.In the end, the general feeling in the community is that this newly revised standard levels the playing field and makes it easier for customers to compare RF generators from different generator vendors. Now that this revised SEMI-E135 standard with the additional output load resistances has been published, the SCIS technical community has gained broader support and is now digging into the creation of a reliability test standard for RF generators to meet the greater semiconductor manufacturing community’s strong need for such a standard.How SEMI Standards are MadeThis sequence of events illustrates how standards are developed at SEMI. The SCIS technical community (or some other technical community within SEMI) develops and incubates test methods until a document is ready for standardization. At that point, a SEMI Standards task force is created. Companies within SCIS work with the task force (or become the task force) to ready the document for standardization. For the SEMI-E135 revision, the list of participating companies encompassed the entire semiconductor manufacturing community including RF generator suppliers, semiconductor capital equipment OEMs, and IDMs. All stakeholders participate.Figure 1 illustrates the sequence of events that occurred during the revision of the SEMI-E135 standard, after the test methods had been developed by SCIS as discussed above. Figure 1: Timeline for SEMI-E135 RF generator test standard revision after SCIS had developed the new load tests. Balloting, as illustrated in Figure 1, is the main way that SEMI obtains global consensus in the standards-making process. To achieve this, SEMI sends out the standard ballot proposal, or in this case a major revision of an existing standard. The changes to SEMI-E135 were sufficiently extensive that it was treated as a complete rewrite to this standard.On first ballot, the revised SEMI-E135 standard received several rejection votes, which also included suggested modifications that would remove the objections. These ballot rejections caused the proposed standard to be further revised, with both technical as well as editorial changes, triggering a SEMI Standards process called a Ratification Ballot. This approach takes less time than starting the balloting process over again. The final revised standard was published in September 2018.Having all stakeholders participate in the early development of the revised standard helped move the standard through the balloting process immensely, but customer participation was especially important. In the end, the semiconductor device makers and equipment OEMs are the ultimate beneficiaries of a standard like SEMI-E135. When end customers help to drive a standard’s development, there’s added pressure to move the standard along in the standardization process and the standard is far more likely to be useful for their purposes.And that’s a very good thing.For those looking to learn more about SCIS or engage in ongoing efforts, please contact Paul Trio, senior manager of Strategic Initiatives at SEMI, at [email protected].