Nvidia

Jay Vleeschhouwer, managing director of Griffin Securities, has followed the EDA industry as a leading financial analyst for 25 years and is a popular speaker at the annual Design Automation Conference. Vleeschhouwer discusses his DAC presentation The State of EDA: A View from Wall Street.

Alameda, Calif.-based Verific Design Automation, a member of the ESD Alliance, made its name in the electronic system design and semiconductor industry supporting companies ranging from startups to billion-dollar industry leaders such as Synopsys, Cadence, Siemens EDA, Xilinx, Microchip, NVidia, Infineon, Qualcomm, Renesas and Samsung. Its software is used as the front end to design automation tools such as synthesis, simulation, debug, and formal verification. I spoke with Verific president and COO Michiel Ligthart about homegrown and open-source EDA tools and other recent trends in chip design. Smith: What trends are you seeing in chip design? Ligthart: Semiconductor companies are starting to build a portfolio of intellectual property, including homegrown electronic design automation (EDA) tools, that they want to keep secure and differentiated from their competitors. The increased interest in internally developed and supported EDA tools is a trend we started to see about two years ago. It’s not simulation, synthesis or place and route (P R). Instead, it’s pieces of a chip design flow optimized for a company’s specific needs. In the past, a semiconductor company would either standardize on one EDA company’s chip design flow or mix and match best-in-class tools from different vendors. The common denominator was that they used off-the-shelf products. If they had a specific requirement, they went to the EDA provider for assistance. In today’s competitive landscape, semiconductor companies are figuring out ways to diversify themselves and their design flow became a way to do so. They may not build their own P R tool, but they will look at building their own power domain approach, for example. Is this a widespread trend? It could be. We hear about it within end-user applications ranging from 5G and AI to data center processors and there are probably others we don’t hear about. Power optimization is an example of the kind of specific internal need being addressed. Smith: What are your thoughts about open-source EDA tools? Ligthart: Our industry supports open source already with language reference manuals (LRMs) for VHDL, SystemVerilog, Unified Power Format (UPF) and the RISC-V Instruction Set. The LRMs and the instruction set are free. Moving to the development of actual tools becomes a question of who will implement, support and maintain the tools. Implementation is expensive. The Big Three (Cadence, Siemens EDA and Synopsys) invest about 35 to 40% of top-line revenue into R D. For smaller EDA companies, this number is even higher. The industry may come up with a business model that will have open-source components as well as a way to fairly reimburse companies that make these tools freely available. I have not seen it yet. Smith: Business Insider reports that Verilog HDL is among the top 10 tech skills that companies are desperate for their employees to learn right. Does Verific get asked about Verilog training? Ligthart: No. Our customers are experienced users. Nonetheless, it was great to read that article and it suggests the semiconductor industry is healthy, growing and hiring talented engineers. Smith: If an entrepreneur asked you for advice about starting an EDA or IP company, what advice would you provide? Ligthart: I would tell the entrepreneur to focus on the problem the startup is solving. Stick to the company’s core competency and try not to build in-house what can be purchased from a reputable supplier. In the end, it will save time and jump-start the development effort, and the engineering budget can be allocated to the startup’s core competency. The external supplier presumably has years of product validation, which brings a major QA gain. About Michiel Ligthart Michiel Ligthart, president and COO of Verific Design Automation, has an extensive background in engineering, product marketing and general management. Prior to joining Verific, Ligthart was vice president and general manager of West Coast operations for Theseus Logic, a startup in asynchronous logic. Before that, he spent eight years with Exemplar Logic in engineering and marketing roles. Ligthart started his career with Philips Research Labs in California and was a visiting scholar at the Center for Integrated Systems at Stanford University. He has a Master of Science degree in Electrical Engineering from Delft University of Technology, the Netherlands. Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community.

Companies around the world are increasingly turning to mergers and acquisitions, research and development, and corporate venture capital (CVC) investment to sustain growth. For many years, global semiconductor companies including Intel, Qualcomm and Samsung have been active CVC investors. However, the economic fallout from the COVID-19 pandemic has forced many venture capital (VC) and CVC investors to rethink their investment strategies as they look to an uncertain future. To help provide SEMI members with the latest market trend information, SEMI Taiwan held the webinar Challenges and Opportunities in Corporate Venturing during the Global Pandemic Crisis on April 28th. Featured speaker James Mawson, founder and editor in chief of Global Corporate Venturing, provided an analysis of the pandemic’s impact on deal flow, capital movement, sentiment and strategies among CVCs. CVC takes larger role in past decadeCorporations have been increasingly active direct and indirect venture investors over the past decade. From 2011-2019, more than US$1.3 trillion of venture capital was invested globally, with corporations accounting for more than half that total, according to data from Pitchbook/GCV Analytics.Semiconductor companies that have been active in corporate venturing include Intel, Samsung, Nvidia, ARM, AMD, SK Hynix, Broadcom and Qualcomm. Pure-play semiconductor and chip companies tend to make few investments in their start-up counterparts because sector saturation of powerful incumbents leaves little opportunity for growth, James said. “While it is hard to find entrepreneurs wanting to be engaged in pure play S C, once they do, they can be very valuable and often be able to bring disruptive forces to the whole ecosystem,” James said.S C corporate investors focus on chip applicationsSemiconductor companies looking beyond pure-play S C start-ups for investment opportunities often target applications or developers that require the additional data, processing power, and memory their chips provide. “There is lots of interest by the big chip companies such as Intel, Qualcomm, and Samsung in developing some of those chip applications, getting them used more and creating a whole ecosystem,” James said.For example, Intel Capital, based on its data-centric theme, has focused on areas like autonomous vehicles, data centers and artificial intelligence (AI) because of the sheer amount of data and processing power they require. In another notable trend, non-traditional S C players such as Apple and Alibaba are leveraging investments in start-ups to develop their own chips for competitive advantage, James said.March deal flow down 20% With COVID-19 slowing the global economy, James expects semiconductor and chip companies to scale back direct investments this year due to rising pressure on their balance sheets. Deal flow in March was down roughly 20% from February.James is hopeful corporates will focus on investing in innovation over the long term rather than target share buybacks to boost near-term earnings. James pointed out that investors can uncover opportunities by identifying future problems to be solved in areas such as quantum computing, biotech, energy, healthcare, communications and ICT. Still, in the near term, where there is a crisis, there is opportunity. While the pandemic hit some sectors hard, it benefits start-ups in industries including gaming, education and telemedicine. This time is different?James said corporates need to rethink the investment model they want to follow. One option is the approach taken by General Electric, which divested its investment team and sold all its portfolio companies last year. Another is to focus on the long term. For example, Intel Capital has been dedicated to investments in innovation for nearly 30 years and continues to invest during downturns.Compared with the internet bubble and global financial crisis, today there are more experienced and mature CVCs that better know how to negotiate a crisis. James also pointed out investors are interested in backing CVCs with sector investing experience. There are now more than 600 CVCs with a 10-year-plus track record.James expects a variety of funding models to emerge over the next decade as pressure on corporate balance sheets encourages corporate investors to consider models that allow third-party capital to effectively leverage their CVC units. Corporate investors are also open to other ways to efficiently deliver financial returns.For more information about the SEMI Taiwan Corporate Growth and Innovation Community, please contact Irene Lin at [email protected]. For GCV’s latest news and event, visit its website.Jo-Ann Su is senior director of the Corporate Growth and Innovation Community at SEMI Taiwan.

New system-on-chip (SoC) devices are driving new memory architectures and photonic interfaces, while specialized new intellectual property (IP) requires analysis down to the nanometer and atomic levels because of single nanometer process nodes. According to Babak Taheri, CTO and EVP of products at Silvaco, a leading EDA Software, semiconductor IP company, a member of SEMI and the ESD Alliance, a SEMI Strategic Association Partner, design technology co-optimization and proven IP are required for this analysis.Taheri recently discussed atoms to systems in next-generation SoC designs with Nanette Collins ahead of ES Design West, co-located with SEMICON West, July 9-11 at the Moscone Center in San Francisco.ESD Alliance: For years now, the assumption is that each new chip design is more complex than the last. Why are the latest SoC designs even more complex than before?Taheri: New SoC devices for mobile phones, automobiles, intelligent edge nodes, big data compute and storage are adopting artificial intelligence and machine learning technologies. This is driving new compute, data flow, as well as memory architectures that are bandwidth-limited and some require photonic interfaces.One common denominator in present SoC design are the numerous blocks of IP. On average, over 85% of these blocks are reused. It’s cost-prohibitive to make these chips over and over again with new IP. According to some estimates, 90% of IP used in an SoC design by 2025 will be reused – only 10% is new technologies. That 10% is significant.ESD Alliance: How so?Taheri: Complex new technologies including flash memory, other advanced non-volatile memory technologies such as MRAM, RRAM and SoCs such as NVIDIA’s Xavier and Apple’s A12 use and reuse design IP at the architectural level.New technologies mean new materials and new processes. Single nanometer process nodes require specialized new IP that needs to be simulated and analyzed down to the nanometer and atomic levels.ESD Alliance: Does the atomic level changes the design equation?Taheri: Yes, it does. Designers need to be able to simulate at the atomic level and understand properties of these materials, and how they behave in at-process and at-device levels. They need be able to simulate the material's nanometer geometries, how molecules behave and how they interact for device operations. When they put together a process and a device, they need to know how the pieces behave and simulate before production.In other words, they run quite a few design experiments and quite a bit of simulation before they finalize the circuits and devices to silicon to save money.ESD Alliance: It’s obvious design automation will continue to have a vital role in design.Taheri: Yes, absolutely. Design technology co-optimization (DTCO) using TCAD solutions and proven design IP are needed to address the span from architecture to device and process physics. The importance of simulation, emulation and design technology co-optimization, along with fully verified and proven IP for SoC design, cannot be overstated. As designers generate devices and processors, they take that up to circuit-level simulation and high-level simulation, schematic capture, extractions and back annotation. They can go from atoms to simulating systems to the ability to do that under the same umbrella in order to get better chips, better yield and lower cost.Taheri’s talk Next Generation of SoC Design: From Atoms to Systems will be part of the Meet the Experts More than Moore session Tuesday, July 9, at 11:30 a.m. at the ES Design West SMART Design Pavilion. SEMICON West attendees are invited to Moscone Center’s South Hall to learn more about electronic system and semiconductor design and its links to the electronic product manufacturing and supply chain. Register for ES Design West or SEMICON West.Babak Taheri is Silvaco’s CTO and EVP of products, has more than 25 years of design experience. His current role managing Silvaco’s Technology CAD (TCAD), electronic design automation (EDA) and IP product divisions makes him an expert on what’s needed for the design of next-generation system-on-chips (SoCs). Previously, he was the CEO and president of IBT working with investors, private equity firms, and startups on M A, technology and business diligence. Babak received his Ph.D. in biomedical engineering from the University of California Davis with Bachelor of Science degrees in Electrical Engineering and Computer Science and Neurosciences. He has published more than 20 articles and holds 28 issued patents.Nanette Collins is a public relations representative for the Electronic System Design Alliance.