integrated circuits

Leading experts gathered at the Power and Opto Semiconductor Forum at SEMICON Taiwan 2022 last year to discuss the growing importance of the devices in semiconductor innovation as the chip industry works to develop a robust compound semiconductor ecosystem.

With the emergence of consolidation as a potent engine of semiconductor industry growth, global mergers and acquisitions are sweeping the industry as companies look to accelerate advances across segments including data centers, AI, IoT and automotive chips.

SEMI spoke with Christian Driller, Vice President of Research and Development at Comet Yxlon, about opportunities to accelerate time-to-market and increase yield for advanced packaging manufacturers through x-ray inspection.

Electronics industry experts will offer insights into key aspects of the radio frequency (RF) challenge – from materials and devices to ICs and modules – at ITF Beyond 5G at SEMICON Europa 2022, Nov. 15-18 in Munich, Germany.

Atomic Layer Deposition (ALD) players are poised to seize a new growth opportunity after the chip shortage pushed manufacturers to announce fab capacity expansions worldwide. Driven by the wafer production volume increase, ALD solutions are now expected to grow and enter the MtM devices market.

Anna Fontanelli, Monozukuri’s founder and CEO, is an expert in deep-submicron silicon technology and design tools shares her view on the state of Moore’s Law and challenges surrounding 2.5D integration, 3D chip stacking & advanced packaging, as well as the chip design industry’s startup environment.

Throughout the current millennium, System-on-Chip (SoC) has been the gold standard for optimizing performance and cost of complete electronic systems. By incorporating practically all the phone’s digital plus analog capabilities onto a single, giant chip, the mobile phone processor serves as a near-perfect exemplar of SoC. But today’s leading integrated circuits (IC) are pushing up against the upper limit of a chip’s size which is limited by the manufacturing equipment’s optical reticle size. This has proven difficult to increase and has grown only slowly over the years. Yet market pressure continues unabated for bigger, more capable electronic systems with more integrated memory, more digital logic, and more analog/mixed signal circuitry. An emerging solution to this tension is 3D and 2.5D multi-die chip assemblies – often referred to as 3D-IC. The key technology breakthrough of 3D-IC is that it makes it possible to spread a system out over multiple, smaller chips that are then assembled close together and interconnected with high-speed, low-power interconnect technologies. By abandoning the need to integrate an entire system on a single SoC and instead allowing it to be disaggregated over multiple chips, 3D-IC enables Moore’s Law to break through the reticle size barrier, improves yield by shrinking the size of individual chips, and makes it possible to mix different process technologies optimized for each function. The Four Engines Driving Semiconductor Design The road forward is not without its challenges, however, and we are seeing design companies making significant efforts to adapt and come to grips with the following four technology and market drivers: The requirement for concurrent multiphysics analysis to ensure reliable and efficient electronic systems The blurring of the lines between silicon and system The need for open and inclusive multiphysics platforms that interoperate with the multitude of design platforms The need for, and value of, bespoke silicon for hyperscalers and system companies Blurring of Silicon and System Design The advent of 3D-IC opens up new horizons for solutions that can be implemented in silicon. But it also forces a closer integration between two distinct technology markets that have co-existed symbiotically for many decades: IC design and printed circuit board (PCB) design. These markets use different tools, different data formats, different manufacturing back-ends, operate at different computational and geometric scales, and focus on different physical concerns. Yet, 3D-ICs share many aspects of both markets: They include monolithic chips but also board-like substrates to stitch the chips together. And in between the two disciplines is packaging, a completely different domain that is requiring companies to re-imagine their design capabilities and flows, as well as their organizational structure. Open, Extensible Multiphysics Platforms The siloed isolation of chip design from PCB design and package design means that each of these markets has developed insular data structures that are ill-suited to deal with the breadth of multiphysics analysis for 3D-IC design. Many different physical disciplines, including computational fluid dynamics, mechanical stress, and electromagnetic radiation, all need to work together based on open and extensible multiphysics platforms. These platforms must embrace the modern cloud compute paradigm and enable an ecosystem by allowing individual design platforms to connect for comprehensive multiphysics analysis. Bespoke Chips Today’s market-leading companies are heavily dependent on technology for their continued success and market differentiation. Everybody from online retailers to telecommunications to social networking companies and hyperscalers are moving away from off-the-shelf solutions and turning to custom-built silicon to give them an edge. Many of these companies are seeking to gain market share by leveraging proprietary AI/ML algorithms trained on their extensive troves of market data – but this requires huge amounts of compute power and specialized chips. Access to high-quality silicon solutions is vital in today’s world and the demand is for continually more complex and powerful electronics. 3D-IC an Inflection Point in Electronic Design To be sure, 3D-IC design is at an inflection point in electronic design and presents major challenges that are realigning the electronic design industry around this new reality. For more insights on this topic from a semiconductor industry leader, please view the Keynote Address 2.5D and 3D – The Road Ahead by Vicki Mitchell, VP Engineering, Arm Central Engineering Systems Group presented at the latest Ansys IDEAS Forum. And for an EDA perspective, please view Successful 2.5D and 3D Multi-die Silicon System Design Using Synopsys’ 3DIC Compiler and Ansys’ Multiphysics Analysis from Synopsys SNUG World 2021. About John Lee John Lee is general manager and vice president of the Ansys Electronics and Semiconductor Business Unit. Lee co-founded and served as CEO of Gear Design Solutions (now Ansys), developer of the first purpose-built big data platform for integrated circuit design. He cofounded two other startups (Mojave Design and Performance Signal Integrity), which successfully exited into companies now part of Synopsys. He holds undergraduate and graduate degrees from Carnegie Mellon University.

A change is underway in the manufacturing sector as the use of curvilinear shapes on photomasks grows, leading to the real possibility of curvilinear shapes in designs. It may just be the start of a revolution away from Manhattan or rectangular shapes to curvilinear shapes. Changing the physical design infrastructure to be curvilinear seems too daunting a task. Are curvilinear shapes in designs a real possibility? I turned to Aki Fujimura, CEO of D2S, a member of the ESD Alliance, a SEMI Technology Community, to further explain the shape of the future. Smith: What is the difference between Manhattan and curvilinear shapes? Fujimura: Manufactured masks and wafers are all curvilinear, even if the input CAD geometries are rectilinear (shown in Figure 1). It’s always been true that nature can’t make 90-degree turns, so sharp corners were always a matter of how closely you looked. These days, at the leading-edge nodes and their required resolutions, wafers and even masks are all visibly curvilinear as you can see in the graphic on the left in Figure 2. Since the 1980s, both chip design and chip manufacturing systems have used axis-aligned rectangles, or “Manhattan” geometries, because 1) that was sufficient to design transistors and interconnect for the most part, and 2) CPU-based computer algorithms can be made much more efficient for Manhattan geometries. Curvilinear shapes can be piecewise linear polygons of some resolution, or spline-like formats that are curvilinear at any resolution, or specific curved patterns like circles and ovals. Figure 1: All shapes on masks and wafers are curvilinear, even if the input geometries are Manhattan. Source: D2S Smith: What are the benefits of curvilinear masks? Fujimura: The manufacturing side of the semiconductor community knows that the best possible process window for wafer lithography is obtained by using curvilinear correction of mask shapes instead of Manhattan shapes. There have been numerous studies on the topic over several decades. The technique to generate purely curvilinear mask shapes is known as inverse lithography technology or ILT and is an advanced form of optical proximity correction (OPC). At a February 2020 eBeam Initiative event, Micron Technology presented a study showing process window improvement up to 85% for advanced memory designs as a result of using curvilinear ILT (shown in Figure 2). Additionally, Ryan Pearman from D2S presented a study at Photomask Japan 2019 showing that it is preferable to move toward a completely curvilinear paradigm, not only because ILT is better, but because the mask manufactured will have reduced variability. Figure 2: Micron Technology explained the benefits of curvilinear mask shapes for advanced memory at the eBeam Initiative event during 2020 SPIE Advanced Lithography Conference. Source: Micron Technology Smith: If the benefits have been known for decades, why is it happening only now? Fujimura: Several things happened at the same time. Multi-beam mask writing is now available. GPU acceleration for general computing has become mainstream. And wafer process window (resilience to manufacturing variation) is increasingly a problem for the leading-edge nodes as we are in the 5nm node, going to 3nm. Curvilinear ILT is needed much more now than before, will soon be needed for EUV lithography too, and is now possible because of multi-beam mask writing and GPU acceleration. Smith: Curvilinear mask shapes enable curvilinear design shapes too? Fujimura: Adoption of curvilinear mask shapes is the first step in targeting curvilinear shapes on wafers. Without curvilinear masks, it is difficult to target and reliably manufacture curvilinear designs. Curvilinear ILT works in the pixel-space to output the desired mask shape to maximize the process window for wafer lithography. A side effect of curvilinear ILT is that it can also take curvilinear targets as input. ILT, most likely GPU-accelerated ILT, works with rasterized input data, so the ILT algorithm itself is not affected even in runtime by having any amount of curvilinear design data. The resulting mask shapes are written in multi-beam mask writers, which write pixels with doses. They too will write curvilinear masks at the same speed as Manhattan masks. Suddenly now, curvilinear designs can be handled by chip manufacturing equally well for the first time in about 30 years. Smith: But curvilinear designs would be hard, right? There are a lot of tools that depend on the Manhattan assumption. Fujimura: Yes, you’re right. We’re not going to suddenly see chips that have curvilinear routing all over the place, or curvilinear intra-connect in standard cells or memory cells. The entire physical design infrastructure that includes place and route, timing, custom layout, parasitic extraction and design rule checking moving to curvilinear design all at once is extremely unlikely. Could portions of these problems be tackled for specific cases over time as “hot spot” solutions? With GPU-accelerated SPICE being available now, as an example, if GPU acceleration is adopted for design, the same transformation that happened in manufacturing can (gradually) happen in design too. The key question is whether it’s worth the trouble. Smith: Is it worth the trouble? Fujimura: I don’t know if it’s worth the trouble for the entire infrastructure. For hot spots, “hot” for various reasons, there are certainly benefits. Jogging a 32-bit bus by one grid is certainly much more economical space-wise with curvilinear shapes. Inside standard cells or memory cells, there are certain types of features that pack better with curvilinear designs. In general, interconnect is the limiter to chip size of course, but there are always critical areas that could use help to shrink. There are manufacturability benefits as well. In general, when something changes so drastically as this for the first time in 30 years, there’s bound to be some innovation that takes advantage of the discontinuity. Let’s see what the combined capitalistic power of the entire community might be able to come up with. The first thing is to let everyone know that curvilinear designs will be manufacturable today. Hear insights from other leading electronic system design industry CEOs at the SEMI ESD Alliance CEO Outlook on May 18, 2021, 2:00pm-3:00pm PDT. Panelists will discuss the state of the industry along with their views of the outlook for the coming years. Registration is free for SEMI members. About Bob Smith Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community. He is responsible for the management and operations of the ESD Alliance, an international association of companies providing goods and services throughout the semiconductor design ecosystem.

Even though microchips continue to get smarter, vital security gaps continue to be exposed through such hack attacks as Meltdown, Spectre, and in recent weeks, Plundervolt. Researchers continue to discover open doors in chip architectures for malicious players to steal increasingly sensitive data, hide the identity of counterfeits, or tamper with electronics systems most anywhere along the global microelectronics supply chain. Today, it’s impossible to have full visibility of the distributed chip making process – from design and fabrication to packaging, testing and delivery. That’s why our industry’s future hinges to a large degree on establishing a hardware root of trust throughout the silicon’s operational lifecycle. Trust but verify! It’s easy to say, but how do we do it?To gain insights, SEMI interviewed Dr. Mark Tehranipoor, currently the Intel Charles E. Young Preeminence Endowed Chair Professor in Cybersecurity at the University of Florida’s Electrical and Computer Engineering Department. A foremost authority on microelectronics security and trust, counterfeit electronics detection, and supply chain risk management, Dr. Tehranipoor will be a keynote speaker at the SEMICON Taiwan Security on Chip Summit, Friday, September 25, where a full program of industry leaders will address key security challenges and solutions involving IoT, systems on a chip (SoCs), integrated circuits, physical unclonable function (PUF) technology, future design, certifications, managed services, and more.For additional insights and to hear Dr. Tehranipoor’s full presentation, register for SEMICON Taiwan 2020, which SEMI is holding as a hybrid event with both a virtual format and an in-show program September 23-25.SEMI: What are the major uncertainties in providing the hardware root of trust within the cyber domain?Tehranipoor: One of the most critical issues we’re dealing with now is loss of control over the process of designing and fabricating integrated circuits and systems. This has happened along with globalization and the movement of supply chain operations overseas to lower costs of nearly all goods, including electronics products and semiconductors. As skill sets, talent, design and fabrication have all shifted offshore, concerns have also risen about security controls across the many different segments of the microelectronics supply chain.For example, when you think about the security of military, space, transportation, power grids, financial or other networks, it becomes a major concern if you cannot trust the underlying electronics system that runs them. New SoCs are also holding more sensitive data around encryption keys, biometrics, personal information or banking data. And as reports escalate about cybersecurity gaps at the electronics part level, it’s increasingly important to establish a hardware root of trust. Today, it’s not enough for a buyer to just call up the design house and verify the electronic ID of an asset. The ID might match, but the device could have been tampered with or replaced with a counterfeit somewhere along its end-to-end journey. Unlike software or networks where problems can be automatically identified, upgraded and fixed, verifying electronic hardware is a costly and time-consuming process, especially when they’re as complex as microchips. It can take months to deconstruct, reverse engineer, inspect, and authenticate a chip. By then, discovery of any security breaches is too late.When addressing the security of electronics systems, there are three important features to keep in mind. First, there’s confidentiality. The device shouldn’t leak information to an unauthorized user. Second, there’s integrity. Unauthorized users should not be able to manipulate an SoC’s sensitive data. The third feature is availability, which can be a result of Denial of Service (DoS) attacks. If the device is under attack and can’t access your online service or network, you must still have security measures for your electronics system to be available in a safe mode while you simultaneously identify the problem, recover from it, and return to normal functions.SEMI: What framework should be followed to establish greater trust and confidence across the entire microelectronics supply chain?Tehranipoor: In the United States, we recognize it may not be possible to bring all manufacturing, design, and delivery teams back to this country and have them certified by the U.S. Department of Defense. You could do some of it, but it would be very costly and complex to bring back all the design, fab, testing, and packaging operations involved with electronics systems and still have complete control.The most practical approach is to make sure we design electronic systems with security and trust in mind from the start. We need to provide security features up front throughout the extended supply chain – into the design flow, fab flow, and out into the field to make it easier and faster for anyone at any point to verify the authenticity of an electronic system as well as identify and mitigate a problem. Finally, we have to remember that we are all in this together – designers, developers, packaging facilities and fabs. We can’t just blame semiconductor manufacturers or any other single entity. As a result, we must be cooperative and collaborative by focusing on this issue as a consortium. Everyone in this ecosystem must come to the table, share best practices, establish standards, and initiate best practices for device to system authentication.SEMI: How can SEMI and the SEMI Electronic System Design (ESD) Alliance help the industry meet these challenges?Tehranipoor: It’s certainly of utmost importance for members of organizations like SEMI and its ESD Alliance committees to jointly develop and adhere to standards or guidelines that establish hardware root of trust across all participants in the global supply chain. At the same time, such alliances should make it a high priority to protect each company’s intellectual property (IP). Collectively, we need resolutions that allow us to develop unique IPs and more easily trace, identify, and verify the authenticity of electronics systems as they flow throughout the end-to-end electronic supply chain. Great efforts are under way and progress is being made. But it’s not enough. Clearly, more needs to be done to establish root of trust standards at the chip level.I can’t emphasize enough the importance of consortia like the SEMI ESD Alliance to create an environment where industry, government, and academia can come together, share best practices and even case studies on how they handled security vulnerabilities and breaches. We understand that not everyone wants to share their security problems, vulnerabilities, or attack surfaces, but learning from each other’s experiences can have a tremendous impact on industrywide progress. If you don’t know what you need to address, you won’t be able to address it when it happens.I also encourage organizations like SEMI to create standards or guidelines that reduce the complexity of microchip designs for security purposes. Realtors often say there are three things to consider in finding a home that will appreciate in value: Location, location, location. To build more secure electronics systems, my mantra is: Automation, automation, automation. Complexity is the enemy of security. By using automation to simplify security mechanisms and detect inconsistencies, it will be easier to find and fix security problems, not to mention lower costs at the same time. SEMI: What will an attendee take away from your talk at SEMICON Taiwan?Tehranipoor: I have a large team of researchers who day and night spot vulnerabilities by attacking and assessing data from different electronic systems set up in our labs. Attendees will see real-world examples and lab animations that show how electronics systems can be hacked most anywhere across the supply chain. They will also learn about step-by-step security solutions we have developed at the microchip level. We need to do a better job of protecting the security of our semiconductor assets and the electronic solutions or services they power. My call to action will be that we need to invest more in research and foster an environment of more open trust and cooperation. We can do this by bringing together different countries, companies, and organizations in the microelectronics ecosystem to overcome this major challenge.Dr. Mark Tehranipoor is currently the Intel Charles E. Young Preeminence Endowed Chair Professor in Cybersecurity at the ECE Department, University of Florida. He is currently serving as Director for Florida Institute for Cybersecurity Research (FICS), National Microelectronics Security Training Center (MEST), CYAN Center of Excellence, and ECI Transition Center. He also serves as Program Director of Cybersecurity for UF Herbert Wertheim College of Engineering. His current research interests include IoT security, hardware security and trust, and reliable circuit design.Samer Bahou is senior manager of corporate communications at SEMI.

The COVID-19 pandemic has inflicted major impacts on manufacturing operations worldwide including in the semiconductor industry. The virus has left millions of people confined to their homes, resulting in a massive shift to virtual work and online engagement. In Singapore, where AEM is headquartered, our management team took proactive measures to protect our workers by implementing best practices ahead of the Singapore Circuit Breakers.AEM is globally deemed an essential service, requiring us to maintain operations and minimize impact to our customers. Business continuity plans that include work-from-home and safe-distancing guidelines are in place. As of the time of this writing, we are very fortunate that all of our employees are safe and that we’ve seen only minimal impacts to our customer commitments. AEM has confined this impact by spreading operational risks across our facilities in Asia, Europe, the U.S. and divisions in Singapore, Malaysia, China, North America, Central America, Finland, France and Vietnam. All told, these facilities employ more than 550 people (Figure 1).Figure 1 – AEM Global Presence As a global leader, AEM offers application-specific intelligent system-level test and handling solutions for semiconductor and electronics companies that serve the advanced computing, 5G communications and artificial intelligence (AI) markets.Leveraging our decade of experience, the latest AMPS solutions provide asynchronous, modular, massively parallel and smart system-level testing to meet the new test challenges of complex ICs. The modularity and scalability of these systems enables customers to scale their existing engineering device validation solutions into high-volume, massively parallel production solutions that increase faults coverage, reduces time to market, and decreases cost of test and ownership (Figure 2).Figure 2 – AMPS System-Level Test Solution In meeting 5G infrastructure test needs, AEM developed a field-deployable fiber optics tester. Called WideOptix SR4, the system was initially developed in collaboration with a world leader to support the 5G fiber infrastructure deployment in China and has now been adopted for some Ethernet standards testing. With our WideOptix SR4 development, we cultivated Silicon Photonics (SiPh) testing expertise that complements our AMPS system-level test capability. As part of our business continuation and risk diversifications plan, we had also set up factories in Penang (5,200m2) and Suzhou (3,600m2). Penang’s rising influence in the Southeast Asia semiconductor industry has prompted AMM (AEM Malaysia) to expand its scope to include value-added services with a Center of SSD Excellence and Center of Photonic Excellence.ASZ (AEM Suzhou) will continue to focus on the domestic market in China for further expansion and penetration with products ranging from cost-sensitive testers to state-of-the-art test measurement instruments. In Europe, AEM is focused on wafer-level test and cost-effective ATE test solutions. Finland-based AFORE specializes in MEMS and application-specific wafer testing with the ability to add physical stimulus. The company's state-of-the-art instruments enable the testing of devices such as diced IMU’s (Inertia and Motion Units) in continuous rotation on a wafer mounting ring. Our process increased test throughput by 3X compared to the traditional pick-and-place methods (Figure 3).Figure 3 – Wafer-Level Test Throughput Advantage A specialist in application-specific wafer handling, AFORE developed its latest design to support quantum computing in collaboration with its partner BLUE FORS. The company’s probing equipment features a handling solution with temperature tolerances to 2K (-270’C) to support cryogenic testing (Figure 4).Figure 4 – Cryogenic Quantum Computing Probing Solution AFORE also gained critical insights into creating total darkness, enabling us to further explore opportunities for dark matter testing. AFORE is currently in talks with a member of the LUX Photonics Consortium funded by the National Research Foundation (Singapore) to provide a dark body testing environment and handling for its IR detectors.In Europe, our acquisition of Mu-TEST in France helps diversify our product and service offerings while spreading our business continuity risks. Mu-TEST enjoys collective test-development experience of more than 320 man-years thanks to various ATE suppliers including Schlumberger and Credence. To help combat rising costs of traditional ATE, Mu-TEST developed cost-effective solutions using FPGA-based instruments supported by a full suite of test development, debug and production test software with links to EDA and standard interfaces. This provides Mu-TEST an agile platform that can be easily re-configured for different customer needs.This Mu-Test acquisition expands AEM’s system-level testing capability to include Functional Test, allowing BIST, SCAN, JTAG to test structural failures and perform other application-level test that interface directly with the DUT using the EVM (Electronics Validation) boards to increase fault coverage within the same test environment. Mu-TEST has also enabled AEM to form the recent partnership with UTAC to develop a cost-effective CIS test solution that addresses UTAC’s test needs and complements its CIS advanced packaging solutions. Our U.S. headquarters based in Chandler, Arizona has expanded its capabilities to provide application engineering.In summary, AEM has been expanding its global footprint while managing risk and has been fortunate to be positioned to manage the recent COVID-19 excursions. While each geographical location specializes in core technologies, all sites have access to one another’s manufacturing facilities in times of need and a pool of IP available to address new opportunities. We believe this risk diversification positions us well to serve the needs and interests of our customers worldwide.Lo Wee Tick is Director, Business Development, and Stuart Pearce is Senior Director, Field Marketing, at AEM Holdings Ltd.