FPGA

Founded in 2004, S2C’s worldwide customer base uses its desktop and enterprise field programmable gate array (FPGA) prototyping tools to verify system on chip (SoC) and application-specific integrated circuit (ASIC) designs will work as intended.

In the early 1990s, engineers of varying degrees of skill with a powerful PC set up shop designing and selling blocks or libraries of reusable components with a defined interface and behavior. These blocks, known as intellectual property, or IP, were then (and still are) integrated into a larger design. While the new market segment created excitement and new opportunities, it also was untested and created uncertainty. Many fledgling companies failed. It’s a different story today. Arm, as well as Cadence and Synopsys, are silicon IP suppliers and the segment’s yearly revenue tops $4 billion, a long way from those early garage startup days. ESD Alliance member CAST, a silicon IP provider since 1993, participated in the remarkable growth and impact on the semiconductor industry. Nikos Zervas, CAST’s CEO, and I discuss those early days of the IP business and what’s ahead. Smith: What were the early days of silicon IP like? Zervas: In those early Wild West days of IP, vendors and customers both wanted to benefit from IP, but nothing was standardized, and people just tried things to see if they worked. The perceived barrier to entry was low: hundreds of IP companies sprang up thinking they only needed RTL coding skills and tools, an FPGA to prototype, and a few thousand dollars to invest. IP deliverables, quality standards, and business practices varied from vendor to vendor and over time. Risk was high, and there are many horror stories of re-spins or market failures due to faulty IP cores. Smith: How has the silicon IP market changed from its early days? Zervas: Firms delivering high-quality IP and providing outstanding customer support survived. Others disappeared. Eventually the industry centered around a reasonably common sense of IP requirements and quality and a consistent set of business practices. IP product complexity has driven upwards as SoCs have grown. The largest ASICs used to approach a few million gates; today they’re hundreds of millions, and the granularity of IP has evolved from small functions to pre-integrated subsystems. Early on, a designer doing image processing might license individual functions like a Finite Impulse Response (FIR) filter or a Discrete Cosine Transfer (DCT) block. Today, instead they would license a complete JPEG compression core containing those functions and more, or even a complete black box subsystem streaming processed, stabilized, compressed video over Ethernet. IP selection criteria have also changed. Early IP was handcrafted to eliminate every extra gate, as being a few thousand gates smaller was a killer advantage in the era of 180nm ASIC processes. Today, at 7nm or 5nm process, tens of thousands gate differences are just noise, and it’s usually the reliability, functionality, and performance of an IP core that matter most. Smith: When did the silicon IP market start to take off? What was the driving force? Zervas: By the early to mid 2000s, uncertainty about what IP was and how best to use it – and the early wave of less-than-great providers – were being replaced by increasing acceptance and emerging best practices. The introduction of smartphones, the wild growth of Internet of Things applications, growing automotive system sophistication, and other advances fueled the explosion of the IP market in the late 2000s. In fact, according to the ESD Alliance Electronic Design Market Data Report, revenue from IP licensing today has surpassed the license revenue from front-end EDA tools. This would have been unimaginable in the late 1990s. Smith: How has silicon IP changed chip design? Zervas: Designers today must develop massive, complex systems with an even tighter time to market. Only the higher level of design abstraction and the distributed expertise that silicon IP provides make this possible. But IP also increases the challenge of differentiation: With the same IP available to everyone, how do you design a product that stands out in its market? The answer to differentiation today lies mainly in clever SoC architecture. Delivering better features with superior performance, lower power consumption, or other winning characteristics now depends not so much on perfecting each separate IP block but rather from selecting the best IP for the system’s requirements, integrating those IP cores for clean communication and efficient resource sharing, and other smart system-level decisions. It’s similar to modern building design: Every firm has access to the same materials and tools – concrete, glass, etc. – but only a few produce exceptional buildings. Smith: It seems that are several different business models for IP licensing, such as up-front license fees, subscriptions, royalties, or a combination of these. Do you think the IP market will gradually align around one basic model, or will it continue as is with a variety? Zervas: Different models serve different needs. For example, commodity IP like a SPI interface can’t demand royalties, but unique, leading-edge IP – like a 112Gbps SERDES – still can. I believe the market will continue with different business models, though the number of different models may shrink and their terms begin to align. About Nikos Zervas Dr. Nikos Zervas is the chief executive officer of CAST, Inc. He co-founded image and video compression IP developer Alma Technologies in 2001, and led the bootstrapped firm as chairman and CEO for nine years before joining CAST. He was a founding member of the Hellenic Semiconductor Industry Association and served on its board for several years with responsibility for strategic planning. He is a senior IEEE member and member of the Technical Chambers of Greece, had contributed to the GSIA's IP Working Group, and has published multiple technical papers on data compression design and related topics. Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community.

As monolithic scaling slows down, the semiconductor industry is increasingly relying on advanced packaging technologies to extend Moore’s law through heterogeneous integration. Higher on-package bandwidth, improved yield resiliency and the need to integrate diverse IP from multiple foundries are driving demand for advanced packaging technologies that address these issues but introduce challenges of their own such as efficient power delivery to all the different domains in a heterogeneous system. SEMI spoke with Kaladhar Radhakrishnan, Intel Fellow at Intel, about heterogeneous system integration trends and new developments in the semiconductor industry. Radhakrishnan shared his views ahead of his keynote at the SEMI Connecting Heterogeneous Systems Summit, 1-3 September 2021, an online event. Join the summit to meet experts from Intel and other key industry influencers. Registration is open. SEMI: What is driving the adoption of electronics and semiconductor devices nowadays and why is the development of new and innovative technologies important? Radhakrishnan: We are living in an increasingly data-driven world where devices have become an integral part of our lives. A recent study estimated that in the United States alone, 13.6 connected devices per capita consume an average of 300 gigabytes worth of data every month. In the workplace, COVID-19 has driven fundamental business changes that has sped up the adoption of digital technologies such as virtual conferencing, remote work, and e-commerce. Organizations are realizing that a high-quality video conference can be an adequate substitute for many in-person meetings. As a result, businesses are accelerating the digital transformation in order to adapt and thrive in this new environment. Five decades of sustained exponential growth in semiconductor performance has conditioned the average digital consumer to expect more from their devices. However, there are some headwinds ahead as traditional scaling slows down and power density rises. Because consumers and businesses are now generating data at a faster rate than they can consume it, technologists need to scale compute, storage, and bandwidth even faster to keep pace. Without investments in research and development of new and innovative technologies to address these challenges, the full potential of this data will go unrealized. SEMI: What forces are heightening the importance of heterogeneous system integration? What are the implications for increased on-package bandwidth, improved yield resiliency and the need to integrate diverse IP from multiple foundries? Radhakrishnan: The semiconductor industry increased transistor density and scaled performance through classical Dennard scaling until the turn of the century. By then, the gate oxide thickness had scaled down to atomic dimensions and the exponential increase in sub-threshold leakage signaled the end of scaling through traditional methods. Since that time, the chip industry has been relying on innovations in transistor materials and structures such as high-k metal gate, strained silicon, and FinFETs to keep pace with Moore’s law. However, this alone will not be sufficient to continue scaling and the industry needs to explore other vectors to augment improvements in transistor technology. Heterogeneous integration through advanced packaging is one key technology that can help drive these gains. Technologies like Foveros can enable device density scaling by creating a 3D stack of multiple die using high-density interconnects. Heterogeneous integration enables chipmakers to move from a monolithic system designed on a single large chip to a heterogeneous system comprised of a number of smaller chiplets. The main benefit of using smaller chiplets is that they improve yield and enable application based customization of the foundry processes. However, if the disaggregation to smaller chiplets is not accompanied by an increase in on-package bandwidth, the power and performance penalties associated with chiplet-to-chiplet communication will hobble system performance. This is why advanced packaging technologies that improve die-to-die communication are key enablers for heterogeneous integration. SEMI: What are some of the key technology challenges in developing heterogeneous systems? Radhakrishnan: The obvious challenge that most people focus on is the need for improved on-package bandwidth. However, as we rely on 3D stacking to continue device scaling at the package level, it is important to comprehend power delivery and thermal challenges as well. Power to the top die has to be delivered through TSVs on the bottom die, which not only adds resistance but also reduces the useful area available on the bottom die. This problem is further exacerbated when we stack more than two die. Excessive noise on the power delivery network can cause timing issues that limit the maximum operating frequency of the transistor. Similarly, when we stack multiple die, we must take into account associated thermal challenges. For example, each interface of the multi-die stack adds thermal resistance, which makes it harder to cool the chips at the bottom. SEMI: What are some of the key global market trends that driving demand for heterogeneous and system-level integration? Radhakrishnan: The number of artificial intelligence (AI) and machine learning applications have grown dramatically due to their ability to solve highly complex problems across a wide range of segments. AI and machine learning models require more memory bandwidth and compute capabilities that are difficult to achieve without some form of heterogeneous integration. Another market trend driving demand for heterogeneous integration is the increasing reliance on custom hardware accelerators. To combat the slowdown in frequency scaling and single-core performance, we have moved to multi-core architectures by tackling the inherent parallelism in our workloads. However, Amdahl’s law tells us that such an approach will hit a bottleneck when we reach the limits of the serial portion of the workload. As these constraints slow the performance of general-purpose processors, the reliance on custom hardware accelerators to boost performance for specific workloads is growing. Heterogeneous integration at the system level with a combination of CPUs, GPUs, FPGAs and other accelerators can optimize system power and performance. SEMI: What solutions is Intel developing to address these market needs? Radhakrishnan: Intel is actively involved in the development of the industry ecosystem for heterogeneous integration. We have developed a number of innovative advanced packaging solutions such as the EMIB and Foveros that are used in products today. Intel is also developing the next generation of advanced packaging technologies, Foveros Omni and Foveros Direct, which will dramatically scale the IO density by using direct Cu-Cu bonding technology. Foveros Omni is a crucial building block technology to enable high-voltage power conversion on the package for efficient power delivery. Intel is uniquely positioned to predict the design needs for future systems and deploy its resources to develop the technology building blocks needed to continue performance scaling. Our IDM 2.0 strategy enables us to leverage our leadership in packaging technologies to design the best products and use the best IP to deliver leading products across a broad range of categories. SEMI: What do you expect from your participation at SEMI Connecting Heterogeneous Systems Summit? Radhakrishnan: I’m hoping to shed some light on some of the new technologies we have been developing at Intel to enable heterogeneous system integration. I also want to bring awareness to the power-related challenges we are facing with heterogeneous systems. I also look forward to listening to what other industry leaders have to say on the topic. Kaladhar Radhakrishnan is an Intel Fellow and a Power Delivery Architect with the Technology Development group at Intel. He plays a significant role in shaping and driving power delivery technologies for Intel microprocessors. His areas of expertise include integrated voltage regulators, advanced packaging and passives technologies. Kaladhar is a two-time recipient of the Intel Achievement Award, the highest Intel honor an individual or small team can receive. He has authored four book chapters, over 40 technical papers in peer-reviewed journals, and has been awarded 35 U.S. patents. He has also served as an adjunct professor at Arizona State University. Kaladhar joined Intel in 2000 soon after receiving his Ph.D. in Electrical Engineering from the University of Illinois at Urbana-Champaign. Serena Brischetto is senior manager of marketing and communications at SEMI Europe.