Co-Packaged Optics

As artificial intelligence (AI) workloads surge and hyperscale data centers expand, the semiconductor industry is confronting fundamental limits in electrical interconnects. Co-packaged optics (CPO) is emerging as a pivotal architectural shift, bringing optical connectivity closer to compute to deliver the bandwidth, latency, and energy efficiency required for next-generation systems. However, while the strategic value of integrated photonics is widely recognized, the transition from research to scalable manufacturing remains one of the industry’s most pressing challenges.At the heart of this transition are a range of process considerations that, while familiar, are fundamentally different for photonics than for traditional semiconductor manufacturing. In many cases, the underlying requirements mirror those of CMOS manufacturing—cleanliness, uniformity, and defect control—though often at a different scale and level of maturity. However, the introduction of heterogeneous materials, new device structures, and optical performance sensitivities adds layers of complexity that must be addressed to achieve consistent, high-yield production.The expanding role of wet processingWet processing plays a critical role in several key stages of photonic device fabrication, including cleaning, etching, and drying. These steps directly impact surface quality, defectivity, and, ultimately, optical performance.Critical considerations include:Etch uniformity, essential for maintaining consistent optical pathways and minimizing signal loss;Particle control, as even small contaminants can scatter light and degrade performance; and Drying processes, where residues, watermarking, or contact-related defects can impact yield and reliability.Drying, in particular, has emerged as a significant challenge. Techniques such as nitrogen blow-off or chemical vapor drying are being refined to address issues like residual marks or contamination. In some cases, additional process enhancements—such as sonic energy—are being explored to further improve particle removal and surface integrity.Increasingly, tighter control of process chemistries and concentrations is required to minimize residues and improve particle performance. As these requirements tighten, the industry is recognizing that wet processing is not just a supporting step, but a critical determinant of device performance.At the same time, photonics manufacturing introduces variability that is less common in high-volume CMOS environments. Differences in wafer size, material composition, and process flows demand a higher degree of flexibility. In many cases, both batch-style wet benches and single-wafer processing approaches are used, depending on the application. Equipment and processes must often be adapted—through changes in wafer handling, fluid delivery, or process parameters—to accommodate these variations. In some cases, hybrid approaches that combine immersion and spin-based processing are being adopted to support a broader range of process steps within a single workflow.Scaling for yield and manufacturabilityThroughput, while important, is not yet the primary constraint. The industry’s immediate focus is on achieving stable, repeatable processes that support high yield and consistent performance. Over time, as designs mature and volumes increase, throughput expectations will increase significantly, with industry targets moving toward several hundred wafers per hour.Another important consideration is how photonics capabilities are integrated into existing fabrication environments. Contrary to some expectations, this integration does not always require wholesale changes to fab infrastructure. In practice, integration challenges are often less significant than anticipated and are typically addressed through targeted engineering adjustments rather than fundamental infrastructure changes. This approach minimizes disruption while enabling manufacturers to extend their capabilities into new application domains.Yield remains a central concern throughout this transition. As with any emerging technology, variability in early-stage manufacturing can create cost and reliability challenges. Reprocessing is particularly undesirable in photonics, where complex material systems and tight performance requirements make defects difficult and expensive to correct. Achieving high yield, therefore, depends on precise control across all process steps, from chemical concentration management to particle mitigation and surface preparation.At the same time, the cost of ownership must be carefully managed. While photonics manufacturing may not yet demand the extreme throughput of advanced logic production, it must still be economically viable at scale. This creates a dual imperative: to optimize processes for yield and performance while maintaining the flexibility needed to adapt to evolving designs and standards.Sustainability and the path to adoptionSustainability is also becoming an increasingly important dimension of photonics manufacturing. Although optoelectronic technologies can deliver system-level energy efficiency benefits, their fabrication still relies on water, chemicals, and energy-intensive processes. As a result, the industry is beginning to apply lessons learned from CMOS manufacturing to improve environmental performance. This includes exploring alternative chemistries, particularly as regulatory pressures drive the reduction or elimination of substances such as per- and polyfluoroalkyl substances (PFAS), and aligning with established environmental, health, and safety frameworks.More broadly, the evolution of co-packaged optics highlights a familiar pattern in semiconductor innovation: the need to bridge the gap between laboratory breakthroughs and high-volume manufacturing. Standards are still maturing, design approaches continue to evolve, and early implementations may give way to new architectures. In this environment, flexibility and adaptability are critical—not only in device design, but across the manufacturing ecosystem.Demand signals, however, are unmistakable. AI-driven data center growth is accelerating the need for more efficient interconnect technologies, and photonics is widely expected to play a central role in meeting this demand. As more fabs invest in photonics capabilities, the focus will increasingly shift from feasibility to scalability—from demonstrating what is possible to delivering it reliably and cost-effectively.Wet processing, though often viewed as a supporting function, is deeply embedded in this transition. Its influence on cleanliness, uniformity, and defect control makes it a key enabler of photonic device performance and manufacturability. As the industry continues to refine processes and align standards, advances in wet processing will help define how quickly and effectively co-packaged optics moves into the mainstream.For SEMI members navigating this shift, the implications are clear. Success in photonics manufacturing will depend not only on innovation at the device level, but on the ability to translate that innovation into robust, scalable processes. In that effort, the fundamentals—precision, control, and adaptability—remain as important as ever.Dr. Ismail Kashkoush is Chief Technology Officer for JST, based in Meridian, Idaho. With more than 30 years of expertise in the semiconductor industry, he leads JST’s engineering, technology, and product lines teams to develop the next generation of sustainable surface preparation products and processes. Dr. Kashkoush earned his Ph.D. in engineering science from Clarkson University. Prior to joining JST, he served as CTO at Akrion Technologies Inc. He has a large patent portfolio and continues to contribute technical publications and seminars on wafer surface preparation technology for the IC, MEMS, flat panel display, and photovoltaics sectors.

Advanced packaging is no longer operating behind the scenes. The technology of advanced packaging is helping to sustain the speed of the semiconductor industry’s improvement in power and performance, even as the Moore’s Law roadmap for wafer-level scaling comes under strain.At the Advanced Packaging Conference during SEMICON Europa 2025 in Munich, global experts examined the growth trajectory of this critical sector and Europe’s potential to lead in next-generation packaging solutions.Market Momentum Fueled by AI and HPCRomain Fraux, Chief Research Officer at Yole Group, forecasted that global revenues for advanced packaging will grow from $46.1 billion in 2024 to $79.4 billion by 2030. “Everything is linked to AI and high-performance computing (HPC),” said Fraux, while also emphasizing the growing relevance of automotive applications in driving demand.Romain Fraux, Chief Research Officer, Yole GroupThis demand is accelerating innovation across the supply chain. One emerging area is panel-level packaging, which breaks away from traditional round wafers. As Andreas Wocko, Sales Manager at Lam Research, observed, “Since the 1970s, the semiconductor industry has built on wafers. Now we are not just scaling, we are reshaping, building in a square format for the first time” – an innovation which substantially increases area efficiency and reduces device cost. Andreas Wocko, Sales Manager Europe, Lam ResearchTechnology Transformation from Lab to FabEurope is already investing in the foundational technologies that will power tomorrow’s packaging systems. Rolf Aschenbrenner, Deputy Director of Fraunhofer IZM, the home of the European Union’s APECS advanced packaging pilot line, discussed ongoing research into functional interposers, routing density, and organic interposers. “Our goal is to show how a new design philosophy incorporating chiplets can be brought to the industrial systems level,” said Aschenbrenner.Rolf Aschenbrenner, Director Deputy, Fraunhofer IZMThese breakthroughs are essential, as pitch sizes shrink and new materials emerge. Dr. Jessica Stubbe, Global Application Manager at MKS Atotech, described how interconnect densities have doubled in the past two years, with the industry moving to pitch sizes of less than 10µm. Stubbe said this new technology “will be enabled by a move from traditional solder-based interconnects to copper-to-copper hybrid bonding to provide higher density I/Os and lower resistance.” Jessica Stubbe, Global Application Manager, MKS AtotechInnovation Meets Real-World IntegrationThis increased density carries thermal risks with it. As Ram Trichur, Global Head of Semiconductor Packaging at Henkel Corporation, said, “New architectures enabled by advanced packaging are putting power devices on the backside, interposer or substrate, and this addition of more power delivery components in the package creates more local hotspots.”The reduced feature sizes inside the latest packages make it more difficult than ever to apply thermal interface materials. “At Henkel, we are now making 1µm-level fillers which enable the effective filling of gaps as small as 7µm,” said Trichur.Ram Trichur, Global Head of Semiconductor Packaging Market Segment, Henkel CorporationOne of the applications which stands to gain the most from the development of advanced packaging technology is silicon photonics. Dr. Himani Kamineni, Director for Advanced Packaging at GlobalFoundries, described how co-packaged optics (CPO) brings photonics directly inside the package, reducing connection lengths from centimeters down to millimeters, and providing higher bandwidth and lower latency at lower power. “Advanced packaging and CPO are foundational elements for AI and data centers to enable scalability to the next generation of compute,” said Kamineni. “But it will need a lot of packaging innovation: silicon interposers, copper-to-copper interconnects, and fiber-attach units for precise alignment.” Himani Kamineni, Director, Advanced Packaging, GlobalFoundriesReliability and Test Under PressureIn the transition to new packaging technology, it is crucial that the industry does not lose sight of the reliability standards which have made semiconductors so valuable in sectors such as automotive and aerospace. Amar Mavinkurve, Director of Materials and Labs Package Innovation at NXP Semiconductors, warned the finer spacing and smaller feature sizes in the latest packages posed a problem for reliability and long-term performance. He said, “We are dealing now not just with one failure mechanism, but with multiple. So, the way that we are used to describing behavior in models will not necessarily hold in future. Even industry standards might not hold.”Discussing new technologies such as copper-to-copper interconnects, Mavinkurve pointed out that failure would not be due to a single event, but to processes such as electromigration, corrosion, and thermomechanical effects. To model reliability properly in future, he said, “we need to move from a physics of failure to a physics of degradation.” Amar Mavinkurve, Director Materials and Labs Package Innovation, CTO, NXP SemiconductorsFabio Pizza, Business Segment Manager at Advantest Europe focused on quality and failure. With geometry scaling toward 1nm, early identification of known-good dies is essential to optimize cost and test coverage. Pizza said that, while device manufacturers need to keep time-to-market and the cost of test under tight control, they are also trying to figure out how to increase test coverage. “In a modern GPU, even a 100 DPPM quality process leaves 20 million transistors untested,” he said. Fabio Pizza, Business Segment Manager, Advantest EuropeEurope’s Position in the Global EcosystemThe conference concluded with a panel discussion about the prospects for Europe in the global advanced packaging market. According to Yole’s Romain Fraux, there is a strong ecosystem in Europe: “Europe’s strengths include specialized packaging service providers in the photonics and power market segments, as well as many packaging equipment manufacturers,” said Fraux. This resonated with the instincts of NXP’s Amar Mavinkurve and Advantest’s Fabio Pizza. Mavinkurve said: “We should focus on what we are already good at doing. It will be challenging to compete with advanced packaging providers elsewhere for AI and HPC business.”Ram Trichur of Henkel, however, urged the industry in Europe, “Do not take your foot off the gas on advanced packaging. You cannot do the full stack here, but in a technology such as CPO, there is a lot of innovation in Europe, and there is scope to add the manufacturing of these devices on top of the research capabilities.”Chris Scanlan, Senior Vice President of Technology at Besi, raised the idea of shifting production toward Eastern Europe. But Trichur cautioned that talent and infrastructure remain limiting factors in that strategy. From left to right: Chris Scanlan, Senior Vice President Technology, Besi;Amar Mavinkurve, Director Materials and Labs Package Innovation, CTO, NXP Semiconductors; Fabio Pizza, Business Segment Manager, Advantest Europe; Rolf Aschenbrenner, Director Deputy, Fraunhofer IZM; Ram Trichur, Global Head of Semiconductor Packaging Market Segment, Henkel CorporationCollaboration is the Path ForwardSpeakers throughout the conference echoed a common message: advanced packaging is reshaping the semiconductor landscape, and global collaboration will be essential to success. “It is impossible for one country or one region to do the entire stack,” Trichur concluded. “Innovation must be matched with strategic partnerships to bring advanced packaging from research to real-world impact.”On behalf of SEMI, the SEMI Europe team would like to thank the industry leaders whose expertise and enthusiasm made this conference a resounding success. SEMI ContactCassandra Melvin, Senior Director of Business Development and OperationsEmail: [email protected]