electronic design automation

Maheen Hamid is a co-founder of Breker Verification Systems, supplier of functional verification solutions for complex chip design challenges, and serves as its COO and CFO. She is also Co-Chair of the ESD Alliance and member of the SEMI North America Advisory Board (NAAB).Given her background, roles within the industry and interests, it seemed like a good time for me to reach out for her perspective and market analysis. During our discussion, she offered up some great observations, identified trends, pointed to areas in need of attention and ways for the industry to better collaborate. We ended by talking about AI’s role today.Smith: How do you track where the semiconductor industry is going?Hamid: Business and macro strategies have always been interesting to me. In recent years, with the increasing global importance of silicon sovereignty, it is necessary to track the pulse of initiatives across various channels in multiple geographies. Starting with policy discussions at SEMI to media coverage of the semiconductor value chain to EDA specific news, I read voraciously and listen in on disparate discussions. There is no denying that it is impossible to envision the boundaries of where the semiconductor industry could go, particularly in design innovation. Smith: Nonetheless, what trends have you identified?Hamid: Global trade wars are creating as many roadblocks as they are creating opportunities. It is fascinating to watch the incredible innovation led by the U.S. for decades in semiconductor design be challenged as technology and access to technology gets democratized across the board. Maintaining thought leadership is a demanding task and no longer contained to an individual company’s cleverness. Crafting an effort that is coordinated with national interests has become compulsory. Separately, developments in AI are creating a new wave of complex chip designs that are redefining hardware investments. Data centers are becoming as ubiquitous as the personal computers of the ‘80s. While advanced chip designs forge ahead and additional classes of chips such as memory become truly commoditized, the need for efficiency in the full flow from design to manufacturing becomes imperative to protect margins for relevant players.Smith: The need for industry collaboration appears to be a trend that is an essential part of the industry’s evolution. How do you see that developing in chip verification?Hamid: RISC-V has given rise to many new design starts by companies that do not have the legacy verification frameworks owned by the NVIDIAs and Intels of the world. Several of these larger customer companies are investing heavily in their own complex chip designs, creating interesting opportunities for a collaborative approach to enabling internal innovations. As well, this new class of customers is less married to enterprise flows from large EDA companies and prefer to invest in best-of-breed solutions. This is driving necessary collaborations across EDA vendors in chip verification. Driven by mutual customer demand, we have recently modified several of our arrangements with other EDA players.Interestingly, the momentum in the RISC-V ecosystem is also driving new initiatives in the more traditional flows. This is a necessary shake-up in how business needs to be done in an increasingly, globally competitive landscape. Smith: What area do you see that needs more attention?Hamid: It is imperative to keep the business climate conducive for innovation and thought leadership. Policy debates impacting the chip industry are getting more heated and controversial. We need more concerted collaboration among the players in the chip ecosystem to help influence this policy in a way that allows U.S. companies to thrive. We need to promote more opportunities that bring disparate companies together to build clever flows that increase our silicon sovereignty. Smith: AI is playing in the design and design tools area. What about other parts of an organization, such as finance or operations and marketing?Hamid: AI efficiencies can help with predictive analysis for large companies in these core functions such as finance, operations and marketing, but for smaller, nimble companies, the human element still rules. Our strategic marketing, as an example, is defining industry-leading initiatives. AI does not have access to language models to automate any of what we need to invent in communicating new ideas. LLMs do provide a good sounding board though. It’s interesting to “discuss” ideas with ChatGPT and pull templates of successful implementations in unrelated industries that could be a blueprint for how we approach next steps.About Maheen HamidMaheen Hamid is the co-founder CFO and COO at Breker Verification Systems, bringing a wealth of financial engineering experience from investment banking and small business management. Hamid has been instrumental in establishing Breker as an important stakeholder in the EDA industry, running its business side and driving operational growth as it thrives as an established software supplier. She plays an active role in defining the company’s strategic direction, corporate communications and branding. Hamid holds a BBA from North South University and an MBA from the University of Texas at Austin.Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community. 

Electronic Design Automation (EDA) is essential for the entire semiconductor design-to-manufacturing process. EDA tools streamline the design process, speed up development cycles, and ensure higher precision in chip design. Accellera Systems Initiative, an independent standards body, focuses on standards for system-level design, modeling and verification used extensively in the EDA ecosystem. These standards facilitate industry-wide collaboration and accelerate innovation, working closely with many members of the Electronic System Design (ESD) Alliance.Bob Smith, Executive Director of the ESD Alliance, recently talked with Lu Dai, Senior Director of Technical Standards at Qualcomm and Chair of Accellera Systems Initiative about Accellera’s new and future standards, and its successful global Design Verification Conference (DVCon) events.Smith: What’s new in Accellera’s standards effort since we last spoke?Dai: We are working on two new initiatives. The first and biggest initiative is our recently formed Federated Simulation User Group. Our members requested an end-to-end simulation environment or models that can be plugged into a system-level simulation environment. This challenge triggered industry-wide discussions among Qualcomm, NXP and many other semiconductor companies, especially those from Europe tied to auto and avionics industries.The need for this new standard effort is being driven by industries such as automotive where tiny microcontroller chips are traditionally used. The automotive industry has some existing simulation standards that include physical devices. With autonomous vehicles, systems on chips (SoCs) are replacing microcontrollers and handling system-level features that require rigorous system-level simulation. The user group is tasked with reviewing current automotive industry simulators and discovering how our traditional register transfer level (RTL) code- or emulation-based simulations could work with them via an interface.This effort has attracted new companies outside of the traditional EDA world. Ford, for example, is now an Accellera member and has a seat on our board. It’s exciting to see this collaboration.Functional safety is another initiative that we started a few years ago, also driven by the advancements in autonomous vehicles. Accellera’s focus is to define functional safety as a format that can be carried through the design stages from intellectual property (IP) to SoC, and from front-end design to back-end. Across the different stages of design and verification, an engineer can then confirm that the functional safety goal is maintained. We’ve published resources including whitepapers and are currently working on developing the language format. Smith: Where do you see Accellera’s next standards efforts?Dai: We have a mixed-signal standard coming out soon. It adds a mixed-signal interface to the SystemVerilog standard, currently under IEEE management because Accellera donated it to IEEE.A common question we’re asked is, “What are you doing with AI?” Accellera is a heavily EDA-centric standards body, and EDA tools are increasingly incorporating AI. AI consumes and outputs large amounts of data. A challenge is how to ensure the AI work output from one vendor’s EDA tool can propagate to another EDA tool. Accellera may look at defining an AI data format for EDA. It comes with a unique challenge because AI data is highly proprietary, both from the vendor’s and customer’s perspectives, so a robust security solution is needed. We may need to consider an interface standard, because companies may not be willing to share data, even with other groups that are in the same company. among their partners. They might need to hide the data and have a special interface to extract the data that they are willing to share. Accellera could investigate how to make AI deployment cross-vendor while allowing vendors and customers to protect their IP. Another area for potential new standards is around supply chain security challenges. This is a global issue driven in part by the COVID experience and geopolitical concerns. One possible approach is to use tagging. When a chip comes out of the fab, it would have a tag designating where it was designed and manufactured, and where the tooling is from. The tag would also include data about the regions or countries the design traveled through during the entire flow from design to manufacturing. Smith: Is Accellera looking into any standards or addressing any open-source design and verification flows?Lu: Accellera has been in the open-source domain for quite some time. Accellera has a language reference manual, user guides and reference implementations. Because many Accellera standards are related to language, we often work on libraries when a new language comes out and reference implementations to help our community deploy that standard. Reference implementation libraries are open source, as is our SystemC material. We have an active open-source SystemC community.Smith: I hear that the DVCon conferences are expanding globally. What’s driving that?Dai: Engineers enjoy attending conferences in person where they can reconnect with peers, build new connections and foster collaboration. We have regional DVCon events to bring information to our community and make Accellera more accessible to them. We now host several DVCon conferences in North America, Europe and Asia. Our next DVCon will be held in San Jose, Calif., from Feb. 24-27.Smith: How can readers of this blog post get more information about Accellera?Dai: For up-to-date information about Accellera’s activities, please visit our website: https://accellera.org/. Lu Dai is Senior Director of Technical Standards at Qualcomm and is a leader in semiconductor standards and industry organizations including Accellera. Dai holds a Master of Science degree in Electrical Engineering from Cornell, and a Bachelor of Science degree in Electrical Engineering and Computer Science from UC Berkeley.Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community.

Dr. Walden Rhines, former CEO of Mentor Graphics (now Siemens EDA), and current CEO of Cornami, recently joined Dan Nenni of SemiWiki.com for a podcast to discuss the latest Electronic Design Market Data (EDMD) report.