Dolphin Design

SOI News spoke with Philippe Berger, CEO of chip silicon IP design / power management specialist Dolphin Design. Here’s what he told us about the work they’re doing on FD-SOI.SOI News (SN): Dolphin Design has been offering IP solutions for bulk technologies since 1995. What is your specialty, and why are you expanding your offering to FD-SOI? Philippe Berger (PB): Low power is part of Dolphin’s DNA since its inception and we work hand-in-hand with our customers to offer IPs that enable design of Energy Efficient SoCs while allowing our customers to focus their design activity on their core competencies. Technology scaling is no longer the only answer for the next generation of Energy Efficient SoCs. FD-SOI is one of the attractive technologies to address the upcoming energy efficiency challenges of next SoC generations, be it for IoT or automotive among several other applications. FD-SOI offers the opportunity to deal with a complex SoC architecture, made of multiple power domains, including RF, including digital processing with AI, and sensor interfaces, all together with a complete power management on a single chip. [caption id="attachment_33090" align="alignright" width="175"] Philippe Berger, CEO, Dolphin Design.[/caption] This is a great opportunity for Dolphin Design. Adding the deep expertise of our engineers in this technology and our turnkey design platforms, we can really help companies targeting FD-SOI implement easily, quickly and safely an energy-efficient SoC. We have two complementary offerings for companies that want to leverage FD-SOI: A sensor-centric MCU subsystem as a configurable RTL design platform. This design platform, named Chameleon, allows achieving the best energy efficiency by turning the CPU off whenever possible and by eliminating latency and congestions on the memory bus. A power management design platform as a total solution to implement fast and safely a power management network that leverages low power techniques to meet the energy efficiency targets. This design platform, named Spider, combines a library of configurable power management IPs, including adaptive body biasing, with a scalable power controller enabling to control power and clock activity autonomously, even with the CPU off. We can intervene at a very early stage of our customers’ design cycles thanks to our system-level utilities rather than just IP bits and pieces. The figure below describes the components of our Spider power management design platform which is a key turnkey solution to leverage some unique capabilities of FD-SOI, such as the capability to operate at a very low voltage with a decent speed or the capability to support as high as 5V input voltage. ASN: What’s driving that business? PB: The emergence of new IoT and automotive markets is driving the business forcing IC design teams to pursue tough objectives: zero power consumption in off modes while maximizing the performance in active modes at minimal power consumptions. Unfortunately, scaling down to the next technology node makes it even harder to reduce power in off modes and is an expensive choice - too expensive - for many applications to achieve the energy efficiency targets in active modes. As a result, design teams must now pursue their gains by deploying increasingly complex power management techniques to meet the stringent requirements of the new IoT markets. This is particularly tricky in advanced IoT where near-sensor processing must be efficiently combined with RF connectivity, together with advanced power management. In addition, designers must confront the complexity of supporting high input voltage for interfacing with 4.2V/4.4V Li-Ion batteries or 5V USB charging mode that rely on 1.8V IO transistors. The need for solutions that enable to select fast and to implement safely the power management network which allows a seamless system-level integration while meeting power consumption targets in each SoC power mode -- that drives our business. SN: What do you see as the biggest benefits – and challenges – for designers moving to FD-SOI? PB: Its biggest benefit is its high integration capability. One of its key challenge is the ”so-far” relatively more complex design methodology that is required to take advantage of all FD-SOI characteristics, namely for example the biasing of the bulk to either reduce leakage or improve energy efficiency depending on working mode and technology centering. And ultimately, assuming the FD-SOI design flow is no longer a point of discussion, we need to get all designers “Thinking FD-SOI”. By that I mean to be aware of the breadth of FD-SOI advantages, so they are using it at every possible opportunity: in RF, in switches, in A/D converters (ADC) – in everything! FD-SOI’s double gate lets you think about more than decreasing noise and energy consumption. There are many opportunities for many blocks – especially analog. [bctt tweet="We need to get all designers “Thinking FD-SOI” so they’re using it at every possible opportunity: in RF, switches, ADC – in everything! Body biasing is usually thought of in the digital context, but it is also very useful in analog. – DolphinDesign CEO" username="soiconsortium"] SN: What does Dolphin Design offer designers moving to FD-SOI? PB: In order to ease these tasks, we developed the turnkey Spider platform based on power management IPs and system-level utilities. It speeds-up the design of energy efficient power management systems to weeks instead of months. Spider obviously exists in FD-SOI technology. It enables chip-architects to explore many power architectures and to select the best one to match the targeted PPA. It bridges the complexity gaps of designing fast and safely a power controller that can deal with numerous power domains and several operation modes for each domain and that can operate even when the CPU is off. Then, it bridges the gap between standard RTL and GDS flow, as it is able to generate the UPF backbone of the SoC. It offers a standardized and predictable power management flow, securing first silicon success. As an example, one of our key customers doing a ULP MCU shared that they have been able to design a complete power controller in less than one week instead of a couple of months. SN: You announced design kits with Adaptive Body Bias (ABB) solutions for GlobalFoundries’ 22FDX technology at the end of 2019. What challenges is that solving? PB: In the race for higher energy efficiency, digital designers face the impact of process variations. Chip designers have added margins all along their design to ensure the future chip will work fine whatever the technology centering after fabrication. Performance or size tradeoffs are necessary to cope with extreme variation cases (the so-called “corners”). At low voltage, SoC designers often use compensation techniques to limit the impact on the SoC energy efficiency. Through the control of transistor threshold voltage in FD-SOI technology, body biasing acts as a fantastic and automated control method to offset all variations. Designers can design their SoCs with reduced design corners for process, temperature and aging, boosting the PPA trade-off up to 10x at low voltage. We have been cooperating with GlobalFoundries over the last two years to provide the market with an Adaptive Body Bias (ABB) IP solution. The ABB feature allows designers to leverage forward and reverse body bias techniques to dynamically compensate for process, supply voltage, temperature (PVT) variations and aging effects. Our ABB IP embeds the body bias voltage regulation, PVT monitors and aging sensors, and a control loop. From standard-cell library to sign-off verification, our customers will continue to use their usual standard flow. For IoT on GF 22FDX, the design kits are available for production. For automotive, it will be in the next months. SN: Looking to the future, will there be a need for more application-specific FD-SOI IP? Where are the growth opportunities? Which ones will you be working on? PB: We anticipate new needs along the time as new applications will emerge in FD-SOI. We have a roadmap to enrich the catalog of power management IPs for addressing each market vertical with the most complete offering. But where we see the biggest growth for us is the growing adoption of power management IPs even by companies that were used to make voltage regulators on their own. Power management is no longer an issue of designing some good voltage regulators, like LDOs. Fabless companies face the challenge of dealing with the growing complexity of SoC power management network. It absorbs a significant portion of their design “energy”, in logic and in analog domains. They need to customize voltage regulators for each SoC and to maintain their design to keep them competitive. They also face the challenge of complex and sensitive power controller design. Finding the right design expertise to make such complex SoCs is a challenge in itself and in many cases power management complexity is the cause of a design respin. With the emergence of solutions such as Spider, that streamline and secure the selection and the implementation of the power management network, fabless companies start to question whether their core competency is power management IP design or if they can focus their design resources where they are the best at. The addition of body biasing into this picture makes it even more obvious for fabless companies that relying on a solid IP partner is a strong option. For Dolphin Design another opportunity for growth will mainly come from our capability to expand our offering for complementary design platforms for various FD flavors. We will communicate a lot in the coming months on our design platforms. We are also looking for diversification to other SoC functionalities. Processing is definitely an area in which we are significantly investing (MCU sub-systems and their associated DSPs), but energy harvesting and RF could also be good candidates in the future. SN: Dolphin Design is a member of the SOI Consortium. What do you see as the advantages of membership? PB: The 2019 Silicon Valley SOI Symposium was my first participation in an SOI Consortium event. [Note: you can get his full presentation here.] My first impression was good! I was positively surprised by the wide diversity of material shown. But really the key advantage was the opportunity to meet with so many different companies, all involved, from near or from far, with an FD-SOI tape out. It really helped me understand what I needed to put my teams to work on next!

Here is our second post about the SOI Consortium’s Japan Symposium this past fall. This will provide summaries of eight very informative presentations on SOI in IoT and automotive by NXP, Dolphin Design, Leti, Silvaco, Arm, I-fuse and Secure-IC. There’s a lot of content to summarize, so this post is about twice as long as those we usually do. But you’ll want to read right to the end, for sure! In case you missed our previous post on the 5G/RF-SOI presentations given at the Japan event, you can read it here. Our next and final post on the Japan event will cover photonics presentations by Cisco/Luxtera, TowerJazz, GlobalFoundries, Leti, Cadence and Soitec. By way of reminder, the Japan SOI Symposium was a great success, with both days well attended. If your company is a member of the SOI Consortium, you can now access most of these presentations on our website. You can also click on the illustrations in this post to see them in enlarged versions. [caption id="attachment_28106" align="alignleft" width="366"] (Courtesy: NXP SOI Consortium)[/caption] The IoT World Enabled Through SOI - Jon Cheek, NXP Sr. Director, Front-End Innovation For NXP, FD-SOI introduced the ability to easily add different functionalities to the technology node like ULP, eNVM, support for high-voltage and embedding RF. For them, said Cheek, it’s about the range, and with adaptive back bias, you can “get crazy”, so you can really achieve amazing things. In fact, they think they now have the lowest leakage SRAM in the industry, thanks to body biasing. The i.MX 7ULP is finding significant success in wearables. Their “crossover” chips are the latest beneficiaries of FD-SOI with body biasing. The “new normal”, they offer huge improvements for real-time operating systems – which is of course key for edge computing. (As you can imagine, the audience was intently taking notes throughout -- this was a really excellent talk!) It also is great for machine learning, as it is designed to unlock the potential of voice-assisted end nodes. The IP they needed is now available from multiple vendors, noted Cheek, such as Tensilica and VeriSilicon. Another key play will be in visuals for industrial computing. He concluded by observing that the automobile is the ultimate IoT machine, with 10x the amount of code now found in leading edge airplanes. That’s where the i.MX8 and 8X come in. [caption id="attachment_28104" align="alignright" width="323"] (Courtesy: NXP SOI Consortium)[/caption] High-Voltage SOI – Enabling Automotive- NXP Jon Cheek gave this presentation on the second day of the Japan event. Long-time followers of SOI will know that NXP has been excelling in high-voltage (HV) SOI for well over two decades now (including the pioneering work done by Philips, now part of NXP: their EZ-HV SOI patent dates back to 1993). It’s probably safe to say that NXP's SOI-based automotive chips are used by virtually every carmaker on the planet. HV follows well behind the leading edge – it’s currently mostly around 130nm (the limits are related to metalization). Reason #1 it’s on SOI? SOI-based technologies are incredibly reliable, especially in the automotive culture targeting the three zeros (0 emissions, 0 accidents and 0 time wasted). Today’s car manufacturer’s are going to a distributed environment, and SOI still provides a huge advantage, making parts that are smaller, lower power and more reliable – so it drives a lower BOM for automakers.In conclusion, said Cheek, NXP’s leadership through SOI innovation enables scalable solutions, high voltage analog integration, sensor integration, and reliable safe passenger experience. [caption id="attachment_28101" align="alignleft" width="432"] (Courtesy: Dolphin Design SOI Consortium)[/caption] Improving SoC Energy-Efficiency with Dolphin Design Platforms – Nicolaus Gaude, BizDev Product Marketing, Dolphin Design Dolphin has a series of platforms, techniques and IP for increasing speed and drastically improving energy efficiency in SoC design. Gaude introduced their Speed Platforms, which include a Power Management Platform and a Processing platform, both of which make dramatic improvements in energy efficiency. The Power Management Platform keeps control of power management from architecture to design, resulting in a 10x improvement in energy efficiency. The Processing Platform comprises configurable RTL clusters for best-in-class (100x) energy-efficiency. Gaude then turned to the Dolphin’s Adaptive-Body Bias (ABB) IP for breakthrough energy-efficiency with FD-SOI. This is real-time, “on-the-fly” body biasing: the IP does it all. It is silicon-proven on GlobalFoundries’ 22FDX with Arm cores and Invecus standards cells SRAM, with breakthrough energy efficiency. [caption id="attachment_28108" align="alignright" width="363"] (Courtesy: Silvaco SOI Consortium)[/caption] Platform Infrastructure for SOI-IP Ecosystem – Thomas Blaesi, VP of Global Marketing, Silvaco The massive use of IP is both an advantage and a challenge, began Blaesi. There are solutions out there, but they are disconnected. Typically SoC/IP designers, IP librarians and support folks use various systems, while procurement, finance and legal use others. This is a problem for both the providers and the consumers of IP. Silvaco has a new system called Xena that centrally organizes all IP data: it’s an IP repository for tracking accounts, products, contracts, devices, support, compliance and reporting. One of the first beneficiaries of Xena will be the SOI ecosystem, as providers of SOI IP are already signing on. Beyond the organizational advantages, Xena has patented “finger printing” and “DNA analysis”, so there is a digital representation of each IP on an SoC that can’t be reverse engineered. Each fingerprint contains list of unique signatures of each file in an IP or SoC. A file’s unique signature is created from the entire file content, and that signature is guaranteed to be unique to that content. It enhances support for all versions of common design files: hard IP, soft IP, and embedded software. Because it’s cloud or enterprise based, it will be particularly useful for large organizations. Fingerprinting and DNA analysis are vendor agnostic, universal, and easy-to-use tools and methodologies for IP lifecycle management, he concluded. [caption id="attachment_28103" align="alignleft" width="463"] (Courtesy: Leti SOI Consortium)[/caption] Ultra-low power, FD-SOI based IP, in the space of IoT, Health Care, Smart Connectivity 5G – Michael Tchagaspanian, EVP Industrial Partnerships, CEA-Leti This presentation began with a review of the explosion in devices with IoT and related investments, then connected all the ways in which innovations powerhouse Leti is contributing – from the SOI wafer level to the chip level – which is to say practically everywhere! Especially hot topics in FD-SOI included: the roadmap to sub-10nm; CoolCube monolithic 3D; new embedded memories; power amplifiers; Ultra-Wide Range DSP; smart sensing local processing (including haptics, imaging, infrared advanced processing); local processing with edge AI; and spike coding for deep neural networks. He showed information on two always-on/on-demand transmission 28nm FD-SOI IoT test chips that taped out in mid-2019: the Warrior and the Samurai. And finally, he covered silicon-proven IP that Leti has for FD-SOI including power management blocks, lots of RF IP (including low-power RF wake-up), sensor interfaces, clockless network-on-chip and new SRAM technologies. These and more will be covered at the next Leti Innovation Days in Grenoble (June 2020) – during which in parallel, btw, there will also be a European SOI Summit hosted by the SOI Consortium. [caption id="attachment_28099" align="alignright" width="475"] (Courtesy: Arm SOI Consortium)[/caption] FDSOI Enablement for a Total Compute Future – Manuj Rahor, Director Emerging Technologies Product Marketing, Arm Subtitled A perspective on system optimization with Arm FDSOI IP, this presentation reviewed how Arm is enabling system gains through optimization across IP boundaries. This is work happening in the Arm Artisan Physical Design Group (PDG), which provides logic, memory and POP (processor optimization package) IP as well as various products to help ease implementation challenges for advanced nodes. In this case the focus is on Total Compute enablers on Samsung 28nm FD-SOI (called 28FDS) – specifically three building blocks recently launched on FD-SOI. The first is the 128Mb Wide Capacity embedded MRAM (an eNVM to replace eFlash) compiler for storage delivered to Samsung in July `19. It was demonstrated in silicon in the Musca-S1 Smart IoT Device Demonstrator on 28FDS, an energy efficient IoT device with eMRAM secure boot on-chip storage. [Read our coverage from March 2019 here.] The second is a novel design developed with Spin Memory. It recently taped out on 28FDS and is slated for delivery in 2020. Adding an “Endurance Engine to the eMRAM that was delivered in 2019, the ARM-Spin innovation delivers RAM-like performance with increased speed and endurance. What’s at issue here is a change in use cases. Use cases served by eFlash were not written to that often; now with sensors (as in IoT) that continually gather and write data, eFlash endurance is not sufficient. The third is billed as an SRAM replacement compiler. Its MRAM as RAM in A-class systems, with significant energy and performance gains. Again, this is a use-case issue: retention is lower (this is for weeks months, whereas the other solutions are for 10 years). But you can get more RAM than SRAM into the same footprint, so you get a 60% reduction in DRAM traffic and increased performance. Delivery for this is marked as 2020+. [caption id="attachment_28100" align="alignleft" width="294"] (Courtesy: Attopsemi SOI Consortium)[/caption] I-fuse™: A Disruptive OTP Technology – Dr. Shine Chung, Chairman, Attopsemi I-fuse is a disruptive OTP (One-Time Programmable) technology without disrupting a fuse. The goal was a 100x increase in reliability at 1/100th of the cell size and 1/10th the power. It has now been demonstrated in GlobalFoundries’ 22FDX FD-SOI technology for energy harvesting applications. In the OTP IP technologies, explained Dr. Chung, they defied the conventional wisdom of breaking a fuse to maintain a permanent programmed state forever: Attopsemi’s I-fuse™ is actually a “non-breaking” fuse. “I don’t mind to break a fuse, but I do care about breaking a fuse by explosion”, said Dr. Chung. “The I-V curve of programming a fuse beyond the break point actually shows more like an explosion. The anti-fuse OTP also ruptures gate oxide by explosion. On the contrary, I-fuse™ is a disruptive OTP technology without disrupting a fuse.” He concluded, “By using MOS as switches to enable discharging two capacitors, through cell and reference cell respectively, and compare the discharge rates, the resistance in the cell can be determined higher or lower than the reference resistance so as to convert into logic data. The read energy consumed is only 1/100 of the conventional sensing, which is good for energy harvest IoT applications. Eventually most IoT devices will be battery-less.” [caption id="attachment_28107" align="alignright" width="398"] (Courtesy: Secure-IC SOI Consortium)[/caption] AIoT Embedded Security Using FD-SOI – Yan-Taro Clochard, Japan Sales Director, Secure-IC In addition to opportunities, the impact of AI on IoT (aka AIoT) adds new threats to edge devices. Design for security and in-depth security is required, down to the physical layer. For example in automotive, sensors gather data and AI analyzes it – but the enabler is security. The challenge of AI is the increase in data and connectivity with unsecured devices. FD-SOI is a key for Secure-IC’s Securyzer security module: it leveragesFD-SOI properties to secure the AIoT world. It is flexible, and tuned for each customer. Here, FD-SOI enables the creation of physically secure systems, with secure boot and firmware updates, cryptographic services, key management and secure storage.