downloadGroupGroupnoun_press release_995423_000000 copyGroupnoun_Feed_96767_000000Group 19noun_pictures_1817522_000000Member company iconResource item iconStore item iconGroup 19Group 19noun_Photo_2085192_000000 Copynoun_presentation_2096081_000000Group 19Group Copy 7noun_webinar_692730_000000Path
Skip to main content
Default Banner Image

DAC

Electronic Design Automation (EDA) financial analyst Jay Vleeschhouwer, Managing Director of Software Research at Griffin Securities, carefully tracks the design portion of the semiconductor industry and offers insightful analysis used by this community. He also presents the State of EDA, a yearly report on EDA, during the Design Automation Conference (DAC). After this year’s presentation, he and I talked about trends, the difference between EDA and Architecture, Engineering, and Construction (AEC), security and chiplets. A condensed version of our talk follows. Smith: Now that the Synopsys-Ansys merger closed, what changes? Vleeschhouwer: Synopsys is now the largest company by revenue and backlog in all of Engineering Software, a well over $30-billion industry, including all the parts of that market—AEC, EDA and Technical Software. The pro-forma backlog, about $9.84 billion as of the most recently reported quarter, is the largest in the industry. An important question is how will Synopsys integrate, employ and leverage the four-fifths of Ansys that is not strictly EDA? That is, other than Ansoft and Apache, the two entities that mostly comprise Ansys' EDA, and that ties into the convergence theme. Also, the question in any acquisition is the balance between leaving the operations and the portfolios as they were, or not. In other words, let them continue doing what they were doing if they were doing it well or quickly absorbing, integrating and leveraging those portfolios into the buyer's portfolio. That roadmap is something that we would be interested in hearing more about in terms of its purely EDA aspects and as well the convergence aspects.Smith: Have you observed any new trends in 2025 that surprised you? Vleeschhouwer: The short answer is that it's more of the same in terms of the main technical and business trends. Of course, the most recent important exogenous effect is the advent of tariffs and new export restrictions, or the variability around export restrictions. That's perhaps the main thing that's occurred in the last few weeks and months. We're seeing a continuation of trends that have been in place for a number of years in terms of many of the technical and business results that we've highlighted in our reports. From industry data, there continues to be multiple EDA categories that are continuing to grow. It’s observable and important that we see this breadth of product adoption and growth across multiple categories. This has been beneficial to each of the four largest EDA companies. There have been compelling technical reasons for this, and I would expect it to remain the case. In terms of those significant multi-year trends, the answer would be no. Otherwise, in terms of 2025 specifically, the thing that was interesting about this year’s DAC was the presence of more startups, something that we've not seen in EDA for a long time. It's interesting that we are seeing startup activity not only in EDA, but even in one of the other areas of Engineering Software that we cover: AEC has little to do with semiconductors and electronic systems and it too has more startup activity than we've seen for about a quarter of a century. Although the rationales for the startups in these two different areas of Engineering Software are quite different. The rationale for the EDA startups is one set of rationales, whereas in the case of AEC, it's different, which to me is analytically interesting. Smith: What is the difference between the rationales for startup activity in EDA and AEC? Vleeschhouwer: AEC has to do with the design and construction of commercial buildings, residential buildings, infrastructure, meaning roads, bridges, airports, tunnels, civil engineering, public works. Among the companies that we follow in those markets are Autodesk and Bentley Systems. Autodesk has a small connection to EDA because one of their mechanical CAD products has some integration with some PCB design tools. In any case, the rationale for startups in AEC that we've seen has mostly to do with what has been some vocal dissatisfaction with the incumbent or large incumbent products. That's different from EDA, where we can’t make a case that there is dissatisfaction or sufficient dissatisfaction with the incumbent tools that would necessitate, or be a catalyst, for startups. What we're seeing here is the ongoing, complex, rapid evolution of semiconductor design and electronic systems design because of the unusual breadth of EDA tools and functions, far more so than in AEC. There's much more opportunity for niche products to perhaps complement existing tools. As you know, it can be difficult to dislodge an existing tool in EDA. The industry has become consolidated among the big four—Ansys, Cadence, Siemens EDA and Synopsys—and now three with Synopsys/Ansys merger. Backlogs have continued to grow and book-to-bill has been positive for 15 years. It’s hard to infer any dissatisfaction with incumbent tools or insufficient satisfaction showing up in the numbers. Whereas in AEC, it's different in terms of the profile of the customers or the way the tools are used. There are far more customers than in EDA—thousands upon thousands of architectural firms and construction firms and so forth. The installed base of the AEC software is an order of magnitude more than in EDA. It just so happens that there was one tool from Autodesk that has been getting considerable attention from customers in terms of how modern it is and so forth. This created an opening for some startups. Notwithstanding the nominal dissatisfaction with this tool, however, that particular brand continues to grow. It has the largest base in the industry. At the end of the day, the largest product of its kind in the market continues to grow at a decent rate. The vendor in this case, Autodesk, has acknowledged some of the things needed to do to improve the tool, and it's investing toward that. In any case, there are differences in why these startups exist, how they're approaching the market.Smith: The big topics now are 2D and 3D and chiplets. Where is the market relative to chiplet-based design? Vleeschhouwer: It’s still early, based on commentary from the EDA vendors, about developing and delivering the tools. I don't have a precise measure as to how much of the business is attributable to it. It’s still something that has a considerable runway, which is a good thing. As more tools that can enable it come together, then we'll continue to see this cycle of enablement and delivery. That phenomenon will continue to grow. We would love to hear the vendors’ provide more precise attribution in terms of how much of the business is coming from this. For investors, it will be incumbent upon the vendors to be more explicit about the contribution from the new technical phenomena because it is a new growth catalyst. Smith: The ESD Alliance is starting to see more interest in securing the design flow. This is a huge issue. The design flow is more complex and it's going to require cooperation, collaboration and new standards. Vleeschhouwer: Yes. Siemens EDA is the largest in classical product lifecycle management (PLM) or managing the whole process, an important issue for the industrial and manufacturing markets with its Teamcenter product. Interestingly, Siemens EDA still has work to do to integrate Teamcenter with Calibre, which would seem to have been a natural thing to have done, and I think still is. Teamcenter and Calibre are the two billion-dollar brands that Siemens Industry Software has as an entity. Calibre is by far the predominant product of its kind for semiconductor manufacturing. It's got at least two-thirds market share. Teamcenter is the market leader in classical PLM. The connection between those two brands, owned by the same company, would be an interesting executable to observe.About Jay Vleeschhouwer  Jay Vleeschhouwer, Managing Director of Software Research at Griffin Securities, has more than 40 years of research analyst experience in the technology sector, including software, semiconductors and computer hardware. Vleeschhouwer does a yearly presentation on the State of EDA during the Design Automation Conference (DAC). The slides can be found at: DAC presentation (June 2025) 2.pdf Note: The ESD Alliance will host a three-hour design track “The Convergence of Semiconductor Manufacturing and Design” Tuesday, October 7, from 1 p.m. until 4 p.m. during SEMICON West in Phoenix, Ariz. Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community. 
Read More
That FD-SOI can be a key to achieving near-threshold voltage design was an important point made during a #55 DAC expert panel. Entitled How Close to Threshold-Voltage Design Can We Go Without Getting our Fingers Burnt? the session was organized by Jan Willis of Calibre Consulting. Turnout was excellent. Btw, Jan (herself an EDA expert) was one of the original advisors in the formation of the SOI Consortium, and while this DAC panel was not meant to be about FD-SOI, it turned out be a focal point. Near-threshold voltage design* is an especially hot topic for IoT and edge-computing designers, for whom balancing performance, reliability and extremely low power is generally challenge #1. For them, the ability to get chips working at very low voltages translates into battery life savings. The original goal of the panel was “...to explore how far below nominal voltage we can design, in what applications it makes sense and in what ways it will cost us.” The description in the #55 DAC program noted that “Energy consumption is the driving design parameter for many systems that must meet 'always-on' market requirements and in IoT in general. For decades, the semiconductor industry has attempted to leverage the essential principle that lowering voltage is the quickest, biggest way to reduce energy for a SoC. Some today contend sub-threshold voltage design is viable while others argue for near-threshold voltage design as the minimum.” (Update 2 August 2018: a complete video of this panel is now available on YouTube -- click here to view it.) [caption id="attachment_12035" align="alignnone" width="958"] #55 DAC Expert Panel: How Close to Threshold-Voltage Design Can We Go Without Getting our Fingers Burnt? Left to right: Brian Fuller, Arm (moderator); Scott Hanson, Ambiq Micro; Lauri Koskinen, Minima Processor; Mahbub Rashed, GlobalFoundries; Paul Wells, sureCore. (Organized by Jan Willis of Calibre Consulting)[/caption] The panelists included: Scott Hanson - Ambiq Micro Mahbub Rashed - GLOBALFOUNDRIES Lauri Koskinen - Minima Processor Paul Wells - sureCore Ltd., Sheffield Brian Fuller of Arm served as moderator. [caption id="attachment_12033" align="alignright" width="200"] Panel organizer Jan Willis, Calibre Consulting[/caption] Following the panel Jan published the following excellent recap on LinkedIn. She graciously agreed for it to be reprinted here in ASN, for which we thank her. So without further ado, read on! #55DAC Expert Panel on Near-Threshold Voltage Sees Growing Opportunity Despite ChallengesFirst published on LinkedIn, June 27, 2018 by Jan Willis, Strategic Partnerships Marketing Executive Brian Fuller, Arm, skillfully guided a group of experts through the challenges of near-threshold design to conclude that the adoption is going to start gathering pace in a panel session at the 55th DAC in San Francisco on Monday, June 25. Scott Hanson, CTO of Ambiq Micro, led off by saying the list of what's not challenging is a much shorter list but that by taking an adaptive approach, they have been successful. It's required innovating throughout the design process including test where Scott said they had create their own "secret sauce" to make it work. Later on in the panel, Scott described designers in near-threshold as "picojoule fanatics" to overcome the limitations in design tools which are geared towards achieving performance goals. Lauri Koskinen, CTO of Minima Processor, agreed that adaptivity is key. Minima says it has to be done in situ in the design to make it robust for manufacturing while useful across more than one design. Later in the panel, Lauri indicated that FD-SOI is like having another knob available for optimizing energy in the Minima approach to near-threshold design. Mahbub Rashed, head of Design and Technology Co-Optimization at GlobalFoundries, highlighted the need for more collaboration between EDA, IP, and foundries to support near-threshold design but noted a lot of progress has been made on FD-SOI processes. Mahbub cited models down to 0.4V for FD-SOI processes are available now and GlobalFoundries is able to guarantee yield. Paul Wells, CEO of sureCore, validated that sureCore has bench marked their memories on GlobalFoundries FD-SOI with success. He reflected that FD-SOI has rapidly established itself as cost effective for a number of emerging markets. The panel all agreed that achieving quality on the memory at near-threshold voltage was much tougher than for digital IP. [Editor's note: sureCore's CTO wrote an excellent summary of their SRAM IP for FD-SOI in ASN back in 2016 – you can still read it here.] Paul went on to summarize at the end of the panel that near-threshold voltage is the way of the future and that it's gathering pace. Mahbub called upon the EDA community to step up to improve the tools for low energy design. Lauri and Scott both summarized that there were drivers emerging that will grow the addressable market for near-threshold voltage design. Lauri pointed to growth coming from the applications that require edge computing which he thinks will require near-threshold voltage design. Scott concluded the panel by pointing out that there's been a tremendous increase in performance of near-threshold voltage designs which will increase the addressable available market in the future. ~ ~ ~ This piece was first published by Jan Willis on LinkedIn, June 27, 2018. Here is the original. * As explained by Rich Collins of Synopsys in the TechDesign Forum: "Operating at near-threshold or sub-threshold voltages reduces static and dynamic power consumption, at the cost of design complexity. [...] A transistor’s threshold voltage (Vth) is the voltage at which the transistor turns on. Most transistor circuits use a supply voltage substantially greater than the threshold voltage, so that the point at which the transistors turn on is not affected by supply variations or noise. [...] In sub-threshold operation, the supply voltage is well below the Vth of the transistors. In this region, the transistors are partially On, but are never fully turned. Near-threshold operation happens between the sub-threshold region and the transistor threshold voltage Vth, or around 400 – 700mV for today’s processes.
Read More