Photonics

Let’s celebrate! As of April/May 2020, Advanced Substrate News – or ASN for short, and now aka the SOI Consortium newsletter – has been bringing you news for 15 years. I hope you’ll forgive me if this post has a personal angle, as I have been the Editor-in-Chief since Day 1 back in 2005. One of the things I’ve learned over my career covering technology in general and SOI in particular is that “new” technologies are never really new. They don’t pop out fully formed like Venus Boticelli-style. They take years – decades, even. SOI is no exception. What is exceptional about SOI imho is that the ecosystem – from the substrate providers to the end-product designers – keeps finding new things to do with it. There have always been naysayers – and for a while it took on an quasi-fanatic ferocity. There were those who quipped that SOI was the technology of the future...and always would be. But as it turns out, SOI’s is, has been and will be the right technology at many right moments, and I don’t see any sign of that changing in the years to come. We Need a Newsletter! [caption id="attachment_32012" align="alignright" width="189"] My Design News piece on SOI from June 2000 - it changed my life![/caption] As so much in the SOI story, ASN began with Soitec. I first encountered Soitec when I was working as Contributing Editor in Europe for Semiconductor International in the mid 1990’s. It was a start-up of just a few people that made silicon-on-insulator aka SOI wafers. Most of us at the time had barely a notion of what that was all about, but they had an intriguing story to tell about higher performance and lower power. It so happened a few years later (circa 2000) I was also writing for another publication called Design News – not about chip design, but product design, for folks designing cars and consumer electronics and washing machines and such. I kept hearing a new requirement added to the product-design mantra of faster-smaller-cheaper: lower power. It seemed to me that these SOI wafers could go a long way in solving some of product designers’ challenges. I pitched a story to my editor and it wound up on the cover (those were the days some might remember when trade magazines were on paper…). The big players were IBM for digital (in a current-events aside, DKY that those big iron machines at the US national labs cranking on the solutions for the current pandemic use IBM FinFET-on-SOI chips? Just saying…), Philips (now NXP) for power/analog, and Soitec for wafers – and of course Honeywell for aerospace and the big electronics players in Japan for all sorts of things automotive and ultra-low power. Top management at Soitec read the piece and saw that I “got it”. They brought me on board as a consultant, writing early websites, PR, brochures and such. But also most importantly, they invited me “in” – I sat in on sales reviews and attended the big shin-digs they sponsored on the Riviera and in the Alps. The people I met there – and stayed in touch with – were many of the ones that drive the industry today. (Of course, that was then, this is now: I don’t have that insider status any more, but I’ve kept in touch with and often still rely on the expert advice of people I met during that heady time.) Anyway, one day at the end of 2004, the Soitec folks said to me, “We need a newsletter.” They asked me to come up with a concept they could pitch to the Board. Since Soitec was also doing GaN SiC at the time, I thought it should be called Advanced Substrate News – ASN for short. And we agreed it should involve the entire ecosystem: end users, equipment manufacturers, academics, suppliers of all sorts, and especially: chip designers. But it was not an easy pitch. Who’d want to read about SOI wafers, they asked? Wouldn't we run out of things to say after two or at most three editions? But the idea was a solid one: ASN could be a bully pulpit for the nascent SOI ecosystem. Happily it won the day. I was named Editor-in-Chief, and have held that title ever since. Our very first edition (we were a print quarterly then) had about a dozen articles on SOI, including automotive with Philips, ultra-low power FD-SOI with Oki for Casio’s G-Shock watches (oh yes – it goes back a long ways!), low-power (by a company that Arm then bought), high-performance, high-resistivity SOI wafers for RF…it was all there. And if you look at what we cover now, it’s still all there – albeit better than ever and growing fast. (I just listened to the most recent Soitec Q4'20 quarterly financial report audiocast – announcing that they’d just had their best quarter ever – largely driven by RF-SOI.) We Need a Consortium! In 2007, the SOI Consortium was created with 19 members (a dozen of whom are still members today). As ASN Editor-in-Chief, I was honored to be part of that effort, participating in the meetings where we hashed out what it was all about and what a consortium would do. It was a great opportunity to meet the movers and shakers across the industry, many of whom I’m still in touch with. We published steadily, as the years, technologies and applications came and some went, but ASN readership continued to grow worldwide. Then in 2015, I got an email from the head of the Shanghai Academy of Sciences, which had recently spun off an SOI wafer maker called Simgui. He was (and is!) an ASN reader (though now he’s China’s Vice-Minister of Science Technology). Would I come to Shanghai and present some of the SOI-based applications ASN had been covering to his team there? They’d been working on SOI in parallel for many years, and were interested in where it was going in Europe and America. That was exciting! My first trip (of many, now) to China, it coincided with Semicon China 2015 and the announcement of the “Big Fund”. It was hall upon massive hall of stands immense and tiny, and the level of excitement was nothing short of amazing. (I was one of the only Western journalists there, and essentially broke the story in a piece I wrote for Consortium member Applied Materials’ customer magazine). That trip opened a lot of doors for me and ASN. As the SOI Consortium teamed up to with partners in China to host symposia there, we devoted more and more extensive coverage in ASN to those exciting events. [caption id="attachment_32041" align="alignright" width="328"] Here's some of our core players at the SOI Consortium: Executive Co-Directors Carlos Mazure (also of Soitec) and Jon Cheek (also of NXP) on the far left and right, respectively, Event Manager Iris Rith in the middle, me (Adele Hars) next on the right. We're joined here by Lucy Dai (2nd from left) of Simgui.[/caption] Eventually in 2016, ASN moved under the aegis of the SOI Consortium. We’re quite a jolly band that I have the privilege of working with. Granted at the time of this writing, the world is a difficult place, with so much uncertainty. But there are exciting times ahead with new products and technologies enabled by SOI, and you can be sure we’ll be covering them. RF-SOI will continue its juggernaut path in 5G mmWave. FD-SOI is steadily defining the new mainstream at the edge. The huge amounts of data the world is generating is driving photonics (which is all about SOI) to new heights. SOI for power (meaning high-voltage – think smart power) and imagers continues to grow. [caption id="attachment_32045" align="alignleft" width="99"] That's me - Adele Hars, ASN Editor-in-Chief - at the SOI Consortium's 2019 FD-SOI Symposium. (Photo courtesy VeriSilicon)[/caption] I’m honored to have brought you ASN for the last 15 years. Our archives are truly a treasure trove, and our mailing list of over 2500 really is an industry who's who. We’ve published well over a thousand (!) pieces in that time, most of which I’ve written with guidance from many an expert. However, we of course encourage our readers to pitch stories and/or submit SOI articles for publication consideration - so please, don't hesitate! I want to thank you all for your interest and your continued support. And thank you especially to all the SOI experts out there who so generously – and so patiently – share their time and enthusiasm with me and our readers. Stay safe! With warm regards, - Adele P.S. If you're not already on our emailing list and would like to join, just fill in the form at the bottom of this page. Thanks!

It should really be called SOI photonics – not just silicon photonics, quipped Soitec CTO Christophe Maleville at the SOI Consortium Japan event last fall. You’ve got to have SOI for the waveguides. There are megatrends driving significant growth in photonics – and they were all covered at the event. This is the final post in our coverage of the SOI Consortium’s Japan event (thank you for your patience!). It covers the photonics-related presentations by Soitec, Leti, Cisco/Luxtera, GlobalFoundries, Cadence and TowerJazz. Most of these presentations are now posted on the SOI Consortium website – you can access them if your organization is a member of the consortium. By way of reminder, the Japan SOI Symposium was a great success, with both days well attended. In case you missed our previous posts about the event, you’ll want to go back and read them, too. The first post covered the 5G/RF-SOI presentations by ST, Toshiba, Incize, GF, Silvaco and Sitri – you can read it here. The second post on the event covered eight very informative presentations on SOI in IoT and automotive by NXP, Dolphin Design, Leti, Silvaco, Arm, I-fuse and Secure-IC – you can read that here. Note that you can click on any of the illustrations to see enlarged versions. And now without further ado, here are the summaries of the photonics presentations. SOI Enabling Photonics – Ecosystem and Market Outlook – by Aziz Alami-Idrissi, GM Specialty SOI, Soitec. [caption id="attachment_28773" align="alignleft" width="233"] (Courtesy: Soitec SOI Consortium)[/caption] The megatrends in SOI photonics are: 5G (for more bandwidth, HPC, edge quantum computing), data centers (for high data rate transceivers and high-switch bandwidth), sensors (lidar, gas/chemical and gyroscopes) and biosensors (especially for medical). These are driving big changes: the 44% CAGR means the market is growing from a current TAM of about 500M$ to over 4B$ in 2025. One thing that’s really interesting is the expansion of the photonics market into these new fields in the next few years. While in 2019 90% of the photonics market served data center applications (the other 10% is for long haul), in 2025 optical I/O’s will account for over a third of the photonics market TAM. The other applications making an impact include AI, quantum, lidar (which will move into high-volume manufacturing in 2024) and medical sensors (hitting high-volume in 2023). For its part, Soitec is strengthening its portfolio with 8” and 12” large product coverage, new product sampling engaged, and extended features including newer engineered layers and RF immunity. Advanced Silicon Photonic Solutions Leverage SOI Technology – Eleonore Hardy, Business Development Manager, Silicon Photonics, CEA-Leti [caption id="attachment_28769" align="alignright" width="358"] (Courtesy: Leti SOI Consortium)[/caption] Leti helps companies make photonics products they can bring to volume foundries, explained Hardy. (btw, they’re presenting 21 (!) papers – including 5 invited – at PhotonicsWest 2020. Read about that here). You want to do integrated photonics to bring down costs, reduce power consumption, and scale (for higher volumes and reduced footprint). There are essentially three substrate choices: InP, SiN or SOI. SOI uses CMOS processes, so it’s low-cost and can be used in high-density photonic integrated circuits. What about the laser? Leti has developed III-V on silicon bonding, so you can have the laser on 4” III-V with a 300mm CMOS process (this is what Intel’s doing). They’re moving to 300mm wafers, 3D and advanced packaging. While communications is the big application realm, Leti is also applying photonics in automotive, medical, environment and computing. In the computing realm she gave the example of the European QuantERA SQUARE (Silicon Photonics for Quantum Fibre Networks) project for which Leti is doing the quantum emitter for absolute security and computing, wherein the transceiver/receiver for quantum cryptography integrates a hybrid III-V on silicon pump laser. Other examples of their work include miniature, low-cost and agile lidar for automotive and industrial applications (they’re working on a beam-steering emitter for an optical phased array). GlobalFoundries Silicon Photonics Solutions for Wired Infrastructure – Anthony Yu, VP, GF [caption id="attachment_28770" align="alignleft" width="684"] (Courtesy: GlobalFoundries SOI Consortium)[/caption] GF is giving their photonics business a big push. Optical interconnects are the future, said Yu, so they’re putting a lot of money into it. With data streaming multiplying by 3x/year and a current foundry TAM of $63 billion, the opportunity is huge. Fab 10 in Fishkill runs their 90WG process on 300mm wafers. A new process, 45CLO (also on 300mm) for O and C bands is going into the Malta fab. A big focus here are optical transceivers that convert RF signals to light. They see RF on SOI in a monolithic solution is needed to serve 100Gbs applications. They’re also moving to co-packaging optics: the packing technology will surround it with photonic chiplets. Customers have indicated that pulling the signals off the chips is limited by power, so they’ve worked hard on the fiber attach with MEMS and packaging technology for co-packaging. GF relies on substrate providers for high-quality SOI, and they have a world-class development team, he concluded. Integrated Electro-Photonics Design Platform – A multi-physics, multi-fabrics system design solution – Scott Li, Sr. AE Manager of Custom IC Platform, Cadence [caption id="attachment_28771" align="alignright" width="374"] (Courtesy: Cadence SOI Consortium)[/caption] This talk focused on photonics design challenges and solutions – including the CurvyCore™-based PDK for waveguide creation modal properties calculation that Cadence will soon be announcing. It’s a math-based engine that generates complex curvy shapes to support photonics. The first design challenges, said Li, are at the circuit level: how to do the schematics. The detailing tools, timesteps management and circuit simulation need to give the user the best performance. Cadence is working in close collaboration with a company called Lumericable on this. The next set of design challenges come at layout – especially generating curvilinear layout for any shape so that there are no gaps in connections. This is where CurvyCore comes in, fully automating layout and making it easy to modify. This includes place route, DRC and LVS for curvy shapes. The final challenge is at the system level. There is work to do here, but Cadence is collaborating closely on solutions with key partners. The ultimate goal is for photonics layout and editing to be available with all the features designers get in electronics editing. Silicon Photonics for High Volume and High Performance Optical Interconnects Applications – Thierry Pinguet, Technical Leader Engineering, Cisco /Luxtera [caption id="attachment_28772" align="alignleft" width="396"] (Courtesy: Cisco/Luxtera SOI Consortium)[/caption] Over the last decade there’s been steady growth in optical high speed interconnect solutions, mainly driven by HPC, enterprise, and especially the hyperscale datacenter. The largest volumes are for intra datacenter interconnect (between servers). Now mobile applications for backhaul are also driving volume for high speed optical interconnect for 5G network implementation. ASICs and photonics are getting closer as the industry moves to put them in the same package. But everybody does silicon photonics differently (even within Cisco). Luxtera tries to use the same infrastructure as electronics, but patterning is still a challenge: it’s not 90o “Manhattan” style. The wafers are no problem – they work with leading wafer suppliers like Soitec and SEH. They have explored a “double SOI” substrate (like a mirror), which showed large insertion loss improvements in grating couplers . For the electronics and the laser (MEMS), they do a micropackage, although at one point they also did monolithic integration. For better performance, they’re moving to TSVs. A hot topic is ASIC and photonics co-packaging. You can use optical tiles, but then the light is remote, like a power supply. No matter how you do it, though, the bottom line is that silicon photonics is the only way forward for the data center. PH18: World’s First Open Commercial Silicon Photonics Process and PDK from TowerJazz – Masanobu Kumazaki, Engineer, TowerJazz. This presentation was given in Japanese without translation into English, and is not available on the consortium website. But the slides showed at the event indicated that their PH18 is the world’s first open commercial silicon photonics offering. For optical transceiver components, silicon photonics provides another opportunity for a specialty foundry. It is a high-growth market. The TowerJazz offering is 220nm SOI, and uses standard EDA tools from Synopsys, Cadence and Mentor for design flow.

Digitimes Research is predicting a doubling of the global SOI market between 2019 and 2024, "...thanks to significant expansion in applications to mobile devices, communication infrastructure, IoT devices and automotive electronics in the 5G era...". (Read the full article in Digitimes here.) Beyond the continued enormous success of SOI in front-end modules (FEMs) for RF (aka RF-SOI, which as we know is found in every smartphone on the planet), the report cites high growth specialty areas such as imaging chips for smartphones and photonics in data centers. They also predict that FD-SOI will be "massively applied" in 5G, with applications in base stations and data centers. And of course, low voltage and low power consumption will be the big drivers in IoT and wearables. All this is driving Soitec, the major SOI wafer manufacturer, to expand capacity at its facilities in France and Singapore in 2020, says the report. This is happening in strategic cooperation with Shanghai-based Simgui. As noted in ASN about a year ago, Soitec and China’s SOI wafer leader Simgui announced an enhanced partnership and increased production capacity of 200mm SOI wafers in China, securing future growth. At that time the two companies redefined their manufacturing and licensing relationship to better serve the growing global market for RF-SOI in mobile and Power-SOI in automotive and consumer electronics. Separately, Okmetic of Finland, which specializes in SOI wafers for MEMS, sensors and RF, is also doubling its capacity (we covered their 2019 Shanghai presentation here.) (Image courtesy: Soitec)

The SOI Consortium’s next annual event in Japan takes place on the 30th and 31st of October in Yokohama. Both days of the SOI Design Symposium will take place in the Yokohama Landmark Tower. The event is complimentary, however pre-registration is required – just follow the link here. Rest assured that in addition to the excellent program, the agenda provides ample time for networking.Wednesday, October 30 -- RF and ULP on SOI: IP ProductsOctober 30th showcases industry leaders with ULP IoT applications by NXP, and opportunities in the RF space by STMicroelectronics and Toshiba. The strong development of the design and EDA platform is discussed by ARM, Silvaco, Attopsemi and Dolphin. GlobalFoundries will present on their predictive reliability platform for RF, while Incize discusses the criticality of RF characterization and Secure-IC addresses to important topic of IC security.The day finishes with an overview of the SOI ecosystem by the SOI Industry Consortium. (See the full agenda here.)Thursday, October 31st -- SOI Enabling Photonics and Power InnovationWe start the day with two keynotes on High Voltage SOI electronics for automotive by NXP followed by Soitec on engineered substrate solutions. The Silvaco overview on RF modeling and SOI NB-IoT by SITRI promises to be very interesting. Then the day will offer a deep dive into Photonics touching applications with Cisco, foundry offerings with TowerJazz and GlobalFoundries, EDA with Cadence, and advanced SOI Photonic solutions by Leti-CEA. An ecosystem and market outlook by Soitec wraps-up the day. (See the full agenda here.)We look forward to seeing you there!