NXP

Let’s celebrate! As of April/May 2020, Advanced Substrate News – or ASN for short, and now aka the SOI Consortium newsletter – has been bringing you news for 15 years. I hope you’ll forgive me if this post has a personal angle, as I have been the Editor-in-Chief since Day 1 back in 2005. One of the things I’ve learned over my career covering technology in general and SOI in particular is that “new” technologies are never really new. They don’t pop out fully formed like Venus Boticelli-style. They take years – decades, even. SOI is no exception. What is exceptional about SOI imho is that the ecosystem – from the substrate providers to the end-product designers – keeps finding new things to do with it. There have always been naysayers – and for a while it took on an quasi-fanatic ferocity. There were those who quipped that SOI was the technology of the future...and always would be. But as it turns out, SOI’s is, has been and will be the right technology at many right moments, and I don’t see any sign of that changing in the years to come. We Need a Newsletter! [caption id="attachment_32012" align="alignright" width="189"] My Design News piece on SOI from June 2000 - it changed my life![/caption] As so much in the SOI story, ASN began with Soitec. I first encountered Soitec when I was working as Contributing Editor in Europe for Semiconductor International in the mid 1990’s. It was a start-up of just a few people that made silicon-on-insulator aka SOI wafers. Most of us at the time had barely a notion of what that was all about, but they had an intriguing story to tell about higher performance and lower power. It so happened a few years later (circa 2000) I was also writing for another publication called Design News – not about chip design, but product design, for folks designing cars and consumer electronics and washing machines and such. I kept hearing a new requirement added to the product-design mantra of faster-smaller-cheaper: lower power. It seemed to me that these SOI wafers could go a long way in solving some of product designers’ challenges. I pitched a story to my editor and it wound up on the cover (those were the days some might remember when trade magazines were on paper…). The big players were IBM for digital (in a current-events aside, DKY that those big iron machines at the US national labs cranking on the solutions for the current pandemic use IBM FinFET-on-SOI chips? Just saying…), Philips (now NXP) for power/analog, and Soitec for wafers – and of course Honeywell for aerospace and the big electronics players in Japan for all sorts of things automotive and ultra-low power. Top management at Soitec read the piece and saw that I “got it”. They brought me on board as a consultant, writing early websites, PR, brochures and such. But also most importantly, they invited me “in” – I sat in on sales reviews and attended the big shin-digs they sponsored on the Riviera and in the Alps. The people I met there – and stayed in touch with – were many of the ones that drive the industry today. (Of course, that was then, this is now: I don’t have that insider status any more, but I’ve kept in touch with and often still rely on the expert advice of people I met during that heady time.) Anyway, one day at the end of 2004, the Soitec folks said to me, “We need a newsletter.” They asked me to come up with a concept they could pitch to the Board. Since Soitec was also doing GaN SiC at the time, I thought it should be called Advanced Substrate News – ASN for short. And we agreed it should involve the entire ecosystem: end users, equipment manufacturers, academics, suppliers of all sorts, and especially: chip designers. But it was not an easy pitch. Who’d want to read about SOI wafers, they asked? Wouldn't we run out of things to say after two or at most three editions? But the idea was a solid one: ASN could be a bully pulpit for the nascent SOI ecosystem. Happily it won the day. I was named Editor-in-Chief, and have held that title ever since. Our very first edition (we were a print quarterly then) had about a dozen articles on SOI, including automotive with Philips, ultra-low power FD-SOI with Oki for Casio’s G-Shock watches (oh yes – it goes back a long ways!), low-power (by a company that Arm then bought), high-performance, high-resistivity SOI wafers for RF…it was all there. And if you look at what we cover now, it’s still all there – albeit better than ever and growing fast. (I just listened to the most recent Soitec Q4'20 quarterly financial report audiocast – announcing that they’d just had their best quarter ever – largely driven by RF-SOI.) We Need a Consortium! In 2007, the SOI Consortium was created with 19 members (a dozen of whom are still members today). As ASN Editor-in-Chief, I was honored to be part of that effort, participating in the meetings where we hashed out what it was all about and what a consortium would do. It was a great opportunity to meet the movers and shakers across the industry, many of whom I’m still in touch with. We published steadily, as the years, technologies and applications came and some went, but ASN readership continued to grow worldwide. Then in 2015, I got an email from the head of the Shanghai Academy of Sciences, which had recently spun off an SOI wafer maker called Simgui. He was (and is!) an ASN reader (though now he’s China’s Vice-Minister of Science Technology). Would I come to Shanghai and present some of the SOI-based applications ASN had been covering to his team there? They’d been working on SOI in parallel for many years, and were interested in where it was going in Europe and America. That was exciting! My first trip (of many, now) to China, it coincided with Semicon China 2015 and the announcement of the “Big Fund”. It was hall upon massive hall of stands immense and tiny, and the level of excitement was nothing short of amazing. (I was one of the only Western journalists there, and essentially broke the story in a piece I wrote for Consortium member Applied Materials’ customer magazine). That trip opened a lot of doors for me and ASN. As the SOI Consortium teamed up to with partners in China to host symposia there, we devoted more and more extensive coverage in ASN to those exciting events. [caption id="attachment_32041" align="alignright" width="328"] Here's some of our core players at the SOI Consortium: Executive Co-Directors Carlos Mazure (also of Soitec) and Jon Cheek (also of NXP) on the far left and right, respectively, Event Manager Iris Rith in the middle, me (Adele Hars) next on the right. We're joined here by Lucy Dai (2nd from left) of Simgui.[/caption] Eventually in 2016, ASN moved under the aegis of the SOI Consortium. We’re quite a jolly band that I have the privilege of working with. Granted at the time of this writing, the world is a difficult place, with so much uncertainty. But there are exciting times ahead with new products and technologies enabled by SOI, and you can be sure we’ll be covering them. RF-SOI will continue its juggernaut path in 5G mmWave. FD-SOI is steadily defining the new mainstream at the edge. The huge amounts of data the world is generating is driving photonics (which is all about SOI) to new heights. SOI for power (meaning high-voltage – think smart power) and imagers continues to grow. [caption id="attachment_32045" align="alignleft" width="99"] That's me - Adele Hars, ASN Editor-in-Chief - at the SOI Consortium's 2019 FD-SOI Symposium. (Photo courtesy VeriSilicon)[/caption] I’m honored to have brought you ASN for the last 15 years. Our archives are truly a treasure trove, and our mailing list of over 2500 really is an industry who's who. We’ve published well over a thousand (!) pieces in that time, most of which I’ve written with guidance from many an expert. However, we of course encourage our readers to pitch stories and/or submit SOI articles for publication consideration - so please, don't hesitate! I want to thank you all for your interest and your continued support. And thank you especially to all the SOI experts out there who so generously – and so patiently – share their time and enthusiasm with me and our readers. Stay safe! With warm regards, - Adele P.S. If you're not already on our emailing list and would like to join, just fill in the form at the bottom of this page. Thanks!

Here is our second post about the SOI Consortium’s Japan Symposium this past fall. This will provide summaries of eight very informative presentations on SOI in IoT and automotive by NXP, Dolphin Design, Leti, Silvaco, Arm, I-fuse and Secure-IC. There’s a lot of content to summarize, so this post is about twice as long as those we usually do. But you’ll want to read right to the end, for sure! In case you missed our previous post on the 5G/RF-SOI presentations given at the Japan event, you can read it here. Our next and final post on the Japan event will cover photonics presentations by Cisco/Luxtera, TowerJazz, GlobalFoundries, Leti, Cadence and Soitec. By way of reminder, the Japan SOI Symposium was a great success, with both days well attended. If your company is a member of the SOI Consortium, you can now access most of these presentations on our website. You can also click on the illustrations in this post to see them in enlarged versions. [caption id="attachment_28106" align="alignleft" width="366"] (Courtesy: NXP SOI Consortium)[/caption] The IoT World Enabled Through SOI - Jon Cheek, NXP Sr. Director, Front-End Innovation For NXP, FD-SOI introduced the ability to easily add different functionalities to the technology node like ULP, eNVM, support for high-voltage and embedding RF. For them, said Cheek, it’s about the range, and with adaptive back bias, you can “get crazy”, so you can really achieve amazing things. In fact, they think they now have the lowest leakage SRAM in the industry, thanks to body biasing. The i.MX 7ULP is finding significant success in wearables. Their “crossover” chips are the latest beneficiaries of FD-SOI with body biasing. The “new normal”, they offer huge improvements for real-time operating systems – which is of course key for edge computing. (As you can imagine, the audience was intently taking notes throughout -- this was a really excellent talk!) It also is great for machine learning, as it is designed to unlock the potential of voice-assisted end nodes. The IP they needed is now available from multiple vendors, noted Cheek, such as Tensilica and VeriSilicon. Another key play will be in visuals for industrial computing. He concluded by observing that the automobile is the ultimate IoT machine, with 10x the amount of code now found in leading edge airplanes. That’s where the i.MX8 and 8X come in. [caption id="attachment_28104" align="alignright" width="323"] (Courtesy: NXP SOI Consortium)[/caption] High-Voltage SOI – Enabling Automotive- NXP Jon Cheek gave this presentation on the second day of the Japan event. Long-time followers of SOI will know that NXP has been excelling in high-voltage (HV) SOI for well over two decades now (including the pioneering work done by Philips, now part of NXP: their EZ-HV SOI patent dates back to 1993). It’s probably safe to say that NXP's SOI-based automotive chips are used by virtually every carmaker on the planet. HV follows well behind the leading edge – it’s currently mostly around 130nm (the limits are related to metalization). Reason #1 it’s on SOI? SOI-based technologies are incredibly reliable, especially in the automotive culture targeting the three zeros (0 emissions, 0 accidents and 0 time wasted). Today’s car manufacturer’s are going to a distributed environment, and SOI still provides a huge advantage, making parts that are smaller, lower power and more reliable – so it drives a lower BOM for automakers.In conclusion, said Cheek, NXP’s leadership through SOI innovation enables scalable solutions, high voltage analog integration, sensor integration, and reliable safe passenger experience. [caption id="attachment_28101" align="alignleft" width="432"] (Courtesy: Dolphin Design SOI Consortium)[/caption] Improving SoC Energy-Efficiency with Dolphin Design Platforms – Nicolaus Gaude, BizDev Product Marketing, Dolphin Design Dolphin has a series of platforms, techniques and IP for increasing speed and drastically improving energy efficiency in SoC design. Gaude introduced their Speed Platforms, which include a Power Management Platform and a Processing platform, both of which make dramatic improvements in energy efficiency. The Power Management Platform keeps control of power management from architecture to design, resulting in a 10x improvement in energy efficiency. The Processing Platform comprises configurable RTL clusters for best-in-class (100x) energy-efficiency. Gaude then turned to the Dolphin’s Adaptive-Body Bias (ABB) IP for breakthrough energy-efficiency with FD-SOI. This is real-time, “on-the-fly” body biasing: the IP does it all. It is silicon-proven on GlobalFoundries’ 22FDX with Arm cores and Invecus standards cells SRAM, with breakthrough energy efficiency. [caption id="attachment_28108" align="alignright" width="363"] (Courtesy: Silvaco SOI Consortium)[/caption] Platform Infrastructure for SOI-IP Ecosystem – Thomas Blaesi, VP of Global Marketing, Silvaco The massive use of IP is both an advantage and a challenge, began Blaesi. There are solutions out there, but they are disconnected. Typically SoC/IP designers, IP librarians and support folks use various systems, while procurement, finance and legal use others. This is a problem for both the providers and the consumers of IP. Silvaco has a new system called Xena that centrally organizes all IP data: it’s an IP repository for tracking accounts, products, contracts, devices, support, compliance and reporting. One of the first beneficiaries of Xena will be the SOI ecosystem, as providers of SOI IP are already signing on. Beyond the organizational advantages, Xena has patented “finger printing” and “DNA analysis”, so there is a digital representation of each IP on an SoC that can’t be reverse engineered. Each fingerprint contains list of unique signatures of each file in an IP or SoC. A file’s unique signature is created from the entire file content, and that signature is guaranteed to be unique to that content. It enhances support for all versions of common design files: hard IP, soft IP, and embedded software. Because it’s cloud or enterprise based, it will be particularly useful for large organizations. Fingerprinting and DNA analysis are vendor agnostic, universal, and easy-to-use tools and methodologies for IP lifecycle management, he concluded. [caption id="attachment_28103" align="alignleft" width="463"] (Courtesy: Leti SOI Consortium)[/caption] Ultra-low power, FD-SOI based IP, in the space of IoT, Health Care, Smart Connectivity 5G – Michael Tchagaspanian, EVP Industrial Partnerships, CEA-Leti This presentation began with a review of the explosion in devices with IoT and related investments, then connected all the ways in which innovations powerhouse Leti is contributing – from the SOI wafer level to the chip level – which is to say practically everywhere! Especially hot topics in FD-SOI included: the roadmap to sub-10nm; CoolCube monolithic 3D; new embedded memories; power amplifiers; Ultra-Wide Range DSP; smart sensing local processing (including haptics, imaging, infrared advanced processing); local processing with edge AI; and spike coding for deep neural networks. He showed information on two always-on/on-demand transmission 28nm FD-SOI IoT test chips that taped out in mid-2019: the Warrior and the Samurai. And finally, he covered silicon-proven IP that Leti has for FD-SOI including power management blocks, lots of RF IP (including low-power RF wake-up), sensor interfaces, clockless network-on-chip and new SRAM technologies. These and more will be covered at the next Leti Innovation Days in Grenoble (June 2020) – during which in parallel, btw, there will also be a European SOI Summit hosted by the SOI Consortium. [caption id="attachment_28099" align="alignright" width="475"] (Courtesy: Arm SOI Consortium)[/caption] FDSOI Enablement for a Total Compute Future – Manuj Rahor, Director Emerging Technologies Product Marketing, Arm Subtitled A perspective on system optimization with Arm FDSOI IP, this presentation reviewed how Arm is enabling system gains through optimization across IP boundaries. This is work happening in the Arm Artisan Physical Design Group (PDG), which provides logic, memory and POP (processor optimization package) IP as well as various products to help ease implementation challenges for advanced nodes. In this case the focus is on Total Compute enablers on Samsung 28nm FD-SOI (called 28FDS) – specifically three building blocks recently launched on FD-SOI. The first is the 128Mb Wide Capacity embedded MRAM (an eNVM to replace eFlash) compiler for storage delivered to Samsung in July `19. It was demonstrated in silicon in the Musca-S1 Smart IoT Device Demonstrator on 28FDS, an energy efficient IoT device with eMRAM secure boot on-chip storage. [Read our coverage from March 2019 here.] The second is a novel design developed with Spin Memory. It recently taped out on 28FDS and is slated for delivery in 2020. Adding an “Endurance Engine to the eMRAM that was delivered in 2019, the ARM-Spin innovation delivers RAM-like performance with increased speed and endurance. What’s at issue here is a change in use cases. Use cases served by eFlash were not written to that often; now with sensors (as in IoT) that continually gather and write data, eFlash endurance is not sufficient. The third is billed as an SRAM replacement compiler. Its MRAM as RAM in A-class systems, with significant energy and performance gains. Again, this is a use-case issue: retention is lower (this is for weeks months, whereas the other solutions are for 10 years). But you can get more RAM than SRAM into the same footprint, so you get a 60% reduction in DRAM traffic and increased performance. Delivery for this is marked as 2020+. [caption id="attachment_28100" align="alignleft" width="294"] (Courtesy: Attopsemi SOI Consortium)[/caption] I-fuse™: A Disruptive OTP Technology – Dr. Shine Chung, Chairman, Attopsemi I-fuse is a disruptive OTP (One-Time Programmable) technology without disrupting a fuse. The goal was a 100x increase in reliability at 1/100th of the cell size and 1/10th the power. It has now been demonstrated in GlobalFoundries’ 22FDX FD-SOI technology for energy harvesting applications. In the OTP IP technologies, explained Dr. Chung, they defied the conventional wisdom of breaking a fuse to maintain a permanent programmed state forever: Attopsemi’s I-fuse™ is actually a “non-breaking” fuse. “I don’t mind to break a fuse, but I do care about breaking a fuse by explosion”, said Dr. Chung. “The I-V curve of programming a fuse beyond the break point actually shows more like an explosion. The anti-fuse OTP also ruptures gate oxide by explosion. On the contrary, I-fuse™ is a disruptive OTP technology without disrupting a fuse.” He concluded, “By using MOS as switches to enable discharging two capacitors, through cell and reference cell respectively, and compare the discharge rates, the resistance in the cell can be determined higher or lower than the reference resistance so as to convert into logic data. The read energy consumed is only 1/100 of the conventional sensing, which is good for energy harvest IoT applications. Eventually most IoT devices will be battery-less.” [caption id="attachment_28107" align="alignright" width="398"] (Courtesy: Secure-IC SOI Consortium)[/caption] AIoT Embedded Security Using FD-SOI – Yan-Taro Clochard, Japan Sales Director, Secure-IC In addition to opportunities, the impact of AI on IoT (aka AIoT) adds new threats to edge devices. Design for security and in-depth security is required, down to the physical layer. For example in automotive, sensors gather data and AI analyzes it – but the enabler is security. The challenge of AI is the increase in data and connectivity with unsecured devices. FD-SOI is a key for Secure-IC’s Securyzer security module: it leveragesFD-SOI properties to secure the AIoT world. It is flexible, and tuned for each customer. Here, FD-SOI enables the creation of physically secure systems, with secure boot and firmware updates, cryptographic services, key management and secure storage.

The industry continues rewarding luminaries of the SOI ecosystem. Recently recognized are Jean-Pierre Raskin for RF-SOI, Lattice Semi and NXP for FD-SOI products, and Bich-Yen Nguyen for her work in SOI. The SOI Consortium extends hearty congratulations to all the winners and their teams. Professor Jean-Pierre Raskin was awarded by the prestigious Médaille Ampère 2019 for the originality of his scientific work in the field of RF-SOI technologies for wireless communication. The international award was delivered by Mr. François Gérin, president of the SEE - Société de l'électricité, de l'électronique et des technologies de l'information et de la communication, on December 3rd, 2019, in Paris, France. We’ve long covered the work of Professor Raskin and his UCLouvain team – which is largely responsible for why SOI is in every smartphone on the planet. It’s a great story (read it here) and it goes on! In his Ampère acceptance speech, Professor Raskin said, “...significant industrial research and development is being performed toward fully integrated SOI front-end-modules. Notably, the 45nm PD-SOI [RF-SOI] and 28nm and 22nm FD-SOI nodes are being extensively designed with to develop 5G mm-wave low-noise amplifiers (LNA), power amplifiers (PA) and switches, in particular at 28 GHz. […] Overall, SOI is expected to be a big contender as a technological platform to enable mass production of millimeter wave 5G and ultra-low power RF IoT devices and products in the near future.” [caption id="attachment_27119" align="alignleft" width="294"] Lattice CEO Jim Anderson (left) and Mark Lipacis (right), Managing Director of Jefferies (Courtesy: GSA Lattice Semi)[/caption] Lattice Semiconductor was the recipient of the Global Semiconductor Alliance’s (GSA) 2019 Analyst Favorite Semiconductor Company award based on technology and financial performance. The GSA awards recognize the achievements of top performing semiconductor companies and the 2019 winners were announced at the annual GSA Awards Ceremony held on December 5, 2019. In thanking his team, Lattice CEO Jim Anderson, added, "We are even more excited about the solid execution of our product roadmap, specifically, the accelerated product rollouts of both CrosslinkPlus and our next generation FPGA platform based on FDSOI technology, which will be key catalysts to our achieving sustained long-term revenue and profitability growth.” [caption id="attachment_27120" align="alignright" width="71"] (Courtesy: NXP)[/caption] NXP was a recipient of a Best-in-Show Award at the 2019 Arm TechCon this fall. As was noted by Brandon Lewis, Editor-in-Chief of Embedded Computing Design, “The i.MX RT1170 crossover MCU marks a technology breakthrough in MCUs, running up to 1GHz while maintaining low-power efficiency. It is architected to deliver a record-setting performance, with a 6468 CoreMark score and 2974 DMIPS while executing from on-chip memory. The solution uses advanced 28nm FD-SOI [note: fabbed by Samsung Foundry] technology, making NXP the first company to build MCUs in this advanced technology node. This new MCU family is redefining the "edge" and MCU landscape, bringing unprecedented performance and high levels of integration to propel industrial, IoT, and automotive applications.” And finally, Soitec Senior Fellow Bich-Yen Nguyen was elevated to the status of IEEE Fellow in the Class of 2020 “for contributions to silicon on insulator technology”. As previously noted in her IEEE bio, “Her honors and awards include the Dan Noble Fellow, the highest technical award at Motorola; the Master of Innovation Award; and the first national Women in Technology Lifetime Achievement Award. She holds over 200 worldwide patents and has authored more than 180 technical papers on integrated circuit technologies.”

The first day of the SOI Consortium’s recent China event – the 7th Shanghai FD-SOI Forum – was full to bursting in every way: the room, the networking, the level of expertise, the in-depth presentations and the overall energy. We covered the Samsung and GlobalFoundry keynotes in our previous post (if you missed it, read it here).This post will recap the rest of the presentations given during the day. (If your company or institution is a member of the SOI Consortium, you’ll be able to access the full presentations online.)International Business Strategies (IBS) – Impact of AI on Automotive and IoT, and Opportunities in China (Handel Jones, CEO) When it comes to deep insights on China + tech + analytics, and especially with a thorough understanding of FD-SOI markets, Handel Jones is arguably the world’s leading expert. Here are some of the observations he shared. Though the chip industry will see declines across the board in 2019 (he sees 13.5%), he sees a return to growth in 2020. By 2030, he sees it as a trillion dollar market, of which China will have half. AI is a key driver – and will become more prevalent at the edge. Major drivers will include preventative medicine, gaming, NB-IoT and 5G. At the chip level, FD-SOI has a lower cost/chip compared to bulk – you’ve got small chips and high yields. Sensors – especially image sensors – are a key area, and this is another place where FD-SOI is better than bulk. He sees chip shortages in the 2022-24 time frame (as opposed to the current oversupply), so now is the time that China should be establishing large FD-SOI capacity.NXP – Automotive, Industrial and IoT Solutions Leveraging FD-SOI (Ron Martino, VP GM) In terms of power consumption, computing is easy but data transmission is hard, Ron Martino reminded the audience at the onset. That’s why you need the edge. This is where FD-SOI comes in, and if you want to have leadership, you should be leveraging body biasing, he said. In terms of machine learning, a lot can happen at the edge on the smallest devices. NXP is now shipping a very wide range of products based on FD-SOI, including the i.Mx7 and 8 families and the new RT crossovers. The latest announcement is the i.Mx RT 1100 MCUs, a very low-cost processor solution for high volumes. The i.MX7 ULP is in mass production for wearables, with record low leakage and high performance. The i.Mx8 and 8x are going into a broad range of applications – from retail solutions for automated checkout to pasta makers, and automotive applications for full cockpits with vision detection, as well as things like parking, V2X and in-vehicle monitoring.Sony Semi – Low Power IoT Products with FD-SOI eMRAM Technology (Kenichi Nakano, GM) Chips built on FD-SOI with eMRAM are in production, said Kenichi Nakano. In GNSS/GPS, Sony is the #1 in lowest power consumption worldwide, thanks to FD-SOI, he continued. They’ve had 70 remarkable design wins, giving them over 50% market share in the sports and health watch markets, he said with a tip of the hat to the FD-SOI ecosystem and SOI Consortium. In GNSS, performance is very important – and now they can do it in water, which is huge. Development cycles are shorter than ever – for the latest chip it started in February 2018 and was in production by the spring of 2019, achieving decreases of 20% in power, 30% in area and 10% in cost. Integrating eMRAM was easy in terms of the design flow and manufacturing, with production yield of 97-100%. So with the GXD5605GF they’ve got the first GNSS chip with FD-SOI/eMRAM/RF in the world and it’s on 28FDS/eMRAM technology. It’s very reliable and very good, he concluded.Rockchip – Challenges of AIoT Chip (Feng Chen, SVP) At the beginning of this year Rockchip announced the launch of their RK1808, a low-power AIoT solution with built-in high performance (3TOPS) NPU fabbed in GlobalFoundries 22FDX, said Feng Chen. Their clients were very happy that Rockchip delivered the real power and performance numbers they’d promised. Because of the power/performance it delivers, FD-SOI (both 22 and 28nm) is very well suited for AIoT chips, he said. It’s very cost-effective in terms of NRE and die, and there’s room for further savings. While the ecosystem needs a unified push, FD-SOI is good for the market in China, and China has the volumes FD-SOI needs. Rockchip sees particular potential in retail and smartphones.Panel – Verticals Driving FD-SOI VeriSilicon CEO Wayne Dai moderated the first panel, asking first why China should adopt FD-SOI. Soitec CEO Paul Boudre said because it is a big, dynamic market (noting that Sony’s first FD-SOI GPS win was in China). Handel Jones said that at the wafer level, there was cost parity, but with FD-SOI chips are smaller and higher yield. The main reason it’s taken so long to get going was IP, but that’s changing now, he added. Dai’s next question was about the top application fields the panelists predicted for 2020. Sony’s Kenichi Nakano said wearables with connectivity, low power consumption, small size and high levels of integration; Rockchip’s Feng Chen agreed. NXP’s Ron Martino said FD-SOI for automotive, machine learning and edge computing was shipping now, with wearables ramping.VeriSilicon – Low Power IoT Connectivity IP Design Based on FD-SOI (Yi Zeng, Director, IoT Connectivity Platform) The “value” of IoT data is not yet being generated, noted Yi Zeng but AI can help here. The IoT industry needs innovation for both chips and networking. SiPaaS – which stands for Silicon Platform as a Service – as offered by VeriSilicon can help lower the barrier to entry. [In the SiPaaS model, VeriSilicon has its own IP-based core. Based on the company's advanced chip design capabilities and mass production service experience, it has created a variety of silicon-proven chip design platforms that can significantly reduce the customer's chip design cycle.] They have FD-SOI IP for NB-IoT, BLE, GNSS and sub-1 GHz. The BLE (Bluetooth) RF IP is a complete offering optimized for low power on GlobalFoundry’s 22FDX. The NB-IoT IP is also optimized on their 22FDX ZSPNano, an energy efficient general purpose MCU+DSP core on 22FDX. And they’ll have results of test chips for GNSS RF IP on 22FDX by the end of this year.Secure-IC – AIoT Embedded Security Using FD-SOI (Hassan Triqui, CEO) While AI enables products and services, it’s important to plan for security early in the design cycle, said Hassan Triqui. Software is not enough to protect edge-to-cloud. Secure-IC’s hardware security module, Securyzr, is an IP block that can be embedded into every device to answer security functionalities such as root-of-trust and key management. In sleep-mode/tunable cryptography, FD-SOI allows the creation of physically secure systems. (Note that designers are leveraging FD-SOI’s unique body biasing for ultra-low-power deep-sleep modes.) Because safety and privacy require a combined solution, Securyzer is particularly well-suited to IoT chips built on FD-SOI, he concluded, so that IoT adds value to AI, and not just the other way around.Soitec: FD-SOI – The 5th Gear for mm-Wave Radio (Michael Reiha, GM FD-SOI Business Unit) There are four key areas to 5G, explained Michael Reiha: coverage, number of antennas, frequency and traffic density. 5G mmW access architectures are currently inefficient in terms of power and performance, but FD-SOI is ready for 5G access as both an analog and hybrid beamformer. For MU-mMIMO (massive MIMO), the RF front-end modules (FEMs) and transceiver will fully exploit FD-SOI. Sensing, calibration and control enabling hybrid beamforming and multiple users is easy in FD-SOI. The adaptive body biasing on the horizon will reduce power of FEM mixed-signal circuitry, and be a disruptive technology.STMicroelectronics – Automotive MCUs in 28nm FD-SOI for ePCM NVM (Shan-Lin Liu, Automotive Marketing Manager) As a leader in the automotive market, ST has seen that increased data flows in automotive are driving demand for higher performance and bigger memory in automotive MCUs, said Shan-Lin Liu. ST has taken a unique approach to NVM with embedded PCM (phase change memory) on 28nm FD-SOI. This gives them energy-efficient, high-performance cores with larger NVM memories, and it’s already qualified up to auto grade-0. PCM (vs MRAM) is BEOL. It uses two cells, so it’s more reliable and is good at high temperatures, he said. With FD-SOI, they can go up to 165o, and it’s soldering compliant. The preliminary results of the first MCU chip are excellent. It’s now running in a car, replacing the previous generation 40nm eFlash product.Leti – Advanced FD-SOI for Edge AI (Emmanuel Sabonnadiere, CEO) To fully run artificial intelligence on the edge, research powerhouse Leti is working on an unsupervised learning neural network using advanced FD-SOI and a mix of other technologies. These include embedded non-volatile memory (NVM), 3D integration, and new design tools. Sabonnadière said this new approach is expected to exceed the performance levels of current digital deep learning with neural networks that are capable of handling time-domain signals, sound and speech—and may produce a first "killer app" for advanced SOI. AI will require compact and power-efficient circuits for the inference phase, when neural networks infer things based on new data they receive, close to the end user. The combination of FD-SOI, 3D integration, and NVM opens a path towards dedicated circuits with major performance improvement within the limited power budgets of distributed electronics. In Europe, he noted, privacy concerns are driving the move from the cloud to the edge. On the Leti roadmap, they’ve broken through the 10nm limit for FD-SOI, using strain and body biasing to compensate for transistor mismatch. Also of note: since 2016 Leti has had an ongoing collaboration with SITRI, the Shanghai Industrial μTechnology Research Institute, an international innovation center focused on globally accelerating the innovation and commercialization of More than Moore technologies to power IoT.GlobalFoundries – GF Fab 1 Dresden: Delivering Differentiation with FDX for the Future of Automotive (Thomas Morgenstern, SVP GM Fab 1) Dresden Fab 1, Thomas Morgenstern reminded the audience, is the biggest in Europe, where it is part of the Saxony ecosystem. GF is moving advanced mask-making to Dresden, which is the lead site and Center of Competence for FD-SOI. With the “pivot”, GF is providing platforms. Fab 1 is automotive certified for 22FDX (GF’s 22nm FD-SOI technology), with automotive tapeouts in 2019. “Automotive is a journey,” he said, of continuous improvement, and a mindset: it’s a zero defects culture. The ramp to volume production is well underway, with 26 tapeouts of 22FDX products this year – almost double that of last year. He showed high yield data of about a dozen products, adding that since the beginning of the year every tapeout was first-time right with decreased cycle time. The key specifications for 22FDX with eMRAM for Auto Grade-1 have all been demonstrated, and customer feedback has been excellent.Next: Shanghai International RF-SOI Workshop recap As you can see, it was a packed day for the FD-SOI part of the SOI Consortium’s Shanghai event. In fact the room was still packed at the very end of the day. Several hundred VIPs then headed out for the ever-popular and festive evening riverboat dinner cruise, where the non-stop networking continued.A big shout-out to our sponsors and supporters: VeriSilicon, Simgui, SIMIT, Soitec, Samsung, IBS Ion Implant, ShinEtsu, GlobalFoundries and NXP.The next day of the event was devoted to RF-SOI. That will be the subject of our next post.

GlobalFoundries Has Quietly Become A Player In Silicon Photonics Manufacturing - 31 March 2020 by Patrick Moorhead, Forbes. Blog: Body Bias Gets Its Own Book - 13 February 2020, Junko Yoshida, EETimes Asia. The authors of The Fourth Terminal: Benefits of Body Biasing Techniques for FD-SOI Circuits and Systems make the case for body biasing, describing it as “a new and efficient tuning knob.” Three design experts at STMicroelectronics, including Fellow Andreia Cathelin, have co-edited and written chapters for The Fourth Terminal. NXP's i.MX RT1170 Crossover MCUs (on Samsung's 28nm FD-SOI) - the industry's first GHz MCU - wins Best In Show Arm - TechCon2019 in the Microprocessors, Microcontrollers and IP category! (Embedded Computing Design, 9 Oct. '19)

The SOI Consortium’s next annual event in Japan takes place on the 30th and 31st of October in Yokohama. Both days of the SOI Design Symposium will take place in the Yokohama Landmark Tower. The event is complimentary, however pre-registration is required – just follow the link here. Rest assured that in addition to the excellent program, the agenda provides ample time for networking.Wednesday, October 30 -- RF and ULP on SOI: IP ProductsOctober 30th showcases industry leaders with ULP IoT applications by NXP, and opportunities in the RF space by STMicroelectronics and Toshiba. The strong development of the design and EDA platform is discussed by ARM, Silvaco, Attopsemi and Dolphin. GlobalFoundries will present on their predictive reliability platform for RF, while Incize discusses the criticality of RF characterization and Secure-IC addresses to important topic of IC security.The day finishes with an overview of the SOI ecosystem by the SOI Industry Consortium. (See the full agenda here.)Thursday, October 31st -- SOI Enabling Photonics and Power InnovationWe start the day with two keynotes on High Voltage SOI electronics for automotive by NXP followed by Soitec on engineered substrate solutions. The Silvaco overview on RF modeling and SOI NB-IoT by SITRI promises to be very interesting. Then the day will offer a deep dive into Photonics touching applications with Cisco, foundry offerings with TowerJazz and GlobalFoundries, EDA with Cadence, and advanced SOI Photonic solutions by Leti-CEA. An ecosystem and market outlook by Soitec wraps-up the day. (See the full agenda here.)We look forward to seeing you there!

The 45th (yes!) IEEE SOI Conference takes place 14-17 October 2019 in San Jose. Now called S3S –since it also covers 3D and subthreshold – it’s a networking event par excellence: a unique opportunity to meet firsthand the movers and shakers in the SOI ecosystem and the giants of R D. As always, it has a strong technical program you won’t want to miss. Plus this year there’s a full-day short course dedicated to FD-SOI design, and half-day tutorial on RF design. Get all the details and registration info at http://s3sconference.org/.The SOI Consortium’s own Executive Co-director Jon Cheek of NXP is one of the keynoters. In fact the consortium membership is extremely present at this event, with over half our member organizations having a hand in it. There’s a plenary talk by GF’s CTO/VP Subramani Kengeri, keynotes by ST Fellow Andreia Cathelin and NXP Fellow Rob Cosaro, and invited talks from Arm, Samsung and Dolphin Design, for example. And this year’s General Chair is Incize CEO Mostafa Emam. Focus Sessions #12 and 13 are all about FDSOI Platforms and Products, with invited speakers from Renesas, NXP, ST, ARM, GF, Huali and Dolphin Design, while focus Session #2 is all about RF-SOI. Here’s the agenda for the FD-SOI Design short course (which takes place on Thursday, 17 October):Short Course Opening and Welcome Philippe Flatresse, Business Development Marketing Director, Dolphin DesignGLOBALFOUNDRIES 22FDXTM Technology and Body Bias Compensation to Enable New Design Optimization Strategies Joerg Winkler, Fellow Design Engineer, GLOBALFOUNDRIESEmbedded Flash Memory Technologies and Applications in Advanced Nodes Memories Koji Nii, Vice President, Global Marketing Sales, Floadia CorporationEnabling the Adaptive Body Bias in Modern IoT Applications Vincent Huard, CTO, Dolphin DesignSoC Design Realization with Adaptive Body Bias Kripa Venkatachalam, IC Design Practice Director, Mentor Graphics Didier Roland, Application Engineers Manager, Mentor GraphicsAnalog Design Techniques for Microprocessors in FD-SOI: Power-Management, PVT Monitoring and Data Conversion Edevaldo Pereira Da Silva Junior, Senior Principal Engineer, NXP Semiconductors MPU/MCU R DLow Power Solutions for SoC Architectures Antonio Pullini, Senior Hardware Designer, GreenWaves TechnologiesSOI to RF Sidina Wane, CEO, eV-technologiesIf you know the way to San Jose, you'll want to be at S3S 2019, for sure!

Since the beginning of the year, there’s been a steady stream of excellent news around Samsung Foundry’s 28FDS, their highly successful 28nm FD-SOI offering. Let’s take a look at what’s been happening, as things do seem to be accelerating. By way of reminder, they announced the industry’s first eMRAM (embedded MagnetoResistive RAM) testchip tape-out milestone on 28FDS in September 2017 (you can read the press release here) - which was just a year after they had announced mass production of 28FDS process technology.At the end of 2018, Arm announced the industry’s first Embedded MRAM (eMRAM) compiler IP built on Samsung Foundry’s 28FDS process technology. Follow that with this announcement at the beginning of 2019: Soitec Expands Collaboration with Samsung Foundry on FD-SOI Wafer Supply. The two companies announced that Samsung had secured a high-volume supply of FD-SOI technology to meet industry's current and future demands especially in consumer, IoT and automotive applications. In March came two more big announcements. First: Samsung Electronics Starts Commercial Shipment of eMRAM Product Based on 28nm FD-SOI Process. As they noted in the PR, “Samsung’s 28FDS-based eMRAM solution offers unprecedented power and speed advantages with lower cost. Since eMRAM does not require an erase cycle before writing data, its writing speed is approximately a thousand times faster than eFlash. Also, eMRAM uses lower voltages than eFlash, and does not consume electric power when in power-off mode, resulting in great power efficiency.”Hard on the heals of that came the news that Arm and Samsung Announce IP Platform including eMRAM for 18nm FD-SOI. At the SOI Consortium’s Silicon Valley Symposium in April, Tim Dry (he’s Samsung’s Director of Foundry Marketing for Edge and End Point), gave a terrific presentation. Entitled Samsung’s FDS with MRAM: Enabling Today’s Innovative Low Power Endpoint Products, it details the company’s FDSOI roadmap for the IoT Endpoint Platform (and yes, you can download in its entirety). Then in May at the big Samsung Foundry Forum in Silicon Valley, Arm, in collaboration with Samsung Foundry, Cadence, and Sondrel, demonstrated the first 28nm FD-SOI eMRAM IoT test chip and development board. The Musca-S1 test chip demonstrates a new choice in SoC design for IoT solutions, said Arm. (Sondrel, btw, is Europe's largest independent IC design consultancy.)In parallel, Cadence announced: Cadence Custom/AMS Flow Certified for Samsung 28nm FD-SOI Process Technology. Especially aimed at digitally-assisted analog designs, what’s new here is that the Cadence custom and analog/mixed-signal IC design flow is now Samsung Foundry certified for 28FDS. Samsung’s 28FDS PDK techfile is Mixed-Signal OpenAccess ready, enabling customers to deploy OpenAccess-integrated, fully interoperable Virtuoso-Innovus implementation flows. For its part, at its Foundry Forum, Samsung unveiled extensions of the company’s FD-SOI (FDS) process and eMRAM together with an expanded set of state-of-the-art package solutions. They indicated that the development of the successor to the 28FDS process, 18FDS, and eMRAM with 1Gb capacity will be finished this year.And finally, companies like NXP are shipping exciting new products fabbed on Samsung’s 28FDS. Ron Martino, VP GM of NXP’s i.MX Application Processor Product Line covered key products in his presentation at the SOI Consortium’s Silicon Valley Symposium (see our coverage here). Among them: the i.MX7ULP for long battery life with 2D 3D graphics for wearables and portables in consumer and industrial applications; the i.MX 8 and 8X subsystems for automotive and industrial applications; and the i.MX RT series of “cross-over” processors. The i.MX RT ULP (real-time, ultra-low-power) series, which Martino says is the “new normal”, deals with a high number of sensor inputs. The i.MX RT 1100 MCUs, which have been qualified for automotive and industrial applications, are breaking the gigahertz performance barrier.In July, linuxgizmos.com reported that, “In June, NXP began volume shipments of its super power-efficient i.MX7 ULP, which it announced in 2017. The SoC is billed as the most power-efficient processor on the market that also includes a 3D GPU. […] the ULP version includes a 3D graphics capable Vivante GC7000.” (Vivante, btw, is a VeriSilicon company, which is an SOI Consortium member and a leading proponent of FD-SOI design and IP in China and worldwide.) This is leading to some really nice wins for NXP. For example, they’ve got Amazon's Alexa Voice Service (AVS) leveraging the i.MX RT crossover processor, enabling developers to quickly and easily add Alexa voice assistant capabilities to their products. The RT series has rapidly been expanded, with versions for voice-controlled devices and offline face and expression recognition capabilities for smart home, commercial and industrial devices.Also announced this summer: NXP and Microsoft Bring Microsoft Azure Sphere Security to the Intelligent Edge with a New Energy-Efficient Processor. That collaboration includes development of a new crossover applications processor in NXP’s i.MX 8 series integrating Microsoft’s Azure Sphere security architecture and Pluton Security Subsystem. Their customers “will be able to harness the high-performance and energy efficiency of NXP’s i.MX 8 applications processors combined with Microsoft’s unequaled security and assurance provided by Azure Sphere certified chips”. As Martino concluded in his presentation, “The future of embedded processing [is] enabled by FD-SOI.” And Samsung Foundry’s FD-SOI offerings are clearly a massive enabler of that future.

2019 will be a busy fall for the SOI Consortium and our members.First off are the SOI Consortium events in Shanghai and Tokyo, which are very popular indeed. We now have the dates locations locked in, so you’ll want to mark your calendars:Shanghai: 16 17 September 2019, FD-SOI Forum / RF-SOI Workshop. Both days will be held at the Pudong Shangri-La Hotel in Shanghai. The first day will focus on FD-SOI. The second day is all about 5G and RF-SOI. These are huge events – to get an idea of the magnitude, you can read our coverage of the 2018 event. Tokyo: 30 31 October 2019, Japan SOI Design Workshops. This year both days of workshops will take place in the Yokohama Landmark tower. The first day will be devoted to FD-SOI; the second day turns to More-Than-Moore – especially photonics and MEMS. Last year’s workshops were packed with excellent presentations and panel discussions, which we covered here. The SOI Consortium and members will also be giving talks at Semicon Europa, which is being held 13 – 15 November 2019 in Munich, Germany. The programs are currently being finalized. As soon as they’re ready, we’ll be sure to let you know so you can register and/or share the news with your colleagues and clients. But in the meantime, make sure you save the dates.Would you like to check out the presentations given at Consortium events in previous years? If you hover your cursor over the Events tab at the top of our home page, you’ll get a drop-down menu of events for the last five years (we’re working on adding more – we’ve been doing these events for over a decade!). Click through to any past event and you’ll land on a page where you can download most of the presentations that were given there. Of if you’re looking for past presentations given by any particular company, use the search engine at the bottom of any page on our website. S3SYou’ll also find many of our members at the IEEE/EDS S3S Conference in San Jose, CA, October 14 – 19th. S3S (formerly known as The SOI Conference) has been running in various forms for over 30 years. They always have an excellent line-up of speakers, plus it’s a great opportunity for networking with researchers from across the worldwide SOI ecosystem. BTW, while the deadline for general paper selection has already closed, papers of exceptional merit are currently being accepted for their Late News Sessions. See the 2019 Call for Papers for more information – those Late News papers need to be received by 23 August 2019 for consideration. Also, IEEE S3S Conference will once again host a full-day short course and a half day tutorial. These are very popular. The short course this year will be on SOI Design and Technology for Analog and Mixed Signal. As of this writing, the program is still being finalized, but more will be announced in the next few weeks, so check back on their website soon for updated information.Member EventsAnd finally, don’t forget to learn more about the offerings from and in support of the SOI ecosystem at our members’ events around the globe, including: GlobalFoundries – GTC | Samsung Foundry – SFF | ST – Technology Tour | Synopsys – SNUG | Cadence – CDNLive | Silvaco – SURGE | Arm – TechCon | NXP – Tech Days | Leti – Events | imec -Events |

If you’re going to Semicon West this year, be sure to attend the SOI Consortium’s workshop on how IoT is driving the SOI supply chain. There’s a great line-up of speakers – see the program below. IoT means many things to many people but everyone agrees it’s here and growing quickly. IoT, including machine learning and movement to the edge, is fueling innovation as the high compute and ultra-low energy requirements are pushing technology to deliver on these needs. The well-known characteristics defining IoT of “Sense”, “Compute”, and “Act” put additional burden on technology to full these requirements across a variety of use cases and environments without sacrificing reliability or quality. All the various forms of SOI technology from FD-SOI to High-Voltage to RF-SOI, are uniquely situated to deliver on the promise of today’s as well as tomorrow’s IoT roadmap. The supply chain for all forms of SOI technology is in place. This workshop will discuss the current and future solutions from a supply chain perspective.Speakers include experts from SOI Consortium members Applied Materials, NXP, GlobalFoundries and Soitec.Entitled The Internet of Things, Driver of the SOI Supply Chain, the workshop will take place at the Moscone Center South, Wednesday July 10th in Room 301. It will run from 1 pm until 4:30 pm. Anyone and everyone who is registered for Semicon West is welcome. Here is the sign-up page.It’s a great program: 1:00pm - Welcome by Semi1:10pm - IoT/AI/Edge Market – Using SOI Through-out, Jon Cheek, Senior Director, NXP1:35pm - The SOI Opportunity, Manish Hemkar, Director, Semiconductor Products Group, Applied Materials2:00pm - The Foundry IP Ecosystem, Jamie Schaeffer, Sr. Director, GlobalFoundries2:25pm - Engineered Substrates - Enabling the IoT Revolutions, Eunseok Park, Director, Emerging Technology in Strategic Marketing, Soitec 2:50pm - Enabling the SOI Era, Thomas Uhrmann, Head of Business Development, EVG3:15pm - Panel: The Internet of Things, Driver of the SOI Supply Chain, Moderator: Carlos Mazure, Chairman, SOI Industry Consortium. Panelists include:Manish Hemkar, Director, AMATYoshio Kitahara, President Managing Director, Kokusai EuropeThomas Uhrmann, Head of Business Development, EVGJon Cheek, Sr. Director, NXPThomas Piliszczuk, EVP Strategy, SoitecJon Kretzschmar, Manager of Product Sales Marketing, TEL America4:05pm - Closing remarks, Carlos Mazure, Chairman, SOI Industry Consortium4:20pm - EndThis is a great chance to learn more about SOI and the SOI Consortium. Don’t miss it!And while you’re at West, you should also check out a related event. SOI Consortium member Leti will be teaming up with Fraunhofer for a workshop entitled New Paradigms in Microelectronics–Providing R D for the 21st Century. That happens at the nearby W Hotel in San Francisco on Tuesday, July 9th at 5:00pm. Click here for more information on that.