ST

The chip design ecosystem finally has the book it’s been clamoring for: The Fourth Terminal - Benefits of Body-Biasing Techniques for FDSOI Circuits and Systems. [bctt tweet="The FD-SOI Chip Design Book: Yes, It’s Finally Here!" username="@soiconsortium"] The editors (who have also contributed chapters) are Andreia Cathelin, Sylvain Clerc and Thierry DiGilio, all world experts from STMicroelectronics. As Cathelin and Clerc note in the introduction: “The aim of this book is to introduce to the design community the straightforward design solutions in any modern FD-SOI planar CMOS technologies, by taking full advantage of body biasing techniques to efficiently modulate on the fly SoC solutions from high performance operation to energy efficiency mode. All design techniques are based on the classical pillar of regular planar CMOS devices. As the first fully industrial solution has been the 28nm FD-SOI CMOS technology from STMicroelectronics, all the design examples in this book have been demonstrated within this process integration frame.” [bctt tweet="The Fourth Terminal...taking full advantage of (FDSOI) body biasing techniques to efficiently modulate on the fly SoC solutions from high performance operation to energy efficiency mode" username="@soiconsortium"] The folks at ST were really the first to get into FD-SOI in a big way – in fact they’ve been at it for over two decades (!) so you’d be hard pressed to find experts at a company with deeper expertise. [caption id="attachment_29610" align="alignnone" width="535"] The Fourth Terminal team friends sporting Tour de Fourth Terminal t-shirts at ISSCC 2020. From left to right: MIT Prof. (and Series Editor for Springer's Integrated Circuits and Systems) Anantha Chandrakasan; Charles Glaser, Springer Editorial Director; Laurent Le Pailleur, ST; Andreia Cathelin, ST Fellow; Sylvain Clerc, ST; Stanford Prof. Boris Murmann (Photo courtesy Springer STMicroelectronics)[/caption] The Fourth Terminal is structured to cover three major areas: a technology overview (including body biasing for digital, analog and SRAM); a selection of circuits that illustrate body biasing in various fields; body bias deployment in mixed-signal and digital SoCs. The initial response has been tremendous. Editor Andreia Cathelin reports that posts she's made about it on LinkedIn were quickly viewed 10k times and more. Then came the book review by the eminent Stanford Professor Boris Murmann, who heralded its tour de force status in a clever turn of phrase: “With the help of a renowned international team of experts from industry and academia, the editors have distilled everything you need to know about FD-SOI circuit design into a 16-chapter "tour de fourth terminal". (Read his complete review here).[bctt tweet="Stanford Professor Boris Murmann calls this book a #Tour_de_Fourth_Terminal. #FDSOI #lowpower #chipdesign" username="@soiconsortium"] EETimes journalist Junko Yoshida blogged about it as Body Bias Gets Its Own Book (read that here), which generated lively discussions on LinkedIn (and underscored just how necessary this book is!). The Fourth Terminal - Benefits of Body-Biasing Techniques for FDSOI Circuits and Systems is part of the Springer Integrated Circuits Systems Series -- considered by many to be the most prestigious in the industry. Weighing in at 431 pages, The Fourth Terminal is available in both e-book and hardcover versions. See the Springer website to order this must-have addition to your library.

The SOI Consortium’s Japan Symposium this past fall covered a wide array of topics over two days. The first day was devoted to IP and products for RF and ultra-low-power (ULP) on SOI. The second day covered high voltage and photonics. It will take several posts to summarize all the presentations. In this post, we’ll cover presentations related to 5G. In the next posts we’ll cover IoT/ultra-low-power/automotive and photonics. (BTW, if your company is a member of the SOI Consortium, you can now access most of these presentations on our website.) The Japan SOI Symposium was organized for the 4th time at the Yokohama Landmark Tower (from which there was a fabulous view of Mount Fuji). It was a great success, with both days well attended. The event followed the day after (and in the same location as) Silvaco’s SURGE user event, so there were plenty of opportunities for synergy there. (Samsung Foundry talked about their partnership with Silvaco, for example, and their work together on RF and eMRAM on 28nm FD-SOI.) STMicroelectronics [caption id="attachment_27068" align="alignnone" width="589"] From “5G Deployment Driving RF and SOI Technology Opportunity” (Courtesy: ST SOI Consortium)[/caption] As noted in the ST presentation, 5G standards are getting a big push in the Asia-Pacific region, and by China in particular, which is leaping ahead especially in sub-6GHz. It’s a complex standard, noted John Carey, the company’s director of Digital RF for the A-P region, and it’s disruptive, demanding new silicon architectures and technologies. Next year’s premium phones, he said, will include over $30 in RF components, 40mm2 of which will be based on SOI. ST has been working on RF-SOI for over two decades, and offers a range of technologies and foundry services supported by three high-volume fabs. The key benefits with RF-SOI, he explained, stem from RF FEM integration of switches, LNAs and PAs. RF-SOI technologies are here now and are successful in the markets: ST has a long-term technology roadmap and is making continued strategic investments, he concluded. Toshiba [caption id="attachment_27069" align="alignnone" width="410"] From “RF-SOI Switch LNA for Mobile Applications” (Courtesy: Toshiba SOI Consortium)[/caption] Another long-time RF-SOI user is Toshiba, although this marked their first participation in a recent Consortium event. As Group Manager Kazuyuki Uchida talked about RF techology trends, there was lots of note- and picture-taking in the audience. He pointed out that the character and size of the switch LNA modules are particularly important in the move to 5G. They’ve been leveraging their TaRFSOI(tm) process, which he said achieves the industry's lowest insertion loss, for about a decade now. The latest version, TaRF11 will be launching in Q1 of 2020. TaRF10 integrated the LNA with the switch and control circuitry in a single chip. TaRF11 will feature performance improved by about 25%. Incize [caption id="attachment_27065" align="alignnone" width="405"] From “RF Characterization” (Courtesy: Incize and SOI Consortium)[/caption] During the Incize presentation, the company’s CEO Mostafa Emam affirmed that RF-SOI is a very good business opportunity. Incize works with the complete supply chain. For foundries and wafer suppliers, they measure harmonics and output with very high precision, which is especially critical for switches. For the wafer suppliers, it’s predictive. For the foundries, it’s measuring noise for models and PDKs. While RF may be an art, second tier foundries using Incize services are now able to compete with the first tier players, he noted. He sees trap-rich RF-SOI wafers as being especially important for 5G. GlobalFoundries [caption id="attachment_27064" align="alignnone" width="599"] From “RF Reliability for SOI CMOS Si-based Power Amplifier for 5G applications” (Courtesy: GlobalFoundries SOI Consortium)[/caption] The focus of the GlobalFoundries talk was reliability in RF processes. In 5G, you need technologies that are viable for both mmWave and sub-6GHz across handsets, wifi and automotive, noted Purushothaman Srinivasan (who goes by SP and is a senior member of the company’s technical staff). In SOI, you can stack FETs (which you can’t do in bulk) for PAs, which is a big advantage in mmWave. However, delivering scalable, linear, efficient and reliable RF power technology is more challenging than digital, and requires a holistic, collaborative approach that includes the foundry, the customers and the test equipment suppliers. GF has used its RelXpert simulation tool on aging simulations and lifetime predictions for both their 22FDX and 45RFSOI processes. They have observed good RF model-to-hardware correlation, and have built Safe Operating Maps that provide guidance to RF designs. This first-in-industry RF reliability evaluation provides “highly differentiated” solutions for GF. Silvaco [caption id="attachment_27066" align="alignnone" width="606"] From “RFSOI TCAD Solution” (Courtesy: Silvaco and SOI Consortium)[/caption] Silvaco is a leading EDA provider of software tools used for process and device development and for analog/mixed-signal, power IC and memory design. Their presentation began with a review of recent updates to their TCAD simulation framework, including the TCAD design flow, Victory ProcessTM simulation for speeding up 2D/3D process simulations, and Victory DeviceTM simulation. Under Silvaco’s DTCO – Design Technology Co-Optimization – semiconductor physics are connected to circuit design, recognizing that each technology has specific requirements that need to be taken into account at every stage of the flow. Applications Engineer Sun Tao then continued by showing useful TCAD simulations and analysis of SOI for RF applications. In trap-rich substrate simulations, for example, the Silvaco tools can predict the harmonic balance from the active device, device biasing and substrate, all of which can be co-optimized using Victory Process and Device. SITRI [caption id="attachment_27067" align="alignnone" width="305"] From “NB IoT FEM based on SOI” (Courtesy: SITRI SOI Consortium)[/caption] Shanghai Industrial μTechnology Research Institute – aka SITRI – is an international innovation center, focused on globally accelerating the innovation and commercialization of “More than Moore” technologies to power IoT. SITRI Director Wenwei Yang’s talk focused on their narrowband front-end module for IoT (NB IoT FEM). NB-IoT is especially meant to handle small amounts of data from remote places over long periods. There are a lot of players in this market, so taking a “good-enough” approach to performance wherein cost is primordial is key. SITRI’s low-cost NB-IoT FEM integrates everything on a single chip, including the power amplifier (PA) and integrated passive devices (IPD), so packaging costs are low. Putting it on SOI (either trap-rich or high-resistivity) gives them better isolation and simplifies integration. ~ ~ ~ Our next post will continue our coverage of the Japan Symposium. Note: 2019 marks a decade of SOI Consortium events – yes, our first one was in 2009! Because a lot of the presentations in the past were so forward-looking, many of them are still of great interest today. Currently the presentations from 2015 through to the beginning of 2019 are available freely to everyone – and are well worth perusing.

The 2019 International RF-SOI Workshop in Shanghai was packed to overflowing, with over 500 attendees, noted SOI Consortium Chairman Executive Director, Carlos Mazure. There were 16 presentations over the course of the day – every one of them excellent – so it will take two posts to cover them all. We covered Danni Song's compelling keynote in a previous post – see it here. In this post, we’ll cover the remaining keynotes and the morning session, which was dedicated to 5G deployment. In the next post, we’ll cover the afternoon sessions, which were dedicated to the China RF-SOI ecosystem, and the RF value chain. PDFs of the presentations are not yet posted, and then they will only be available to those whose companies belong to the SOI Consortium. But we’ve summarized them all for you, so read on! KeynotespSemi: 30 Years of RF-SOI – Past, Present and Future (Jim Cable, Chairman and CTO, pSemi (a Murata company))The keynote by RF-SOI legend Jim Cable chronicled his always-innovating journey from digital to RF via sapphire then SOI. (Cable's work was recognized in an award that evening.) His original vision back in the early days was for a RF front-end module (FEM) + CMOS transceiver. At the time, doing it on sapphire (an insulator) rather than bulk made it much easier, as sapphire eliminated the non-linear capacitances. That was the beginning of their UltraCMOS technology, and though it did very well, sapphire was only available in 6” wafers. So pSemi (or Peregrine, as it was known at the time), engaged with Soitec on bonded-SOS. “It was a killer technology, and the marketshare we won was staggering,” he recalled, and helped convince Soitec RF-SOI was worth looking at. The goal is to handle high RF power levels: you can use SOI to handle higher voltages than you'd think were possible. They added an invention they called HaRP, that dealt with accumulated charges and enabled them to hit the linearity specs on silicon. With that, he explained, they came to completely dominate the switch industry. UltraCMOS evolved, getting 60% smaller with 20x better linearity – but now of course you have 50 switches, not six. He heralded the great partnership they have with GlobalFoundries, noting, “We were pioneers in this field.” In fact, in 2017 they were in the top 10 for IP generation in semiconductor manufacturing. Now comes mmWave, where he says, “We see everything we believed and more.” They're currently sampling an 8-channel mmWave RFFE (RF Front End). Soitec: 5G-on-Insulator: the 5th Gear In Mobile Radio (Michael Reiha, GM, Soitec)Michael Reiha's talk centered on how SOI wafer-leader Soitec is positioning itself on 5G, which, he explained, demands a wider portfolio. Soitec looked at what they could do to make 5G ready for sub-6GHz. Massive MIMO (mMIMO) is an efficient technique to improve throughput. With SOI, you can reduce the power it takes, making it a good choice for urban environments. RF-SOI is a candidate for power amplifiers, and FD-SOI is enabling more users to be added. The concept of network sharing is an opportunity for compact, low-cost filters that can meet the requirements with simpler, lower-cost, higher-efficiency filters. That's why they've just announced a new substrate called piezo-on-insulator (POI). However, total cost-of-ownership is not just how much a product costs, but how much it costs to run it.. Currently, RF and mechanics dominate the bill-of-materials, so you need to decrease the number of RF FEM components and get savings scaled with the array size. The main challenge of SOI is in efficiency, but the advantage is that it can be used in integrating digital with analog sensing and RF. Then you can use AI sensing for tracking temperature, for example, and control for 5G optimization. In short, with RF-SOI, you apply AI to the radio head, especially for things like mMIMO. And btw, he added, Soitec currently has capacity of two million wafers per year. SESSION 1 – 5G DeploymentYole: 5G is ON. Which Impact for RFSOI Technologies? (Cederic Malaquin, Technology Market Analyst)There are over a thousand 5G networks available today worldwide, said Cederic Malaquin. Adoption is accelerating, driven by 5G cloud gaming, AR/VR/XR, 5G multi-video calling and stadiums. However, carriers need better ROI. 5G should address this so that customers are better served. MIMO and carrier aggregation (CA) are the main techniques supporting network capacity and coverage improvements. 5G NR will bring more spectrum. With each generation putting more content in phones, new spectrum is happening in sub6 and mmWave. The impact of 5G on mobile phones is huge in terms of both content and complexity. Some phonemakers (like Apple and Samsung) are moving towards increased integration. Others (like Huawei) are going more for discretes. Yole sees tuners, switches / LNA as addressable by RF-SOI, but they are less convinced about power amplifiers. They also see SiP (system in package) as prevailing over integration. The 5G mobile and base station markets will really build up in 2022-25. RF-SOI will remain the mainstream technology for switches and antenna tuners through at least 2025: they don't see anything else replacing it. There is still increasing demand for 8” wafers. 12” wafers growth comes from integrated switch/LNAs, which comes from the Tier 1's. In the front-end space, Murata leads in dollars by far, followed by Skyworks and others. Though mmWave is not yet clear, there are opportunities for RF-SOI. ST: 5G Deployment Driving RF and SOI Technology Opportunity (Laura Formenti, Sr. Director)STMicroelectronics has a long history in RF-SOI, noted Laura Formenti, dating back to 2000 when they started collaborating with Soitec and Leti. An IDM, ST also offers foundry services. For 5G, their foundry offering includes H9SOIFEM, C65SOIFEM and SOI mmW for high-performance analog, dedicated RF processes for RF switches, LNA, PA plus RFFEM. Then they have FD-SOI for RF, mixed signal and digital integration. From antennas to transceivers there's an opportunity for full integration. For infrastructure, it depends on the customer preferences. 12” C65SOIFEM was introduced in 2019, and 12” SOIMMW will be introduced in 2020. Both their fabs at Crolles and Rousset, France, are in production. H9SOIFEM is for 4G and 5G sub-6GHz RF FEMs, enabling monolithic integration of the PA, LNA and switches, which is especially good for wifi. The C65SOIFEM is high-performance. Panel: 5G Deployment in China, Jeffrey Wang, CEO, Simgui Technology, moderatorWith Danni Song (China Mobile), Jim Cable (pSemi), Peter Rabbeni (GF), YangYang Pen (SmarterMicro), Paul Hurwitz (TJ), Michael Reiha (Soitec)Q: Why sub-6GHz and not mmWave?Danni Song said its a question of available spectrum. In sub-6, you get the same level of coverage with fewer base stations; also, sub-6 is much more mature. When will mmWave be ready? It depends. In the US, yes, but in China the spectrum allocation for mmWave has not yet been done. So it's a wait and see for the industry to be ready. Peter Rabbeni agreed, adding that in the US sub-6 is crowded and conflicts with military bands. Paul Hurwitz added that mmWave is for fixed wireless access. Michael Reiha added that mmWave has advanced a lot even in the last few months (Verizon in Washington, DC, for example), so there is momentum.Q: Does China lead in the sub-6GHz opportunity?Jim Cable said that at pSemi they have two business models: mobile and infrastructure. He sees massive MIMO in base stations as huge (though in mobile their role is more supporting Murata). Peter Rabbeni added that they're working with innovative partners in China, and that GF also offers skills in services and packaging. Yangyang Peng sees big opportunites with 5G for SmarterMicro and China. Paul Hurwitz has seen an increase in the capabilities of RF companies in China, and that the market in China moves faster than elsewhere. Michael Reiha sees China as strategic, and because there is central deployment, they can plan with the right partners.Q: Data usage will be huge – what will it cost to individual users?Danni Song said 5G phones will be expensive, but consumers want them, so we need to bring down costs and increase performance – but what about power consumption? Power needs to come down, maybe levering things like sleep mode more. For 3G 4G, she noted, they had lots of time. People are pushing hard for 5G, but there's a need for patience. Yangyang Peng said he didn't want to pay more than for 4G. In summary, Jim Cable noted that mmWave will demand huge amounts of silicon, to which Paul Hurwitz agreed, and Michael Reiha said Soitec will be ready. Everybody agreed that 3D packaging would be very important, especially for mmWave. And that's it for our coverage of the morning. Next up we'll cover the presentations given during the afternoon.

The SOI Consortium’s next annual event in Japan takes place on the 30th and 31st of October in Yokohama. Both days of the SOI Design Symposium will take place in the Yokohama Landmark Tower. The event is complimentary, however pre-registration is required – just follow the link here. Rest assured that in addition to the excellent program, the agenda provides ample time for networking.Wednesday, October 30 -- RF and ULP on SOI: IP ProductsOctober 30th showcases industry leaders with ULP IoT applications by NXP, and opportunities in the RF space by STMicroelectronics and Toshiba. The strong development of the design and EDA platform is discussed by ARM, Silvaco, Attopsemi and Dolphin. GlobalFoundries will present on their predictive reliability platform for RF, while Incize discusses the criticality of RF characterization and Secure-IC addresses to important topic of IC security.The day finishes with an overview of the SOI ecosystem by the SOI Industry Consortium. (See the full agenda here.)Thursday, October 31st -- SOI Enabling Photonics and Power InnovationWe start the day with two keynotes on High Voltage SOI electronics for automotive by NXP followed by Soitec on engineered substrate solutions. The Silvaco overview on RF modeling and SOI NB-IoT by SITRI promises to be very interesting. Then the day will offer a deep dive into Photonics touching applications with Cisco, foundry offerings with TowerJazz and GlobalFoundries, EDA with Cadence, and advanced SOI Photonic solutions by Leti-CEA. An ecosystem and market outlook by Soitec wraps-up the day. (See the full agenda here.)We look forward to seeing you there!

The 45th (yes!) IEEE SOI Conference takes place 14-17 October 2019 in San Jose. Now called S3S –since it also covers 3D and subthreshold – it’s a networking event par excellence: a unique opportunity to meet firsthand the movers and shakers in the SOI ecosystem and the giants of R D. As always, it has a strong technical program you won’t want to miss. Plus this year there’s a full-day short course dedicated to FD-SOI design, and half-day tutorial on RF design. Get all the details and registration info at http://s3sconference.org/.The SOI Consortium’s own Executive Co-director Jon Cheek of NXP is one of the keynoters. In fact the consortium membership is extremely present at this event, with over half our member organizations having a hand in it. There’s a plenary talk by GF’s CTO/VP Subramani Kengeri, keynotes by ST Fellow Andreia Cathelin and NXP Fellow Rob Cosaro, and invited talks from Arm, Samsung and Dolphin Design, for example. And this year’s General Chair is Incize CEO Mostafa Emam. Focus Sessions #12 and 13 are all about FDSOI Platforms and Products, with invited speakers from Renesas, NXP, ST, ARM, GF, Huali and Dolphin Design, while focus Session #2 is all about RF-SOI. Here’s the agenda for the FD-SOI Design short course (which takes place on Thursday, 17 October):Short Course Opening and Welcome Philippe Flatresse, Business Development Marketing Director, Dolphin DesignGLOBALFOUNDRIES 22FDXTM Technology and Body Bias Compensation to Enable New Design Optimization Strategies Joerg Winkler, Fellow Design Engineer, GLOBALFOUNDRIESEmbedded Flash Memory Technologies and Applications in Advanced Nodes Memories Koji Nii, Vice President, Global Marketing Sales, Floadia CorporationEnabling the Adaptive Body Bias in Modern IoT Applications Vincent Huard, CTO, Dolphin DesignSoC Design Realization with Adaptive Body Bias Kripa Venkatachalam, IC Design Practice Director, Mentor Graphics Didier Roland, Application Engineers Manager, Mentor GraphicsAnalog Design Techniques for Microprocessors in FD-SOI: Power-Management, PVT Monitoring and Data Conversion Edevaldo Pereira Da Silva Junior, Senior Principal Engineer, NXP Semiconductors MPU/MCU R DLow Power Solutions for SoC Architectures Antonio Pullini, Senior Hardware Designer, GreenWaves TechnologiesSOI to RF Sidina Wane, CEO, eV-technologiesIf you know the way to San Jose, you'll want to be at S3S 2019, for sure!

ASN had a chance to talk to François Brunier of Soitec, who’s leading this important project.Advanced Substrate News (ASN): Can you tell us briefly about OCEAN12?Francois Brunier (FB): OCEAN12 stands for Opportunity to Carry European Autonomous driviNg further with FD-SOI technology up to the 12nm node.Francois Brunier, Partnership Program Manager, Soitec.OCEAN12 deals with “Ultra-low power computing solutions for automotive and aeronautics using all the range of FDSOI technologies”. This project with a budget of 103M€ brings together 27 partners from 7 different countries. The project received the ECSEL JU* label under the 2017 call. ECSEL is an EU-driven public-private partnership enabling the co-financing of innovation in electronic components and systems both by Member States and the European Union.ASN: Why is this project needed?FB: As of today a car has around 500 million transistors. These electronic components represent already an important vector of valorization and differentiation for the automotive industry and for the consumer. The increased autonomy of the vehicles will require a very strong build-up of computational capacities. 50 to 100 times more transistors could be required for a level 5 (fully autonomous car). Following this trend an autonomous car will require power consumption equivalent to 50 to 100 computers running continuously (without taking into account the car propulsion).The OCEAN12 partners.The power consumption of these components becomes a key element in the choice of technologies. We believe that our technologies on SOI present the best assets to meet this challenge.The FD-SOI substrates, technologies and designs developed in OCEAN12 offer a palate of different solutions to this challenge: increased performance for data processing (including Artificial Intelligence); much higher energetic efficiency; and smaller form factors to fit in embedded systems like autonomous cars with higher integration and reliability, and enabling safe connectivity.The OCEAN12 project will demonstrate that SOI technologies are able to meet these challenges through relevant demonstrators in the targeted fields.ASN: What are the project goals?FB: OCEAN12 will bring concrete solutions to the main challenges of smart connectivity and low power consumption in the automotive industry.As such, OCEAN12 will build awareness around the key enabling technologies in substrate development, transistor behavior, and the design and fabrication of integrated circuits up to the system and end-user application levels. We will show that the technology is advantageous for automotive and aerospace applications, which are strategic sectors for Europe. Having the whole supply chain in Europe means having trusted and secured components made in Europe.The OCEAN12 project goals stand on three pillars:First: Confirming the technology foundation. Ocean12 puts the FD-SOI substrate and device developers in direct contact with the full value chain of suppliers and end users. This gives the entire ecosystem visibility into current and future needs, and ensures that substrate and device solutions are both technically feasible and correctly aligned with actual system requirements.Second: Creating concrete, innovative demonstrators in automotive (Audi, Bosch) and aeronautics (Airbus, Thales). These demonstrators are a first step in defining the context and environment to prove the advantages of these technologies in real application cases, showing they are useful and as such prefigure a final system and a potential future product roadmap. Demonstrators should be as close as possible to the final application.Third: Broadening the design ecosystem, with the big companies, the small- and medium-sized companies (SMEs) and the research organizations (universities, RTOs). We have a critical mass of 16 design ecosystem partners focusing their efforts on FD-SOI. The project leverages that dynamic FD-SOI design ecosystem for IC product migration to FD-SOI and the creation of new IP. Inventing the future components in Europe is also key.ASN: Can you tell us more about the demonstrators? When will we see them?FB: There are four demonstrators. All these demonstrators will be delivered by the end of the project in 2021:Always-on wake-up systems (Audi, Bosch, Leti). With such a system we can imagine an application to monitor our car when it is parked in a parking lot for a long time. The sensors would remain aware of everything that goes on around the car. Based on sensor observations, the car can make decisions on further actions to take. This can be used in many future car applications like intrusion detection or vehicle access systems. But you will not have to worry about battery drain: even though all the sensors are always on, they go right back into a very low-power sleep mode thanks to FD-SOI technology.mm-Wave integrated radar SOCs (Bosch and Audi), which will benefit from all the innovations of FD-SOI thanks to its low consumption properties, but also the optimization of the sensors. The performance gain is made over the entire system with adaptations between analog and logic.High-performance video processor for aeronautics. (Airbus, Thales, Kalray). Kalray, a French SME working on Massively Parallel Processor Arrays (MPPA) aims to demonstrate an ultra-low power, low-cost, high-performance neural processor on FD-SOI technology. This demonstrator would be key for Airbus and drones with high-performance, low-power cameras. Airbus and Audi have partnered on air and ground mobility services.Microcontroller plug-and-play board. This demonstrator lead by ST will allow for the development of new solutions in the domain of GNSS/GPS.ASN: Can you tell us more about the partners?FB: The OCEAN12 consortium of 27 partners involves 8 large groups, 9 SMEs and 10 universities/RTOs. These partners come from 7 different European countries.The eight large groups include: Soitec, the world’s leading provider of FD-SOI substrates; EVG, a leading global equipment supplier; GlobalFoundries and STMicroelectronics, the two major European FD-SOI foundries; and Bosch, as a Tier 1 automotive supplier. At the top of the value chain, high-end European automotive manufacturer Audi, the avionics industrial giant Airbus, and Thales for security issues, will develop product demonstrations.Ten highest-level research institutes support the industrial consortium. They include CEA-Leti (FR), Fraunhofer(GE), IMS (FR), INP Grenoble (FR), TU Dresden (GE), U. Paderborn (GE), Bundeswehr U. Munich (GE), Eberhard Karls U. Tübingen (GE), Instituto de Telecomunicações (PT), and Warsaw UT (PL). They increase the competitiveness through technological innovation and transfer of technical know-how while gaining new expertise working with global leaders.In addition, OCEAN 12 has a very strong SME consortium covering the supply chain in the fields of new equipment, IP, system integration and fabless companies. They include: IBS, UnitySC (HSEB), MunEDA, Kalray, AED Engineering, ISD, EVOTEL, M3 Systems and Design Reuse.All these partners have longstanding experience of cooperation in various national and international frameworks and are specialists in their fields of activity. Their contributions are essential for the success of the project.ASN: What is the timetable?The OCEAN12 kick-off event at Soitec’s headquarters near Grenoble.FB: The project started on April 1st 2018. The kick off with all the partners was held at Soitec on 29 September 2018. It was a great success. The project runs through December 2021, by which point everything has to be demonstrated.ASN: Can you clarify the funding structure?FB: The budget is about €103.6M. If the project succeeds, we get European Commission funding. In that case, just over 20% of the eligible cost – about €23M – is subsidized at the European level. The seven countries with companies or organizations participating in the project will then roughly match the European subsidies, contributing about €27M. These ECSEL-type public-private projects are a tried and true model in Europe, maximizing synergy across ecosystems. To conclude, in the name of the consortium I’d like to thank the ECSEL JU, the European Commission and our National Funding Agencies from France (DGE), Germany, Portugal, Greece, Spain, Austria and Poland. Such a project would not exist without them.______*ECSEL JU: Electronic Components and Systems for European Leadership Joint Undertaking

2019 will be a busy fall for the SOI Consortium and our members.First off are the SOI Consortium events in Shanghai and Tokyo, which are very popular indeed. We now have the dates locations locked in, so you’ll want to mark your calendars:Shanghai: 16 17 September 2019, FD-SOI Forum / RF-SOI Workshop. Both days will be held at the Pudong Shangri-La Hotel in Shanghai. The first day will focus on FD-SOI. The second day is all about 5G and RF-SOI. These are huge events – to get an idea of the magnitude, you can read our coverage of the 2018 event. Tokyo: 30 31 October 2019, Japan SOI Design Workshops. This year both days of workshops will take place in the Yokohama Landmark tower. The first day will be devoted to FD-SOI; the second day turns to More-Than-Moore – especially photonics and MEMS. Last year’s workshops were packed with excellent presentations and panel discussions, which we covered here. The SOI Consortium and members will also be giving talks at Semicon Europa, which is being held 13 – 15 November 2019 in Munich, Germany. The programs are currently being finalized. As soon as they’re ready, we’ll be sure to let you know so you can register and/or share the news with your colleagues and clients. But in the meantime, make sure you save the dates.Would you like to check out the presentations given at Consortium events in previous years? If you hover your cursor over the Events tab at the top of our home page, you’ll get a drop-down menu of events for the last five years (we’re working on adding more – we’ve been doing these events for over a decade!). Click through to any past event and you’ll land on a page where you can download most of the presentations that were given there. Of if you’re looking for past presentations given by any particular company, use the search engine at the bottom of any page on our website. S3SYou’ll also find many of our members at the IEEE/EDS S3S Conference in San Jose, CA, October 14 – 19th. S3S (formerly known as The SOI Conference) has been running in various forms for over 30 years. They always have an excellent line-up of speakers, plus it’s a great opportunity for networking with researchers from across the worldwide SOI ecosystem. BTW, while the deadline for general paper selection has already closed, papers of exceptional merit are currently being accepted for their Late News Sessions. See the 2019 Call for Papers for more information – those Late News papers need to be received by 23 August 2019 for consideration. Also, IEEE S3S Conference will once again host a full-day short course and a half day tutorial. These are very popular. The short course this year will be on SOI Design and Technology for Analog and Mixed Signal. As of this writing, the program is still being finalized, but more will be announced in the next few weeks, so check back on their website soon for updated information.Member EventsAnd finally, don’t forget to learn more about the offerings from and in support of the SOI ecosystem at our members’ events around the globe, including: GlobalFoundries – GTC | Samsung Foundry – SFF | ST – Technology Tour | Synopsys – SNUG | Cadence – CDNLive | Silvaco – SURGE | Arm – TechCon | NXP – Tech Days | Leti – Events | imec -Events |

The SOI Consortium and member companies had a significant presence at two important events in China recently: the World Semiconductor Congress (WCS) in Nanjing and the SOI Academy, including an FD-SOI Training Day in Shanghai. Nanjing is especially known as a leading RF chip design hub in China, but WCS went well beyond RF. The three-day 2019 event was held at the Nanjing International Expo Center. It attracted over 30,000 visitors, 5000 of whom attended the various summit forums. Presenting at WCS '19 in Nanjing (clockwise from top left): Wayne Dai, CEO/Founder, VeriSilicon; Carlos Mazure, Executive Director, SOI Consortium; Giorgio Cesana, Director, STMicroelectronics; Christophe Tretz, Design Expert, SOI Consortium. (Photos courtesy: WCS)The SOI Consortium organized the SOI Forum, which was part of an afternoon Innovation Summit. Presentations were given by members of the SOI Consortium team, and by leaders from our membership, including Simgui, NXP, Incize, ST, IBM, Cadence and Xpeedic. Some of those presentations are now available from our website -- click here to get them.Earlier in the day, SOI Consortium member VeriSilicon participated in a morning session on AI and IoT Wireless Communications. They presented their low-power Bluetooth design platform for GlobalFoundries 22FDX, and CEO Wayne Dai moderated a lively round-table discussion.Following hard on the heels of the Nanjing event, the SOI Consortium team and members headed to Shanghai for the SOI Academy 2019, hosted for the second year in a row by member SIMIT (Shanghai Institute of Microsystem and IT under the Chinese Academy of Sciences). The two-day event attracted more than 250 professionals from more than 100 domestic and foreign IC companies and research institutes. Keynotes by SOI Consortium Executive Director Carlos Mazure, SITRI CEO Mark Ding and Jean-Eric Michallet, Head of the Microelectronics Components Department at Leti and bizdev director for the SOI Consortium focused on the SOI ecosystem. The SITRI and Leti talks also gave updates on their research and industrialization alliance. Further talks were given by leaders from Soitec, GlobalFoundries, VeriSilicon, IBM and Xpeedic. These addressed the growing FD-SOI ecosystem, applications in automotive electronics, 22 nm and 10 nm FD-SOI devices, advanced SOI substrate technology, China’s FD-SOI development, the FD-SOI manufacturing process, product design, EDA tools and all aspects of industry’s software and modeling value chain.Several speakers noted that more and more local Chinese customers are actively adopting FD-SOI for low-power, high-performance chips. SOI Academy, Shanghai, 2019, FD-SOI Training Day attendees.(Photo credit: SIMIT)The second day was devoted to hands-on professional training, given by experts from Leti using an actual PDK and punctuated by in-depth discussions. This helped the IC designers to fully understand the advantages and flexibility of FD-SOI in low-power logic, analog/mixed-signal and RF. All in all, “It was a great success,” concluded Jean-Eric MICHALLET, Head of the Microelectronics Components Department at Leti and bizdev director for the SOI Consortium. Plans for the next SOI Academy are already underway, with plans to extend the topics to include more on photonics, RF, power and MEMS.

Why FD-SOI? What can you do with it that you couldn’t do before? That was the big question from IHS Markit’s Matthew Short that kicked off the first panel discussion at the SOI Consortium’s Silicon Valley Symposium. And there were some great answers.VeriSilicon, Analog Bits and Silicon Catalyst were among the consortium members with stands at the SOI Symposium, Silicon Valley 2019.Here in this final part of our coverage of the event, we’ll detail who said what in the two panel discussions, as well as the presentations by Leti, Intento Design the SOI Consortium’s IP/EDA roundup.If you missed the previous two installments of our coverage, you can catch up on the rest of the presentations in part 1 (NXP, Samsung more) here and part 2 here (Synaptics, GlobalFoundries more). Almost all of the presentations are now freely available under "events" on the consortium website - or just click here to get them.How FD-SOI Changes What You Can DoThe presentation by Matthew Short, Sr. Director of IoT Technology at IHS Markit, was not specific to SOI, but it sure did lay out out the market opportunities. Entitled IoT, 5G, ADAS and AI Market, it’s available on our website. Matt spent most of his career in chip design at NXP/Freescale, so he really has an engineer’s perspective on where this all is going. At IHS Markit, they define IoT as anything with an IP address. Over the past year more than 10 billion devices were shipped, and there were more “things” than cellular handsets, so the world has really changed. He outlined the growth drivers, suggested that 5G won’t be a “wow” thing for consumers, and noted there is a lot of debate raging regarding how smart sensors should be (the Tier 1’s want smart).He was then joined on the stage by the participants in the first panel discussion, which looked at product and application drivers. That included: NXP Fellow Rob Cosaro; Tim Dry, Director of Edge Endpoints Marketing at Samsung Foundry; ST biz dev director Roger Forchhammer; CoreAVI biz dev VP Lee Melatti; Nokia VP Michael Reiha; and Analog Bits EVP Mahesh Tirupattur.First Short asked why customers wanted more integrated solutions. For CoreAvi, it’s about safety, for ST in automotive it’s about security, for Analog Bits, it’s about integrating more analog, for Nokia it’s just a necessity.Then he asked Why FD-SOI? What can you do that you couldn’t do before? For ST, which is doing MCUs for automotive, it’s about energy efficiency, speed, the density of non-volatile memory and the robustness of the technology. For NXP, it’s back biasing, low voltage and power numbers never seen before. “FD-SOI really makes a difference in the products we can bring to market,” said Cosaro. For CoreAVI, it’s the long-term power impact. And for Analog Bits, “Customers see huge benefits,” said Tirupattur, for cost sensitive applications. He has customers selling their technology in high volumes in FD-SOI. What about edge vs. cloud? For Nokia, it’s monolithic integration for best-in-class RF, advanced memory, biasing and voltage regulation adding a layer of intelligence. Samsung sees edge as distributed cloud, and CoreAVI sees safety in the edge, because you can’t completely rely on the cloud.Where are the weak points in the FD-SOI ecosystem? For Samsung, more people need to use back biasing. “People need to use the knobs,” said Dry. For Analog Bits, the next step is innovation around back biasing, as many in logic don’t understand the benefits, so the ecosystem needs to promote the value proposition. ST suggests that with more products out there, customers will see the benefits. NXP did “a lot of the heavy lifting” at 28nm – now you need more people using these nodes, not just the cellphone nodes.How will the architecture change? For NXP, it’s all about memory bandwidth. For Samsung, it’s the promise of analog and interconnect. Nokia sees the back-end and heterogeneous integration with FD-SOI and RF enablement. Analog Bits’ Tirupattur said he’s pushing his engineers for even lower power in a still smaller form factor, noting that most analog engineers had been more focused on performance than power, but now that’s changed. For ST, it’s AI/ML throughout automotive, and FD-SOI is beneficial there.Leti the Connected Car Leti's slide 27, SOI Symposium, Silicon Valley 2019Research giant Leti’s presentation was entitled Applications Around the Connected Car. 85% of Leti’s €315M budget comes from R D contracts with its 350 industrial partners. Truly a driving force in FD-SOI, Leti is involved in a dizzying array of projects. For the connected car, they cover (much of it on SOI): high precision smart sensing, embedded processing fusion, new computing paradigms and deep learning, ultra-low power computing nodes framework, ultra-low power connectivity for IoT, energy management and scavenging, and security. They do vision at the edge, 3D technology for smart imagers, and ways to dramatically reduce power. They’ve got a Qbits platform on FD-SOI for AI at the edge, a super low power neural network accelerator, and ULP connectivity. Check out the presentation for lots of details.EDA/IP OverviewSlide 9 from SOI EDA/IP Overview.SOI Consortium Executive Co-Director Jon Cheek gave a quick round-up presentation aggregating various IP and EDA offerings entitled , SOI EDA/IP Overview. It is taken from recent member presentations including Cadence, Silvaco, VeriSilicon, Synopsys and GlobalFoundries, giving you an idea of how dynamic the ecosystem has become.Automating Analog While the logic side of the design equation has long had robust automation tools, some consider the analog side as sort of black magic. New consortium member Intento Design aims to fix that. Here at ASN we covered their work with ST briefly a few months ago here. At the SOI Symposium, the company’s CEO Dr. Ramy ISKANDER presented their solution in ID-XploreTM: A Disruptive EDA for Emerging FDSOI Applications. Intento, a partner in GlobalFoundries FDXcelerator program, has cognitive software for first-time right analog design. It determines the appropriate static and dynamic body biasing ranges to meet PVTB (Process/Voltage/Temperature/Body Bias), and is fully integrated into the Cadence Environment. They produced multiple correct-by-construction FD-SOI designs, and the total time spent to generate eight candidates FD-SOI designs took less than a day. The Tools Are in the BoxThe last panel discussion, entitled Are the Tools in the Box? was moderated by the Consortium’s Jon Cheek. Participants included: VeriSilicon SVP David Jarmon; Arm PDG Marketing VP Kelvin Low; NXP’s Stefano Pietri, Technical Director of the company’s Microcontrollers Analog Design Team; Jamie Schaeffer, who’s GF’s Sr. Product Offering Manager for 22FDX and 12FDX; and Cadence Strategic Alliances Director Jonathan Smith. 2nd panel discussion, SOI Symposium, Silicon Valley 2019Yes, the tools are in the box. Smith of Cadence said they’re providing them, and NXP’s Pietro said that they’re very well positioned in his specialty, analog. VeriSilicon has IP, and anything they don’t have in house they’ll license. So why be afraid of body biasing? NXP has proof by example – they see such huge cost advantages that they try to leverage it as much as possible. GF’s doing training, since each area (automotive, IoT, etc.) has different needs. Some VeriSilicon customers already see such substantial benefits from FD-SOI that they’re not bothering to do biasing. Cadence points out that the Arm POP announcement is huge, and Arm’s Low wondered if the SOI Consortium could do an IP portal? “Our sales departments need to explain the advantages to our customers!” said NXP’s Pietro.From the audience, NXP VP longtime FD-SOI proponent Ron Martino (who, btw, wrote some great articles for ASN when they first got into FD-SOI – read them here), asked why designers think FD-SOI means a lot of corners? How do we convince the industry that FD-SOI simplifies design? Cadence is working with GF, responded Smith, and will have some big new at Arm’s TechCon this fall. “We need more training and marketing to show it’s not scary," he added. For GF, the corners don’t get more complicated, and they’re working with Dolphin Integration on getting them covered early in the planning. Ease of access to IP will help, per Arm. And in a great concluding remark, VeriSilicon’s Jarmon said, “The craft is being automated. The more we work together, the greater success of FD-SOI.”