semiconductor design

Electronic Design Automation (EDA) is essential for the entire semiconductor design-to-manufacturing process. EDA tools streamline the design process, speed up development cycles, and ensure higher precision in chip design. Accellera Systems Initiative, an independent standards body, focuses on standards for system-level design, modeling and verification used extensively in the EDA ecosystem. These standards facilitate industry-wide collaboration and accelerate innovation, working closely with many members of the Electronic System Design (ESD) Alliance.Bob Smith, Executive Director of the ESD Alliance, recently talked with Lu Dai, Senior Director of Technical Standards at Qualcomm and Chair of Accellera Systems Initiative about Accellera’s new and future standards, and its successful global Design Verification Conference (DVCon) events.Smith: What’s new in Accellera’s standards effort since we last spoke?Dai: We are working on two new initiatives. The first and biggest initiative is our recently formed Federated Simulation User Group. Our members requested an end-to-end simulation environment or models that can be plugged into a system-level simulation environment. This challenge triggered industry-wide discussions among Qualcomm, NXP and many other semiconductor companies, especially those from Europe tied to auto and avionics industries.The need for this new standard effort is being driven by industries such as automotive where tiny microcontroller chips are traditionally used. The automotive industry has some existing simulation standards that include physical devices. With autonomous vehicles, systems on chips (SoCs) are replacing microcontrollers and handling system-level features that require rigorous system-level simulation. The user group is tasked with reviewing current automotive industry simulators and discovering how our traditional register transfer level (RTL) code- or emulation-based simulations could work with them via an interface.This effort has attracted new companies outside of the traditional EDA world. Ford, for example, is now an Accellera member and has a seat on our board. It’s exciting to see this collaboration.Functional safety is another initiative that we started a few years ago, also driven by the advancements in autonomous vehicles. Accellera’s focus is to define functional safety as a format that can be carried through the design stages from intellectual property (IP) to SoC, and from front-end design to back-end. Across the different stages of design and verification, an engineer can then confirm that the functional safety goal is maintained. We’ve published resources including whitepapers and are currently working on developing the language format. Smith: Where do you see Accellera’s next standards efforts?Dai: We have a mixed-signal standard coming out soon. It adds a mixed-signal interface to the SystemVerilog standard, currently under IEEE management because Accellera donated it to IEEE.A common question we’re asked is, “What are you doing with AI?” Accellera is a heavily EDA-centric standards body, and EDA tools are increasingly incorporating AI. AI consumes and outputs large amounts of data. A challenge is how to ensure the AI work output from one vendor’s EDA tool can propagate to another EDA tool. Accellera may look at defining an AI data format for EDA. It comes with a unique challenge because AI data is highly proprietary, both from the vendor’s and customer’s perspectives, so a robust security solution is needed. We may need to consider an interface standard, because companies may not be willing to share data, even with other groups that are in the same company. among their partners. They might need to hide the data and have a special interface to extract the data that they are willing to share. Accellera could investigate how to make AI deployment cross-vendor while allowing vendors and customers to protect their IP. Another area for potential new standards is around supply chain security challenges. This is a global issue driven in part by the COVID experience and geopolitical concerns. One possible approach is to use tagging. When a chip comes out of the fab, it would have a tag designating where it was designed and manufactured, and where the tooling is from. The tag would also include data about the regions or countries the design traveled through during the entire flow from design to manufacturing. Smith: Is Accellera looking into any standards or addressing any open-source design and verification flows?Lu: Accellera has been in the open-source domain for quite some time. Accellera has a language reference manual, user guides and reference implementations. Because many Accellera standards are related to language, we often work on libraries when a new language comes out and reference implementations to help our community deploy that standard. Reference implementation libraries are open source, as is our SystemC material. We have an active open-source SystemC community.Smith: I hear that the DVCon conferences are expanding globally. What’s driving that?Dai: Engineers enjoy attending conferences in person where they can reconnect with peers, build new connections and foster collaboration. We have regional DVCon events to bring information to our community and make Accellera more accessible to them. We now host several DVCon conferences in North America, Europe and Asia. Our next DVCon will be held in San Jose, Calif., from Feb. 24-27.Smith: How can readers of this blog post get more information about Accellera?Dai: For up-to-date information about Accellera’s activities, please visit our website: https://accellera.org/. Lu Dai is Senior Director of Technical Standards at Qualcomm and is a leader in semiconductor standards and industry organizations including Accellera. Dai holds a Master of Science degree in Electrical Engineering from Cornell, and a Bachelor of Science degree in Electrical Engineering and Computer Science from UC Berkeley.Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community.

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In the span of a few short months earlier this year, Mentor Graphics became Siemens EDA and introduced a suite of integrated hardware-assisted verification tools, the first product launch under the new Siemens EDA brand. Jean-Marie Brunet, senior director of marketing, product management and product engineering at Siemens EDA, orchestrated the launch and connected with me for a discussion about the chip design verification space. As he pointed out, verification and validation of systems is a fast-growing and important market segment to the electronic system design ecosystem. Smith: What trends do you see in chip design? What is driving these trends? Brunet: Chip verification costs continue to grow faster than design costs because of factors such as increasing design complexity, rising computing power, surging I/O traffic activity, increasing energy consumption and the widespread use of peripherals. These dynamics are being driven by new data center networking, communications/5G, autonomous driving, artificial intelligence (AI) and machine learning (ML), and storage applications. These trends also indicate the need for more powerful verification tools and expanded verification objectives that include power and performance analysis. Hardware-assisted verification tools are perfect for meeting these demands. Smith: Chip design verification consumes the most time in a project cycle. Why is this so? Brunet: The verification of designs reaching multi-billion gates and supported by voluminous software stacks is fraught with challenges. To exhaustively check every possible state in a billion-gate design with simulation alone would require up to trillions of verification cycles. That’s why hardware-assisted verification is one of the fastest-growing technologies in EDA. Given the complexity of today’s SoC design, it’s no surprise that verification is the largest undertaking in the entire project design cycle, consuming more than 50% of it. It also has the greatest impact on quality, cost and schedule because it prevents designs from failing at first silicon. While a respin of a large design taped out at a node below 10 nanometers could cost more than $10 million, delaying delivery of a new product for a few months in a highly competitive market may cost hundreds of millions of dollars. Smith: What other challenges do engineers face trying to verify a chip design will work as intended? Brunet: Verifying an SoC design is a massive undertaking and, in parallel, verification teams are trying to streamline and optimize verification cycles. SoC design groups are tasked with completing full system-level verification prior to creating production masks by thoroughly vetting all hardware blocks, interactions between those blocks, and the software developed for the end application before the chip is built. To alleviate this enormous pressure, they are starting to adopt a shift-left methodology for early functional verification as soon as individual blocks of a SoC design become available. It helps jump-start embedded software validation before full system validation is completed to save time and allow engineers to work in parallel, not serially. While it is an effective approach, it creates the need for a complete and integrated suite of hardware-assisted verification tools to verify and validate a design’s hardware and software components. Smith: How do you define hardware-assisted verification and how does it help solve these challenges? Brunet: A typical definition of hardware-assisted verification is special purpose hardware to accelerate verification. In other words, hardware emulation and FPGA prototyping. Hardware-assisted verification is a mandatory investment as single-die or multi-die chips get larger with more complexity and more interfaces, making hardware and software code integration critical early in the design cycle. Because software performance defines a chip’s success, the need to perform software workload-based analysis is acute, not just analysis of chip functionality, but also accurate performance and power consumption in the context of real-world applications. Hardware-assisted verification is the only option when hardware and software meet. By combining emulation, desktop FPGA prototyping boards and enterprise FPGA prototyping platforms to work on the same SoC design, a verification group can assemble a complete hardware-assisted verification system for thorough and exhaustive verification and validation. Smith: Where are the big opportunities for hardware-assisted verification? Brunet: New end-user applications are coming from computing and storage, AI/ML, 5G, networking and automotive. Recently released market data from the ESD Alliance shows that in 2020, hardware-assisted verification revenues exceeded $700 million. It is reasonable to assume that revenues of $1 billion will be within reach in the next few years given the amount of chip design activity at advanced nodes below 10nm. Smith: With the design/verification and manufacturing phases of the semiconductor supply chain more closely aligning, what role does hardware-assisted verification play? Brunet: Semiconductor manufacturing and the supply chain that supports it benefits greatly from the continued innovation in verification and validation tools and methodologies. With this innovation, designs are delivered to the manufacturing flow with a much greater chance of passing first silicon with success. This reduces friction in the semiconductor supply chain since IP and chips are available when anticipated. Hardware-assisted verification is a quick-moving, highly leveraged resource that helps a design and verification team to ensure chips are manufacturable and meet the functionality, power and performance requirements for the end-product application. Jean-Marie Brunet is the senior director of product management and engineering for the Scalable Verification Solutions Division at Siemens EDA. He has served for over 20 years in application engineering, marketing, and management roles in the EDA industry, and has held IC design and design management positions at STMicroelectronics, Cadence, and Micron, among other companies. Jean-Marie holds a Master's degree in Electrical Engineering from I.S.E.N Electronic Engineering School in Lille, France. Jean-Marie Brunet can be reached at [email protected]. About Bob Smith Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community. He is responsible for the management and operations of the ESD Alliance, an international association of companies providing goods and services throughout the semiconductor design ecosystem.

Adnan Hamid, CEO, founder and visionary of Breker Verification Systems, an ESD Alliance member based in San Jose, Calif., once described his job in chip design verification at AMD as “breaking things.” When it came to naming his startup, Breaker was a natural choice. After some consideration, the “a” was dropped and the company became Breker. Now Hamid is breaking the most complex semiconductor designs and Breker, moving from a startup to a scale-up company, is a noted part of the functional verification space. Smith: Why does verification continue to take the most amount of time in a project cycle? Hamid: The project cycle for semiconductor design has changed. Design abstraction has been raised to a much higher level than the days when developers were connecting logic gates. Today’s developers are typing functions that don’t include lower-level implementation details. Designs incorporate more blocks of reusable IP. Both reduce design time. Meanwhile, designs are getting bigger with more blocks of IP stitched together, all in need of testing. As design complexity grows, the amount of testing and verification increases as a square of design effort. One block requires one functional verification effort. Four blocks of IP mean up to 16 functional interactions require verification. While design is moving up the abstraction level, that’s not the case for verification, where plenty of detail must be reimplemented. Verification has certainly evolved, but engineers still think at the level of independent stimulus, response and coverage, driving the need to allocate so much time for verification. Smith: Are chips targeting artificial intelligence and machine learning applications more difficult to verify? If so, why? Hamid: Yes, absolutely and it’s an interesting challenge, especially given that machine learning is based on massively connected processing element arrays. Attempting to verify the individual processing elements and the critical interconnects is complex. AI device arrays and, interestingly, verification test content operation may both be thought of as a mathematical graph of processing elements and interconnect. Their operation involves walking through the graph form to generate a result. Finding the optimum path through these arrays is key. To understand how these systems may be effectively verified, it is worth investigating planning algorithms. Originally proposed by IBM, these hold the key to this type of verification process. The AI- style algorithm starts backward at the end of the processing element array and tracks down the most optimal and likely paths through it. At Breker, we have used these planning algorithms extensively to drive our graph-based test content synthesis process. Smith: Does system integration require verification? Hamid: Yes, it does. In the past, most functional verification has been performed at the block level. However, with the increase in more specialized SoCs, functionality is spread across multiple blocks, as well as the software running on the processors, driving full system-on-chip (SoC) functional verification. In addition, new requirements such as security and safety must be validated. A system-level infrastructure such as cache coherency and power domain execution has become more complex and these must also be tested. The new frontier in verification is ensuring a fully operational SoC. Of course, given the size of these SoCs, hardware-assisted verification such as emulation is essential, and porting tests from block simulations to SoC emulations has become a requirement. This porting process is problematic and this in turn has driven portable tests, giving rise to the idea behind Accellera’s Portable Stimulus Standard (PSS), of which Breker was a major participant. Indeed, some companies are taking this to the next level by composing their system-level testbench at the same time as they commence SoC architectural design, and then developing the hardware design, software design and test content all in parallel, in the so-called “shift-left” manner. Smith: Is “shift-left” a growing trend that are you seeing in verification? Hamid: Yes. Shift-left is taking hold in hardware and software design, giving way to an increase in early test content composition. Then as individual blocks are finished and connected, their verification is driven from this same test content, saving a significant amount of time and effort. This is a huge verification and test generation change that was inevitable given the increased time-to-market constraints and SoC complexity. Figure 1: Shift-left is ushering in the next generation of SoC verification. Source: Breker Smith: As an entrepreneur, what advice would you give someone founding a startup or thinking about starting one? Hamid: Do not take the attitude “Build it and they will come.” My best advice for an entrepreneur or fledgling entrepreneur is to solve a specific customer problem, however narrow it might seem. Including services as part of a product offering and developing partnerships with other vendors helps with this and turns your company into a solution provider not a product developer. This is essential for getting the right products to market on time and within budget, and then ultimately scaling them across the market. The ESD Alliance and Accellera are hosting a two-part webcast series on the work-from-home experience titled Remote Work, Remote Chip Design: Building Chips During a Pandemic. The first panel, Wednesday, June 9, at 9:00am PDT, will feature a discussion led by Tom Fitzpatrick, strategic verification architect from Siemens EDA verification engineers through their experiences converting their home offices into verification test labs. The second panel in July will explore how executives managed a remote workforce and explain how they plan to bring employees back to physical offices. About Bob Smith Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community. He is responsible for the management and operations of the ESD Alliance, an international association of companies providing goods and services throughout the semiconductor design ecosystem.