5nm

In the early 1990s, engineers of varying degrees of skill with a powerful PC set up shop designing and selling blocks or libraries of reusable components with a defined interface and behavior. These blocks, known as intellectual property, or IP, were then (and still are) integrated into a larger design. While the new market segment created excitement and new opportunities, it also was untested and created uncertainty. Many fledgling companies failed. It’s a different story today. Arm, as well as Cadence and Synopsys, are silicon IP suppliers and the segment’s yearly revenue tops $4 billion, a long way from those early garage startup days. ESD Alliance member CAST, a silicon IP provider since 1993, participated in the remarkable growth and impact on the semiconductor industry. Nikos Zervas, CAST’s CEO, and I discuss those early days of the IP business and what’s ahead. Smith: What were the early days of silicon IP like? Zervas: In those early Wild West days of IP, vendors and customers both wanted to benefit from IP, but nothing was standardized, and people just tried things to see if they worked. The perceived barrier to entry was low: hundreds of IP companies sprang up thinking they only needed RTL coding skills and tools, an FPGA to prototype, and a few thousand dollars to invest. IP deliverables, quality standards, and business practices varied from vendor to vendor and over time. Risk was high, and there are many horror stories of re-spins or market failures due to faulty IP cores. Smith: How has the silicon IP market changed from its early days? Zervas: Firms delivering high-quality IP and providing outstanding customer support survived. Others disappeared. Eventually the industry centered around a reasonably common sense of IP requirements and quality and a consistent set of business practices. IP product complexity has driven upwards as SoCs have grown. The largest ASICs used to approach a few million gates; today they’re hundreds of millions, and the granularity of IP has evolved from small functions to pre-integrated subsystems. Early on, a designer doing image processing might license individual functions like a Finite Impulse Response (FIR) filter or a Discrete Cosine Transfer (DCT) block. Today, instead they would license a complete JPEG compression core containing those functions and more, or even a complete black box subsystem streaming processed, stabilized, compressed video over Ethernet. IP selection criteria have also changed. Early IP was handcrafted to eliminate every extra gate, as being a few thousand gates smaller was a killer advantage in the era of 180nm ASIC processes. Today, at 7nm or 5nm process, tens of thousands gate differences are just noise, and it’s usually the reliability, functionality, and performance of an IP core that matter most. Smith: When did the silicon IP market start to take off? What was the driving force? Zervas: By the early to mid 2000s, uncertainty about what IP was and how best to use it – and the early wave of less-than-great providers – were being replaced by increasing acceptance and emerging best practices. The introduction of smartphones, the wild growth of Internet of Things applications, growing automotive system sophistication, and other advances fueled the explosion of the IP market in the late 2000s. In fact, according to the ESD Alliance Electronic Design Market Data Report, revenue from IP licensing today has surpassed the license revenue from front-end EDA tools. This would have been unimaginable in the late 1990s. Smith: How has silicon IP changed chip design? Zervas: Designers today must develop massive, complex systems with an even tighter time to market. Only the higher level of design abstraction and the distributed expertise that silicon IP provides make this possible. But IP also increases the challenge of differentiation: With the same IP available to everyone, how do you design a product that stands out in its market? The answer to differentiation today lies mainly in clever SoC architecture. Delivering better features with superior performance, lower power consumption, or other winning characteristics now depends not so much on perfecting each separate IP block but rather from selecting the best IP for the system’s requirements, integrating those IP cores for clean communication and efficient resource sharing, and other smart system-level decisions. It’s similar to modern building design: Every firm has access to the same materials and tools – concrete, glass, etc. – but only a few produce exceptional buildings. Smith: It seems that are several different business models for IP licensing, such as up-front license fees, subscriptions, royalties, or a combination of these. Do you think the IP market will gradually align around one basic model, or will it continue as is with a variety? Zervas: Different models serve different needs. For example, commodity IP like a SPI interface can’t demand royalties, but unique, leading-edge IP – like a 112Gbps SERDES – still can. I believe the market will continue with different business models, though the number of different models may shrink and their terms begin to align. About Nikos Zervas Dr. Nikos Zervas is the chief executive officer of CAST, Inc. He co-founded image and video compression IP developer Alma Technologies in 2001, and led the bootstrapped firm as chairman and CEO for nine years before joining CAST. He was a founding member of the Hellenic Semiconductor Industry Association and served on its board for several years with responsibility for strategic planning. He is a senior IEEE member and member of the Technical Chambers of Greece, had contributed to the GSIA's IP Working Group, and has published multiple technical papers on data compression design and related topics. Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community.

A change is underway in the manufacturing sector as the use of curvilinear shapes on photomasks grows, leading to the real possibility of curvilinear shapes in designs. It may just be the start of a revolution away from Manhattan or rectangular shapes to curvilinear shapes. Changing the physical design infrastructure to be curvilinear seems too daunting a task. Are curvilinear shapes in designs a real possibility? I turned to Aki Fujimura, CEO of D2S, a member of the ESD Alliance, a SEMI Technology Community, to further explain the shape of the future. Smith: What is the difference between Manhattan and curvilinear shapes? Fujimura: Manufactured masks and wafers are all curvilinear, even if the input CAD geometries are rectilinear (shown in Figure 1). It’s always been true that nature can’t make 90-degree turns, so sharp corners were always a matter of how closely you looked. These days, at the leading-edge nodes and their required resolutions, wafers and even masks are all visibly curvilinear as you can see in the graphic on the left in Figure 2. Since the 1980s, both chip design and chip manufacturing systems have used axis-aligned rectangles, or “Manhattan” geometries, because 1) that was sufficient to design transistors and interconnect for the most part, and 2) CPU-based computer algorithms can be made much more efficient for Manhattan geometries. Curvilinear shapes can be piecewise linear polygons of some resolution, or spline-like formats that are curvilinear at any resolution, or specific curved patterns like circles and ovals. Figure 1: All shapes on masks and wafers are curvilinear, even if the input geometries are Manhattan. Source: D2S Smith: What are the benefits of curvilinear masks? Fujimura: The manufacturing side of the semiconductor community knows that the best possible process window for wafer lithography is obtained by using curvilinear correction of mask shapes instead of Manhattan shapes. There have been numerous studies on the topic over several decades. The technique to generate purely curvilinear mask shapes is known as inverse lithography technology or ILT and is an advanced form of optical proximity correction (OPC). At a February 2020 eBeam Initiative event, Micron Technology presented a study showing process window improvement up to 85% for advanced memory designs as a result of using curvilinear ILT (shown in Figure 2). Additionally, Ryan Pearman from D2S presented a study at Photomask Japan 2019 showing that it is preferable to move toward a completely curvilinear paradigm, not only because ILT is better, but because the mask manufactured will have reduced variability. Figure 2: Micron Technology explained the benefits of curvilinear mask shapes for advanced memory at the eBeam Initiative event during 2020 SPIE Advanced Lithography Conference. Source: Micron Technology Smith: If the benefits have been known for decades, why is it happening only now? Fujimura: Several things happened at the same time. Multi-beam mask writing is now available. GPU acceleration for general computing has become mainstream. And wafer process window (resilience to manufacturing variation) is increasingly a problem for the leading-edge nodes as we are in the 5nm node, going to 3nm. Curvilinear ILT is needed much more now than before, will soon be needed for EUV lithography too, and is now possible because of multi-beam mask writing and GPU acceleration. Smith: Curvilinear mask shapes enable curvilinear design shapes too? Fujimura: Adoption of curvilinear mask shapes is the first step in targeting curvilinear shapes on wafers. Without curvilinear masks, it is difficult to target and reliably manufacture curvilinear designs. Curvilinear ILT works in the pixel-space to output the desired mask shape to maximize the process window for wafer lithography. A side effect of curvilinear ILT is that it can also take curvilinear targets as input. ILT, most likely GPU-accelerated ILT, works with rasterized input data, so the ILT algorithm itself is not affected even in runtime by having any amount of curvilinear design data. The resulting mask shapes are written in multi-beam mask writers, which write pixels with doses. They too will write curvilinear masks at the same speed as Manhattan masks. Suddenly now, curvilinear designs can be handled by chip manufacturing equally well for the first time in about 30 years. Smith: But curvilinear designs would be hard, right? There are a lot of tools that depend on the Manhattan assumption. Fujimura: Yes, you’re right. We’re not going to suddenly see chips that have curvilinear routing all over the place, or curvilinear intra-connect in standard cells or memory cells. The entire physical design infrastructure that includes place and route, timing, custom layout, parasitic extraction and design rule checking moving to curvilinear design all at once is extremely unlikely. Could portions of these problems be tackled for specific cases over time as “hot spot” solutions? With GPU-accelerated SPICE being available now, as an example, if GPU acceleration is adopted for design, the same transformation that happened in manufacturing can (gradually) happen in design too. The key question is whether it’s worth the trouble. Smith: Is it worth the trouble? Fujimura: I don’t know if it’s worth the trouble for the entire infrastructure. For hot spots, “hot” for various reasons, there are certainly benefits. Jogging a 32-bit bus by one grid is certainly much more economical space-wise with curvilinear shapes. Inside standard cells or memory cells, there are certain types of features that pack better with curvilinear designs. In general, interconnect is the limiter to chip size of course, but there are always critical areas that could use help to shrink. There are manufacturability benefits as well. In general, when something changes so drastically as this for the first time in 30 years, there’s bound to be some innovation that takes advantage of the discontinuity. Let’s see what the combined capitalistic power of the entire community might be able to come up with. The first thing is to let everyone know that curvilinear designs will be manufacturable today. Hear insights from other leading electronic system design industry CEOs at the SEMI ESD Alliance CEO Outlook on May 18, 2021, 2:00pm-3:00pm PDT. Panelists will discuss the state of the industry along with their views of the outlook for the coming years. Registration is free for SEMI members. About Bob Smith Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community. He is responsible for the management and operations of the ESD Alliance, an international association of companies providing goods and services throughout the semiconductor design ecosystem.