process design kit

The semiconductor industry is undergoing a rapid transformation. Artificial intelligence (AI) applications, such as agentic and physical AI, push compute demands to unprecedented heights, prompting the semiconductor industry to push the boundaries of 2nm technology and beyond. Yet, as we move to these advanced semiconductor technology nodes, it has become increasingly challenging for academic research to remain closely connected with the fast-evolving industrial developments, limiting academic researchers in driving innovation. Europe’s NanoIC pilot line, a pioneering European initiative, hosted by imec, is addressing this challenge by offering pathfinding process design kits (P-PDKs). To cover the potential of these P-PDKs and their impact on Europe’s semiconductor ecosystem, we sat together with Professor Mehdi Tahoori (professor at Karlsruhe Institute of Technology) and Anita Farokhnejad (DTCO Program Manager at imec).SEMI: What exactly is a P-PDK, and how does it differ from traditional PDKs?Farokhnejad: At its core, a process design kit (PDK) is a software environment that enables circuit designers to simulate, validate, and optimize chip designs using realistic models of chip technology. Consider it a blueprint or a simulation toolkit allowing chip designers to explore performance, power, and manufacturability of a new chip architecture in a virtual sandbox. What sets P-PDKs apart is that they anticipate future technologies. Unlike traditional PDKs, which are based on existing technologies, P-PDKs are built on predictive models of future nodes and architectures. This allows researchers to explore system-level trade-offs, assess architectural implications, and prepare design flows before a technology reaches maturity. SEMI: Why are they so crucial for academia?Tahoori: For decades, academic researchers could contribute to semiconductor innovation using abstraction layers that allowed them to design and test new architectures without direct access to the latest technologies. This approach worked well until the industry reached the 20-nanometer node. At that point, the complexity of semiconductor design increased, with the introduction of advanced device architectures like FinFETs, nanosheets, Forksheets, CFETs, and novel integration solutions such as 3D stacking and chiplet integration.Transistor scaling in the AI eraTraditional abstraction models could no longer keep up with these advances, and the gap between academic research and industrial practice began to widen. This growing gap started to limit academia’s ability to participate in semiconductor paradigm shifts, such as CMOS 2.0 and new computing architectures. P-PDKs, enabled by the NanoIC pilot line, aim to bridge this gap, restoring the connection between academic thinking and industrial progress.SEMI: How does this support semiconductor innovation in Europe?Tahoori: Universities are ideally positioned to drive out-of-the-box innovation and invent new paradigms for computing. This is where universities truly excel. But to do that, they need access to the latest technologies and tools. We see for example a strong focus on the AI revolution and how the microelectronics industry is enabling that transformation. To meet the demands of AI applications and the computing power they require, we need to design new computing architectures based on advanced technology nodes. This is precisely the academic area of expertise. To design these new AI computing architectures, however, we need the most advanced technologies available. The P-PDKs for advanced nodes provided by the NanoIC pilot line now make this kind of research possible at universities. Something that was not feasible before.Additionally, the P-PDKs also provide an important reference technology and platform to benchmark and validate these innovations within a next-generation design roadmap. This means researchers can test their novel architectures against realistic process and performance metrics.SEMI: Are they only available for academia?Farokhnejad: The NanoIC P-PDKs are meant to be accessible to foster innovation across Europe’s semiconductor ecosystem. These advanced PDKs are therefore also available to European research organizations, startups, and industry partners. Access is facilitated through Europractice, where eligible users can apply by signing a Design Kit License Agreement (DKLA). Once approved, they gain access to the PDKs.SEMI: What other technology nodes are NanoIC’s PDKs addressing?Farokhnejad: The first P-PDK was released in June (first version of the N2) and supports frontside and backside routing with TSVM, standard cell libraries, and multiple VT flavors for early-stage design exploration. Upcoming releases include new versions of the N2 P-PDK, as well as A14 and A7 PDKs, eDRAM and SOT memory PDKs, and advanced interconnect solutions such as redistribution layers (RDL), hybrid bonding, and interposers.Those interested in learning more about the NanoIC ecosystem and the research enabled by the P-PDKs can meet representatives and partners of the NanoIC pilot line during SEMICON Europa, November 18-21 at booth C2417 in Messe Munchen. More information about the initiative is also available on the NanoIC website.BiosMehdi Tahoori, Professor Chair of Dependable Nano-Computing - Karlsruhe Institute of Technology Mehdi B. Tahoori is Professor and Chair of Dependable Nano-Computing at the Karlsruhe Institute of Technology (KIT), Germany, and guest professor at imec, focusing on CMOS 2.0 and future chip technologies. He previously worked at Xilinx (USA), Fujitsu Labs (USA), and served as a junior professor at Boston Northeastern University (USA) and as a visiting professor at the University of Tokyo (Japan). He earned his B.S. from Sharif University (Iran) and M.S./Ph.D. from Stanford (USA). Prof. Tahoori is Deputy Editor-in-Chief of IEEE Design and Test Magazine, is a former Editor-in-Chief of Elsevier Microelectronic Reliability and has chaired major IEEE symposia. His honors include multiple best paper nominations and conference awards, the US National Science Foundation Early Faculty Development (CAREER) Award (2008), an ERC Advanced Grant (2022), and an IEEE fellowship.Anita Farokhnejad, DTCO Program Manager - imec Anita Farokhnejad earned her PhD from Universitat Rovira i Virgili (Spain), specializing in FEOL and device modelling. She joined imec in 2021 as an R D Engineer, focusing on BEOL optimization and future roadmap development. Collaborating closely with integration and physical design teams, she develops models for PnR data analysis and BEOL optimization. Her recent work on the enhanced Ring Oscillator (eRO) model aids in the early assessment of new materials and BEOL boosters. In August 2023, she advanced to team lead for PDK Enablement, translating advanced semiconductor nodes into Pathfinding-PDKs. Farokhnejad is also dedicated to education, conducting courses that make sophisticated technological concepts accessible to both industry veterans and aspiring engineers. Currently, she serves as Program Manager of DTCO at imec, where her contributions continue to drive innovation in the semiconductor industry.AcknowledgementThis work was enabled by the NanoIC pilot line. The acquisition and operation are jointly funded by the Chips Joint Undertaking, through the European Union’s Digital Europe (101183266) and Horizon Europe programs (101183277), as well as by the participating states Belgium (Flanders), France, Germany, Finland, Ireland and Romania. For more information, visit https://www.nanoic-project.eu.DisclaimerFunded by the European Union. Views and opinions expressed are however those of the author(s) only and do not necessarily reflect those of the European Union or Chips Joint Undertaking. Neither the European Union nor the granting authority can be held responsible for them. SEMI ContactJames Lam, Business Development ManagerEmail: [email protected]

New MEMS-based products are constantly emerging, fueled by the Internet of Things (IoT), autonomous driving, smart manufacturing and healthcare applications. The MEMS pressure sensor market is no exception to this trend1. Its growth has been driven mainly by automotive applications such as tire pressure management system (TPMS) regulations in China, fuel and ignition systems, thermal systems, oil-pressure monitoring, and indoor and outdoor navigation systems. Easy to customize and integrate, miniature, sensitive, accurate and low-power MEMS devices are especially well-suited to the accuracy, power consumption, sensitivity and miniaturization that pressure sensors require.Yet MEMS design also presents some specialized challenges, such as a strong coupling between fabrication technology and design. Complex physical structures that exhibit non-linear behavior, custom packaging requirements, and a final product that requires integration with surrounding CMOS circuitry are just a few examples. What’s more, there is a lack of standardized processes and process validation in MEMS design ecosystems. Pressure Sensor (Courtesy: X-FAB) As with other products based on MEMS technology, designers must increasingly customize pressure sensors for higher performance – sensitivity and linearity, in this case – while decreasing their package size. Designers can accomplish the task by studying sensor performance and manufacturability using computer models prior to fabrication. This can ensure that the sensor meets its required specifications while simultaneously reducing manufacturing cycles and cost.The Power of CollaborationThis is where strong collaboration among EDA providers, MEMS technologists and designers delivers tangible benefits. EDA providers and MEMS foundries can collectively help MEMS designers to incorporate foundry process constraints into their designs.In the semiconductor industry, first-pass successful silicon relies on standardized manufacturing processes, thorough technology characterization, accurate model generation, established simulation and verification, and extensive reuse of proven design blocks. In the MEMS world, where processes and products are developed concurrently, and processes change with every product, is it possible to adopt standardized processes, design methodologies, and tools that enable efficient reuse of existing technology and design knowledge? The challenge lies in maintaining the flexibility to optimize products for a diverse array of requirements. The ideal design platform should ease sharing of technology and design data between the foundry and its customers, enabling two-way collaborative development and allowing foundry technologists to easily perform a feasibility assessment of a customer’s project. This approach offers important benefits, allowing designers to explore and evaluate the suitability of a foundry’s process technology in their unique application. It also supports accurate prediction of device performance prior to fabrication and reduces costly build-and-test cycles. Combining standardized manufacturing processes, MEMS process design kits (PDKs), and a proven design flow are the starting point for development of manufacturing-ready designs.A Real-Life Example using Pressure SensorsAn EDA company, Coventor (a Lam Research company), along with MEMS foundry partner X-FAB, collaborated to develop a PDK that would ensure that manufacturing constraints are automatically considered early in their design process. The design flow is based upon an X-FAB fabrication platform that supports multiple process options for the manufacturing of absolute and relative MEMS pressure sensors. The PDK is a “golden container” for all the process and material characteristics of the silicon membrane and substrate, glass, passivation layers, and piezoresistive components. It enforces material properties and guarantees their correct implementation during the simulation. It also includes a component library containing ready-to-use, 3D parameterized devices (such as membranes and resistors), all pre-designed with foundry-supported materials to support their respective design rules. The components are readily partitioned for optimized meshing and simulation, saving design and simulation time. Figure 1: The elements and design flow of the PDK designed by Coventor and X-FAB. (Courtesy: Coventor)Designers can use components from the library to create a custom design — which might include different membrane shapes and sizes, and resistors of varying shape, size and position — to simulate the impact of different technology variants (such as resistor doping profiles, membrane and substrate thickness, glass material properties, and passivation schemes). This allows them to anticipate the effect of these design changes on sensor sensitivity for varying pressure and temperature regimes.Extensive validation of the pressure sensor design platform is currently underway. So far, the simulations have exhibited very good correlation to actual device measurements across a range of pressure and temperature conditions, including predictions of non-linear behavior for various pressure sensor designs. At the same time, the simulation accounts for mechanical membrane properties and piezoresistivity. With this type of design platform, a foundry can provide guidelines to help customers select both the fab technology and design features that lead to an optimal design solution. Figure 2: Simulation results depicting mechanical displacement in a pressure sensor design (Courtesy: X-FAB) Let’s Face the Next Challenges…A complete design platform for MEMS must eventually include not only MEMS device design, but system integration functions, such as the application-specific integrated circuit (ASIC) design and packaging/assembly of the product. In addition to the design verification that the PDK provides, additional partnerships among foundries, integrated device manufacturers (IDMs), research centers, equipment suppliers, and EDA vendors will help to define requirements and solutions that address every level of design and production. These might include tasks such as describing standardized material properties and process specifications, creating accurate foundry-proven design models, and defining requirements for system-level simulation. In the future, PDK simulations might even include up to tape-out and physical verification. To learn more about this collaborative PDK development work, please click here for the whitepaper.Christine Dufour, MEMS PDK Program Manager, CoventorChristine Dufour is the MEMS PDK program manager at Coventor. She has more than 20 years of experience in the semiconductor industry, leading process design kit development for BiCMOS and CMOS processes at several major semiconductor companies. Ms. Dufour has also worked as a product manager in the RF design environment area. In addition to her extensive experience in MEMS PDK development, she is an expert in all aspects of MEMS design flow and design tool development. Ms. Dufour received an engineering degree at Technological University of Compiegne.For more information on Coventor, a Lam Research Company, visit: https://www.coventor.com/ Viraja Sharma, Development Engineer, MEMS Simulation Design, X-FABViraja Sharma is a development engineer for MEMS Simulation Design at X-FAB. Her work involves the design and simulation of MEMS inertial and pressure sensors. Prior to her tenure at X-FAB, Ms. Sharma performed similar duties for other semiconductor companies. She received her Master of Science degree in Micro and Nano Systems from TU Chemnitz, where she studied MEMS and micro technologies.For more information on X-FAB, visit: https://www.xfab.comCoventor and X-FAB are members of SEMI-MEMS Sensors Industry Group that connects the MEMS and sensors supply network, enabling members to address common industry challenges and explore new markets. 1 Market research firm Yole Développement predicts that MEMS pressure sensors alone will become a $2 billion market by 2023. See: https://yole-i-micronews-com.osu.eu-west 2.outscale.com/uploads/2019/01/YD18018_MEMS_Pressure_Sensor_Market_Yole_Developpement_2018_Sample.pdf