silicon photonics

Artificial intelligence (AI) and high-performance computing (HPC) are driving unprecedented demand for data movement. As bandwidth requirements climb and conventional electrical interconnects encounter limitations in power consumption, latency and reach, silicon photonics, near-packaged optics (NPO), and co-packaged optics (CPO) are becoming increasingly important technologies for next-generation data centers.Much of the industry’s attention has focused on photonic device innovation. But demonstrating a high-performance photonic integrated circuit (PIC) is only part of the challenge. Turning these devices into products that can be manufactured reliably and economically at high volume requires a test infrastructure that can keep pace.This represents a significant shift. Semiconductor manufacturing has benefited from decades of refinement in automated electrical test. Silicon photonics adds an optical dimension that brings new requirements for fiber alignment, coupling efficiency, polarization management, and optical instrumentation—while still requiring conventional electrical characterization.As silicon photonics moves from development environments toward high-volume production, test becomes more than a quality gate. It is an integral part of the manufacturing strategy.An HVM-ready test solution requires a full complement of supporting hardware and software.Bringing precision optical alignment to productionOne of the most fundamental challenges is establishing a reliable optical connection to the device under test. Unlike electrical probing, where physical contact provides a relatively straightforward interface, optical testing depends on precisely coupling light into and out of very small structures.That coupling must be repeatable from device to device and wafer to wafer. Even small variations in fiber position or angle can affect insertion loss and measured optical performance, potentially making it difficult to distinguish actual device variation from variation introduced by the test setup.For this reason, high-volume testing requires automated alignment capabilities that can quickly locate the optical interface and optimize coupling. This can involve visual or image-based positioning to bring a fiber array unit close to the grating couplers, followed by area scans and gradient-search techniques to identify the optimal position via feedback loops – a technique typically referred to as “active alignment.” The process may also require optimization across six degrees of freedom—X, Y, and Z positioning plus three rotational axes—to maximize coupling efficiency and minimize channel-to-channel variation.The problem becomes more complex as optical interfaces add channels. Alignment must not simply maximize one channel's performance; it must produce consistent coupling across multiple channels. Rotational alignment, for example, can influence how evenly an optical beam overlaps multiple grating couplers. Other angular adjustments can affect both insertion loss and center wavelength.Polarization presents another variable. Because photonic structures can respond differently depending on the polarization state of incoming light, polarization must be characterized and controlled as part of a repeatable production methodology. Together, these requirements make alignment an active measurement and optimization process rather than a simple mechanical positioning step. The manufacturing challenge is to automate these functions without allowing alignment time to become a throughput bottleneck.Combining electrical and optical test without sacrificing throughputAlignment is only one part of the equation. A PIC may incorporate photodetectors, modulators, and other components requiring combinations of optical and electrical measurements. Typical characterization can include insertion loss, channel-to-channel uniformity, optical attenuation, photodetector responsivity, and wavelength-dependent behavior.Performing these measurements sequentially can add substantial test time. A more scalable approach is to integrate electrical and optical capabilities so that operations can occur concurrently wherever possible. For example, electrical alignment can occur before optical alignment, while continuity and other electrical tests may run during automated optical probe alignment rather than waiting for that process to finish. This type of parallelism becomes increasingly important as device complexity and test coverage grow.The same principle applies to optical instrumentation. Rather than treating each instrument as an isolated resource, high-volume environments benefit from integrated control of lasers, power meters, and other optical equipment, enabling parallel operation of multiple instruments or channels. Automated calibration and compensation are also important for maintaining measurement consistency as the test cell becomes more complex. Advantest’s development work in this area supports multiple optical instruments and parallel power-meter operation within a common test environment.The broader objective is familiar from semiconductor test: maximize useful test coverage while minimizing test cost. What changes with silicon photonics is the number of physical and measurement domains that must be coordinated to achieve it.Collaboration will be essential to ecosystem scalingNo single supplier controls all of the elements required for high-volume PIC test. The complete solution can span automated test equipment, wafer probing, optical positioning, fiber interfaces, optical instrumentation, device design, and manufacturing processes.That makes ecosystem collaboration particularly important. Test equipment providers need to work with probe and positioning specialists, photonic device developers, foundries, and manufacturers so the interfaces among these technologies function as an integrated production system rather than individual laboratory instruments.As an example, Advantest has collaborated closely with FormFactor to develop a wafer-level photonics test environment that combines electrical test instrumentation with wafer handling, optical instruments, and automated fiber alignment capabilities. The significance lies less in individual components than in the integration required to create a repeatable manufacturing workflow.As silicon photonics, NPO and CPO move toward broader adoption, these collaborative efforts will become increasingly important. The industry must develop practical test methodologies that accommodate evolving device architectures while delivering the repeatability, throughput, and economics expected of semiconductor manufacturing.Numerous photonics developments on the horizon will require broad industry effort to bring to fruition.The transition from promising photonic technology to high-volume commercial products will depend on more than advances in the devices themselves. Test must evolve alongside them. By treating optical alignment, electrical and optical measurement, automation, and ecosystem interoperability as parts of a single manufacturing challenge, the industry can build the infrastructure needed to bring silicon photonics fully into the era of high-volume production. About the AuthorDr. Clemens Leichtle is Senior Director and V93000 Photonic Business Lead for Advantest Corp. He has more than 25 years of experience in the semiconductor industry, with companies including Siemens, Agilent and Verigy, specializing in testing and developing respective application solutions for emerging technologies. For more than 15 years, he has been leading the V93000 Center of Expertise at Advantest; more recently, he co-led test solution development for silicon photonics and co-packaged optics targeting data center applications. Dr. Leichtle holds a Ph.D. in physics from the University of Ulm, Germany.

Advanced packaging is no longer operating behind the scenes. The technology of advanced packaging is helping to sustain the speed of the semiconductor industry’s improvement in power and performance, even as the Moore’s Law roadmap for wafer-level scaling comes under strain.At the Advanced Packaging Conference during SEMICON Europa 2025 in Munich, global experts examined the growth trajectory of this critical sector and Europe’s potential to lead in next-generation packaging solutions.Market Momentum Fueled by AI and HPCRomain Fraux, Chief Research Officer at Yole Group, forecasted that global revenues for advanced packaging will grow from $46.1 billion in 2024 to $79.4 billion by 2030. “Everything is linked to AI and high-performance computing (HPC),” said Fraux, while also emphasizing the growing relevance of automotive applications in driving demand.Romain Fraux, Chief Research Officer, Yole GroupThis demand is accelerating innovation across the supply chain. One emerging area is panel-level packaging, which breaks away from traditional round wafers. As Andreas Wocko, Sales Manager at Lam Research, observed, “Since the 1970s, the semiconductor industry has built on wafers. Now we are not just scaling, we are reshaping, building in a square format for the first time” – an innovation which substantially increases area efficiency and reduces device cost. Andreas Wocko, Sales Manager Europe, Lam ResearchTechnology Transformation from Lab to FabEurope is already investing in the foundational technologies that will power tomorrow’s packaging systems. Rolf Aschenbrenner, Deputy Director of Fraunhofer IZM, the home of the European Union’s APECS advanced packaging pilot line, discussed ongoing research into functional interposers, routing density, and organic interposers. “Our goal is to show how a new design philosophy incorporating chiplets can be brought to the industrial systems level,” said Aschenbrenner.Rolf Aschenbrenner, Director Deputy, Fraunhofer IZMThese breakthroughs are essential, as pitch sizes shrink and new materials emerge. Dr. Jessica Stubbe, Global Application Manager at MKS Atotech, described how interconnect densities have doubled in the past two years, with the industry moving to pitch sizes of less than 10µm. Stubbe said this new technology “will be enabled by a move from traditional solder-based interconnects to copper-to-copper hybrid bonding to provide higher density I/Os and lower resistance.” Jessica Stubbe, Global Application Manager, MKS AtotechInnovation Meets Real-World IntegrationThis increased density carries thermal risks with it. As Ram Trichur, Global Head of Semiconductor Packaging at Henkel Corporation, said, “New architectures enabled by advanced packaging are putting power devices on the backside, interposer or substrate, and this addition of more power delivery components in the package creates more local hotspots.”The reduced feature sizes inside the latest packages make it more difficult than ever to apply thermal interface materials. “At Henkel, we are now making 1µm-level fillers which enable the effective filling of gaps as small as 7µm,” said Trichur.Ram Trichur, Global Head of Semiconductor Packaging Market Segment, Henkel CorporationOne of the applications which stands to gain the most from the development of advanced packaging technology is silicon photonics. Dr. Himani Kamineni, Director for Advanced Packaging at GlobalFoundries, described how co-packaged optics (CPO) brings photonics directly inside the package, reducing connection lengths from centimeters down to millimeters, and providing higher bandwidth and lower latency at lower power. “Advanced packaging and CPO are foundational elements for AI and data centers to enable scalability to the next generation of compute,” said Kamineni. “But it will need a lot of packaging innovation: silicon interposers, copper-to-copper interconnects, and fiber-attach units for precise alignment.” Himani Kamineni, Director, Advanced Packaging, GlobalFoundriesReliability and Test Under PressureIn the transition to new packaging technology, it is crucial that the industry does not lose sight of the reliability standards which have made semiconductors so valuable in sectors such as automotive and aerospace. Amar Mavinkurve, Director of Materials and Labs Package Innovation at NXP Semiconductors, warned the finer spacing and smaller feature sizes in the latest packages posed a problem for reliability and long-term performance. He said, “We are dealing now not just with one failure mechanism, but with multiple. So, the way that we are used to describing behavior in models will not necessarily hold in future. Even industry standards might not hold.”Discussing new technologies such as copper-to-copper interconnects, Mavinkurve pointed out that failure would not be due to a single event, but to processes such as electromigration, corrosion, and thermomechanical effects. To model reliability properly in future, he said, “we need to move from a physics of failure to a physics of degradation.” Amar Mavinkurve, Director Materials and Labs Package Innovation, CTO, NXP SemiconductorsFabio Pizza, Business Segment Manager at Advantest Europe focused on quality and failure. With geometry scaling toward 1nm, early identification of known-good dies is essential to optimize cost and test coverage. Pizza said that, while device manufacturers need to keep time-to-market and the cost of test under tight control, they are also trying to figure out how to increase test coverage. “In a modern GPU, even a 100 DPPM quality process leaves 20 million transistors untested,” he said. Fabio Pizza, Business Segment Manager, Advantest EuropeEurope’s Position in the Global EcosystemThe conference concluded with a panel discussion about the prospects for Europe in the global advanced packaging market. According to Yole’s Romain Fraux, there is a strong ecosystem in Europe: “Europe’s strengths include specialized packaging service providers in the photonics and power market segments, as well as many packaging equipment manufacturers,” said Fraux. This resonated with the instincts of NXP’s Amar Mavinkurve and Advantest’s Fabio Pizza. Mavinkurve said: “We should focus on what we are already good at doing. It will be challenging to compete with advanced packaging providers elsewhere for AI and HPC business.”Ram Trichur of Henkel, however, urged the industry in Europe, “Do not take your foot off the gas on advanced packaging. You cannot do the full stack here, but in a technology such as CPO, there is a lot of innovation in Europe, and there is scope to add the manufacturing of these devices on top of the research capabilities.”Chris Scanlan, Senior Vice President of Technology at Besi, raised the idea of shifting production toward Eastern Europe. But Trichur cautioned that talent and infrastructure remain limiting factors in that strategy. From left to right: Chris Scanlan, Senior Vice President Technology, Besi;Amar Mavinkurve, Director Materials and Labs Package Innovation, CTO, NXP Semiconductors; Fabio Pizza, Business Segment Manager, Advantest Europe; Rolf Aschenbrenner, Director Deputy, Fraunhofer IZM; Ram Trichur, Global Head of Semiconductor Packaging Market Segment, Henkel CorporationCollaboration is the Path ForwardSpeakers throughout the conference echoed a common message: advanced packaging is reshaping the semiconductor landscape, and global collaboration will be essential to success. “It is impossible for one country or one region to do the entire stack,” Trichur concluded. “Innovation must be matched with strategic partnerships to bring advanced packaging from research to real-world impact.”On behalf of SEMI, the SEMI Europe team would like to thank the industry leaders whose expertise and enthusiasm made this conference a resounding success. SEMI ContactCassandra Melvin, Senior Director of Business Development and OperationsEmail: [email protected]

Post-Conference Report: SEMI Heterogeneous Integration SummitDemand for high-performance computing (HPC) chips is exploding. These super-speedy chips are critical for data centers and cloud computing infrastructures to support new performance-hungry technologies such as artificial intelligence (AI) and 5G. The challenge is for the devices and their multi-core architectures to couple high bandwidth density with low latency and high energy efficiency. Heterogenous integration offers a potential answer as an advanced packaging technology designed to meet these skyrocketing performance demands on HPC chips and open the door to a whole new world of 3D integrated circuits (ICs).So important are 3D ICs that Intel and TSMC representatives speaking at the recent Heterogeneous Integration Summit hosted by SEMI Taiwan in Taipei declared that the packaging technology will all but dictate the future of the industry. All told, 12 speakers from government, academia and a broad range of leading international companies from sectors including advanced packaging, design, manufacturing, silicon photonics, equipment and materials shared forward-looking strategies, the latest technologies and potential heterogeneous integration market opportunities. Koushik Banerjee, vice president, TMG, Assembly, and Test Technology Integration, at Intel pointed out that using heterogeneous integration for a single SiP (system-in-package) will deliver what the industry has long wanted by enabling multiple process nodes, more diverse silicon IP (intellectual property) and chip functionality, and chips that pair low energy with high frequency. Intel plans to announce its first Forveros 3D packaging product combining a 10nm HPC chiplet with a low-energy 22nm base die and stacked with memory on top. When asked about the future of advanced packaging technology, Banerjee said it will be very much about the combination of Foveros and its very own Embedded Multi-Die Interconnect Bridge (EMIB).For its part, TSMC, will continue to upgrade its CoWoS (Chip-on-Wafer-on-Substrate), InFO (Integrated Fan-out) and other 2.5D IC production solutions while developing 3D chip stacking technology such as SoIC and WoW (wafer-on-wafer). TSMC is ushering in a new age of 3D IC packaging, said Marvin Liao, Vice President, Backend Technology and Service Division, at TSMC. The company’s SoIC is based on Chip-on-Wafer concept, with the flexibility to support one-to-many or different process nodes, whereas its WoW integrates two wafers with solid yields that could be used for products of the same size or manufactured with mature process technology.Speakers also included representatives from ATOTECH, Lam Research, SPIL, Sigurd, Cadence, Grand Process Technology, ITRI (Industrial Technology Research Institute), Industrial Development Bureau, and Lee San-Liang, Distinguished Professor, Department of Electronic and Computer Engineering at National Taiwan University of Science and Technology all shared their perspectives on equipment, materials, and testing and how different industry value chains might contribute to the development of heterogeneous integration technology.Expected to be a key driver of the next wave of semiconductors, heterogeneous integration and related technologies – including 3D IC, FOWLP (Fan-out wafer-level packaging) / FOPLP (Fan-out panel-level packaging), silicon photonics, Micro LED, compound semiconductor, automated optical inspection and SLT (system level testing) – will be a key focus at SEMICON Taiwan 2019, September 18 to 20 in Taipei. The Heterogeneous Integration Innovation Zone – along with featured international programs such as SiP Global Summit, Strategic Materials Conference, the Smart Data Summit and the Smart Automotive Summit – will gather key industry players to reveal the latest technology breakthroughs and market trends.Emmy Yi is a senior marketing specialist at SEMI Taiwan.