SoCs

Anna Fontanelli, Monozukuri’s founder and CEO, is an expert in deep-submicron silicon technology and design tools shares her view on the state of Moore’s Law and challenges surrounding 2.5D integration, 3D chip stacking & advanced packaging, as well as the chip design industry’s startup environment.

In the early 1990s, engineers of varying degrees of skill with a powerful PC set up shop designing and selling blocks or libraries of reusable components with a defined interface and behavior. These blocks, known as intellectual property, or IP, were then (and still are) integrated into a larger design. While the new market segment created excitement and new opportunities, it also was untested and created uncertainty. Many fledgling companies failed. It’s a different story today. Arm, as well as Cadence and Synopsys, are silicon IP suppliers and the segment’s yearly revenue tops $4 billion, a long way from those early garage startup days. ESD Alliance member CAST, a silicon IP provider since 1993, participated in the remarkable growth and impact on the semiconductor industry. Nikos Zervas, CAST’s CEO, and I discuss those early days of the IP business and what’s ahead. Smith: What were the early days of silicon IP like? Zervas: In those early Wild West days of IP, vendors and customers both wanted to benefit from IP, but nothing was standardized, and people just tried things to see if they worked. The perceived barrier to entry was low: hundreds of IP companies sprang up thinking they only needed RTL coding skills and tools, an FPGA to prototype, and a few thousand dollars to invest. IP deliverables, quality standards, and business practices varied from vendor to vendor and over time. Risk was high, and there are many horror stories of re-spins or market failures due to faulty IP cores. Smith: How has the silicon IP market changed from its early days? Zervas: Firms delivering high-quality IP and providing outstanding customer support survived. Others disappeared. Eventually the industry centered around a reasonably common sense of IP requirements and quality and a consistent set of business practices. IP product complexity has driven upwards as SoCs have grown. The largest ASICs used to approach a few million gates; today they’re hundreds of millions, and the granularity of IP has evolved from small functions to pre-integrated subsystems. Early on, a designer doing image processing might license individual functions like a Finite Impulse Response (FIR) filter or a Discrete Cosine Transfer (DCT) block. Today, instead they would license a complete JPEG compression core containing those functions and more, or even a complete black box subsystem streaming processed, stabilized, compressed video over Ethernet. IP selection criteria have also changed. Early IP was handcrafted to eliminate every extra gate, as being a few thousand gates smaller was a killer advantage in the era of 180nm ASIC processes. Today, at 7nm or 5nm process, tens of thousands gate differences are just noise, and it’s usually the reliability, functionality, and performance of an IP core that matter most. Smith: When did the silicon IP market start to take off? What was the driving force? Zervas: By the early to mid 2000s, uncertainty about what IP was and how best to use it – and the early wave of less-than-great providers – were being replaced by increasing acceptance and emerging best practices. The introduction of smartphones, the wild growth of Internet of Things applications, growing automotive system sophistication, and other advances fueled the explosion of the IP market in the late 2000s. In fact, according to the ESD Alliance Electronic Design Market Data Report, revenue from IP licensing today has surpassed the license revenue from front-end EDA tools. This would have been unimaginable in the late 1990s. Smith: How has silicon IP changed chip design? Zervas: Designers today must develop massive, complex systems with an even tighter time to market. Only the higher level of design abstraction and the distributed expertise that silicon IP provides make this possible. But IP also increases the challenge of differentiation: With the same IP available to everyone, how do you design a product that stands out in its market? The answer to differentiation today lies mainly in clever SoC architecture. Delivering better features with superior performance, lower power consumption, or other winning characteristics now depends not so much on perfecting each separate IP block but rather from selecting the best IP for the system’s requirements, integrating those IP cores for clean communication and efficient resource sharing, and other smart system-level decisions. It’s similar to modern building design: Every firm has access to the same materials and tools – concrete, glass, etc. – but only a few produce exceptional buildings. Smith: It seems that are several different business models for IP licensing, such as up-front license fees, subscriptions, royalties, or a combination of these. Do you think the IP market will gradually align around one basic model, or will it continue as is with a variety? Zervas: Different models serve different needs. For example, commodity IP like a SPI interface can’t demand royalties, but unique, leading-edge IP – like a 112Gbps SERDES – still can. I believe the market will continue with different business models, though the number of different models may shrink and their terms begin to align. About Nikos Zervas Dr. Nikos Zervas is the chief executive officer of CAST, Inc. He co-founded image and video compression IP developer Alma Technologies in 2001, and led the bootstrapped firm as chairman and CEO for nine years before joining CAST. He was a founding member of the Hellenic Semiconductor Industry Association and served on its board for several years with responsibility for strategic planning. He is a senior IEEE member and member of the Technical Chambers of Greece, had contributed to the GSIA's IP Working Group, and has published multiple technical papers on data compression design and related topics. Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community.

Even though microchips continue to get smarter, vital security gaps continue to be exposed through such hack attacks as Meltdown, Spectre, and in recent weeks, Plundervolt. Researchers continue to discover open doors in chip architectures for malicious players to steal increasingly sensitive data, hide the identity of counterfeits, or tamper with electronics systems most anywhere along the global microelectronics supply chain. Today, it’s impossible to have full visibility of the distributed chip making process – from design and fabrication to packaging, testing and delivery. That’s why our industry’s future hinges to a large degree on establishing a hardware root of trust throughout the silicon’s operational lifecycle. Trust but verify! It’s easy to say, but how do we do it?To gain insights, SEMI interviewed Dr. Mark Tehranipoor, currently the Intel Charles E. Young Preeminence Endowed Chair Professor in Cybersecurity at the University of Florida’s Electrical and Computer Engineering Department. A foremost authority on microelectronics security and trust, counterfeit electronics detection, and supply chain risk management, Dr. Tehranipoor will be a keynote speaker at the SEMICON Taiwan Security on Chip Summit, Friday, September 25, where a full program of industry leaders will address key security challenges and solutions involving IoT, systems on a chip (SoCs), integrated circuits, physical unclonable function (PUF) technology, future design, certifications, managed services, and more.For additional insights and to hear Dr. Tehranipoor’s full presentation, register for SEMICON Taiwan 2020, which SEMI is holding as a hybrid event with both a virtual format and an in-show program September 23-25.SEMI: What are the major uncertainties in providing the hardware root of trust within the cyber domain?Tehranipoor: One of the most critical issues we’re dealing with now is loss of control over the process of designing and fabricating integrated circuits and systems. This has happened along with globalization and the movement of supply chain operations overseas to lower costs of nearly all goods, including electronics products and semiconductors. As skill sets, talent, design and fabrication have all shifted offshore, concerns have also risen about security controls across the many different segments of the microelectronics supply chain.For example, when you think about the security of military, space, transportation, power grids, financial or other networks, it becomes a major concern if you cannot trust the underlying electronics system that runs them. New SoCs are also holding more sensitive data around encryption keys, biometrics, personal information or banking data. And as reports escalate about cybersecurity gaps at the electronics part level, it’s increasingly important to establish a hardware root of trust. Today, it’s not enough for a buyer to just call up the design house and verify the electronic ID of an asset. The ID might match, but the device could have been tampered with or replaced with a counterfeit somewhere along its end-to-end journey. Unlike software or networks where problems can be automatically identified, upgraded and fixed, verifying electronic hardware is a costly and time-consuming process, especially when they’re as complex as microchips. It can take months to deconstruct, reverse engineer, inspect, and authenticate a chip. By then, discovery of any security breaches is too late.When addressing the security of electronics systems, there are three important features to keep in mind. First, there’s confidentiality. The device shouldn’t leak information to an unauthorized user. Second, there’s integrity. Unauthorized users should not be able to manipulate an SoC’s sensitive data. The third feature is availability, which can be a result of Denial of Service (DoS) attacks. If the device is under attack and can’t access your online service or network, you must still have security measures for your electronics system to be available in a safe mode while you simultaneously identify the problem, recover from it, and return to normal functions.SEMI: What framework should be followed to establish greater trust and confidence across the entire microelectronics supply chain?Tehranipoor: In the United States, we recognize it may not be possible to bring all manufacturing, design, and delivery teams back to this country and have them certified by the U.S. Department of Defense. You could do some of it, but it would be very costly and complex to bring back all the design, fab, testing, and packaging operations involved with electronics systems and still have complete control.The most practical approach is to make sure we design electronic systems with security and trust in mind from the start. We need to provide security features up front throughout the extended supply chain – into the design flow, fab flow, and out into the field to make it easier and faster for anyone at any point to verify the authenticity of an electronic system as well as identify and mitigate a problem. Finally, we have to remember that we are all in this together – designers, developers, packaging facilities and fabs. We can’t just blame semiconductor manufacturers or any other single entity. As a result, we must be cooperative and collaborative by focusing on this issue as a consortium. Everyone in this ecosystem must come to the table, share best practices, establish standards, and initiate best practices for device to system authentication.SEMI: How can SEMI and the SEMI Electronic System Design (ESD) Alliance help the industry meet these challenges?Tehranipoor: It’s certainly of utmost importance for members of organizations like SEMI and its ESD Alliance committees to jointly develop and adhere to standards or guidelines that establish hardware root of trust across all participants in the global supply chain. At the same time, such alliances should make it a high priority to protect each company’s intellectual property (IP). Collectively, we need resolutions that allow us to develop unique IPs and more easily trace, identify, and verify the authenticity of electronics systems as they flow throughout the end-to-end electronic supply chain. Great efforts are under way and progress is being made. But it’s not enough. Clearly, more needs to be done to establish root of trust standards at the chip level.I can’t emphasize enough the importance of consortia like the SEMI ESD Alliance to create an environment where industry, government, and academia can come together, share best practices and even case studies on how they handled security vulnerabilities and breaches. We understand that not everyone wants to share their security problems, vulnerabilities, or attack surfaces, but learning from each other’s experiences can have a tremendous impact on industrywide progress. If you don’t know what you need to address, you won’t be able to address it when it happens.I also encourage organizations like SEMI to create standards or guidelines that reduce the complexity of microchip designs for security purposes. Realtors often say there are three things to consider in finding a home that will appreciate in value: Location, location, location. To build more secure electronics systems, my mantra is: Automation, automation, automation. Complexity is the enemy of security. By using automation to simplify security mechanisms and detect inconsistencies, it will be easier to find and fix security problems, not to mention lower costs at the same time. SEMI: What will an attendee take away from your talk at SEMICON Taiwan?Tehranipoor: I have a large team of researchers who day and night spot vulnerabilities by attacking and assessing data from different electronic systems set up in our labs. Attendees will see real-world examples and lab animations that show how electronics systems can be hacked most anywhere across the supply chain. They will also learn about step-by-step security solutions we have developed at the microchip level. We need to do a better job of protecting the security of our semiconductor assets and the electronic solutions or services they power. My call to action will be that we need to invest more in research and foster an environment of more open trust and cooperation. We can do this by bringing together different countries, companies, and organizations in the microelectronics ecosystem to overcome this major challenge.Dr. Mark Tehranipoor is currently the Intel Charles E. Young Preeminence Endowed Chair Professor in Cybersecurity at the ECE Department, University of Florida. He is currently serving as Director for Florida Institute for Cybersecurity Research (FICS), National Microelectronics Security Training Center (MEST), CYAN Center of Excellence, and ECI Transition Center. He also serves as Program Director of Cybersecurity for UF Herbert Wertheim College of Engineering. His current research interests include IoT security, hardware security and trust, and reliable circuit design.Samer Bahou is senior manager of corporate communications at SEMI.