Synopsys

The EDA industry has accelerated and growth has moved into double digits for the last number of years. Our forecast for 2023 is that we'll have another double-digit growth year to about $13 billion from more than $11.5 billion in total industry revenue last year.

Jay Vleeschhouwer, managing director of Griffin Securities, has followed the EDA industry as a leading financial analyst for 25 years and is a popular speaker at the annual Design Automation Conference. Vleeschhouwer discusses his DAC presentation The State of EDA: A View from Wall Street.

Charles Shi, Principal, Senior Analyst, Needham & Company, LLC., recently offered an upbeat assessment of the electronic design automation (EDA), silicon intellectual property (IP) and services industries, or what SEMI refers to as the electronic system design (ESD) ecosystem.

ESD Alliance’s License Management and Anti-Piracy (LMA) Committee has worked with member companies Cadence, Siemens EDA and Synopsys to develop a protocol for use with software license management systems to provide strong protection against piracy by defining how servers can be uniquely identified.

Vikram Bhatia, Director of the Synopsys Cloud Go-to-Market and Product Strategy, discusses leveraging a flexible, pay-per-use approach to fuel the next phase of semiconductor innovation - bring your own cloud (BYOC) and software as a service (SaaS) deployment model.

As a leading analyst covering the electronic system design segment, Laurie Balch is well steeped in identifying and analyzing technology trends and forecasting new market opportunities. Laurie is now President and Research Director at Pedestal Research.

In the early 1990s, engineers of varying degrees of skill with a powerful PC set up shop designing and selling blocks or libraries of reusable components with a defined interface and behavior. These blocks, known as intellectual property, or IP, were then (and still are) integrated into a larger design. While the new market segment created excitement and new opportunities, it also was untested and created uncertainty. Many fledgling companies failed. It’s a different story today. Arm, as well as Cadence and Synopsys, are silicon IP suppliers and the segment’s yearly revenue tops $4 billion, a long way from those early garage startup days. ESD Alliance member CAST, a silicon IP provider since 1993, participated in the remarkable growth and impact on the semiconductor industry. Nikos Zervas, CAST’s CEO, and I discuss those early days of the IP business and what’s ahead. Smith: What were the early days of silicon IP like? Zervas: In those early Wild West days of IP, vendors and customers both wanted to benefit from IP, but nothing was standardized, and people just tried things to see if they worked. The perceived barrier to entry was low: hundreds of IP companies sprang up thinking they only needed RTL coding skills and tools, an FPGA to prototype, and a few thousand dollars to invest. IP deliverables, quality standards, and business practices varied from vendor to vendor and over time. Risk was high, and there are many horror stories of re-spins or market failures due to faulty IP cores. Smith: How has the silicon IP market changed from its early days? Zervas: Firms delivering high-quality IP and providing outstanding customer support survived. Others disappeared. Eventually the industry centered around a reasonably common sense of IP requirements and quality and a consistent set of business practices. IP product complexity has driven upwards as SoCs have grown. The largest ASICs used to approach a few million gates; today they’re hundreds of millions, and the granularity of IP has evolved from small functions to pre-integrated subsystems. Early on, a designer doing image processing might license individual functions like a Finite Impulse Response (FIR) filter or a Discrete Cosine Transfer (DCT) block. Today, instead they would license a complete JPEG compression core containing those functions and more, or even a complete black box subsystem streaming processed, stabilized, compressed video over Ethernet. IP selection criteria have also changed. Early IP was handcrafted to eliminate every extra gate, as being a few thousand gates smaller was a killer advantage in the era of 180nm ASIC processes. Today, at 7nm or 5nm process, tens of thousands gate differences are just noise, and it’s usually the reliability, functionality, and performance of an IP core that matter most. Smith: When did the silicon IP market start to take off? What was the driving force? Zervas: By the early to mid 2000s, uncertainty about what IP was and how best to use it – and the early wave of less-than-great providers – were being replaced by increasing acceptance and emerging best practices. The introduction of smartphones, the wild growth of Internet of Things applications, growing automotive system sophistication, and other advances fueled the explosion of the IP market in the late 2000s. In fact, according to the ESD Alliance Electronic Design Market Data Report, revenue from IP licensing today has surpassed the license revenue from front-end EDA tools. This would have been unimaginable in the late 1990s. Smith: How has silicon IP changed chip design? Zervas: Designers today must develop massive, complex systems with an even tighter time to market. Only the higher level of design abstraction and the distributed expertise that silicon IP provides make this possible. But IP also increases the challenge of differentiation: With the same IP available to everyone, how do you design a product that stands out in its market? The answer to differentiation today lies mainly in clever SoC architecture. Delivering better features with superior performance, lower power consumption, or other winning characteristics now depends not so much on perfecting each separate IP block but rather from selecting the best IP for the system’s requirements, integrating those IP cores for clean communication and efficient resource sharing, and other smart system-level decisions. It’s similar to modern building design: Every firm has access to the same materials and tools – concrete, glass, etc. – but only a few produce exceptional buildings. Smith: It seems that are several different business models for IP licensing, such as up-front license fees, subscriptions, royalties, or a combination of these. Do you think the IP market will gradually align around one basic model, or will it continue as is with a variety? Zervas: Different models serve different needs. For example, commodity IP like a SPI interface can’t demand royalties, but unique, leading-edge IP – like a 112Gbps SERDES – still can. I believe the market will continue with different business models, though the number of different models may shrink and their terms begin to align. About Nikos Zervas Dr. Nikos Zervas is the chief executive officer of CAST, Inc. He co-founded image and video compression IP developer Alma Technologies in 2001, and led the bootstrapped firm as chairman and CEO for nine years before joining CAST. He was a founding member of the Hellenic Semiconductor Industry Association and served on its board for several years with responsibility for strategic planning. He is a senior IEEE member and member of the Technical Chambers of Greece, had contributed to the GSIA's IP Working Group, and has published multiple technical papers on data compression design and related topics. Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community.

Alameda, Calif.-based Verific Design Automation, a member of the ESD Alliance, made its name in the electronic system design and semiconductor industry supporting companies ranging from startups to billion-dollar industry leaders such as Synopsys, Cadence, Siemens EDA, Xilinx, Microchip, NVidia, Infineon, Qualcomm, Renesas and Samsung. Its software is used as the front end to design automation tools such as synthesis, simulation, debug, and formal verification. I spoke with Verific president and COO Michiel Ligthart about homegrown and open-source EDA tools and other recent trends in chip design. Smith: What trends are you seeing in chip design? Ligthart: Semiconductor companies are starting to build a portfolio of intellectual property, including homegrown electronic design automation (EDA) tools, that they want to keep secure and differentiated from their competitors. The increased interest in internally developed and supported EDA tools is a trend we started to see about two years ago. It’s not simulation, synthesis or place and route (P R). Instead, it’s pieces of a chip design flow optimized for a company’s specific needs. In the past, a semiconductor company would either standardize on one EDA company’s chip design flow or mix and match best-in-class tools from different vendors. The common denominator was that they used off-the-shelf products. If they had a specific requirement, they went to the EDA provider for assistance. In today’s competitive landscape, semiconductor companies are figuring out ways to diversify themselves and their design flow became a way to do so. They may not build their own P R tool, but they will look at building their own power domain approach, for example. Is this a widespread trend? It could be. We hear about it within end-user applications ranging from 5G and AI to data center processors and there are probably others we don’t hear about. Power optimization is an example of the kind of specific internal need being addressed. Smith: What are your thoughts about open-source EDA tools? Ligthart: Our industry supports open source already with language reference manuals (LRMs) for VHDL, SystemVerilog, Unified Power Format (UPF) and the RISC-V Instruction Set. The LRMs and the instruction set are free. Moving to the development of actual tools becomes a question of who will implement, support and maintain the tools. Implementation is expensive. The Big Three (Cadence, Siemens EDA and Synopsys) invest about 35 to 40% of top-line revenue into R D. For smaller EDA companies, this number is even higher. The industry may come up with a business model that will have open-source components as well as a way to fairly reimburse companies that make these tools freely available. I have not seen it yet. Smith: Business Insider reports that Verilog HDL is among the top 10 tech skills that companies are desperate for their employees to learn right. Does Verific get asked about Verilog training? Ligthart: No. Our customers are experienced users. Nonetheless, it was great to read that article and it suggests the semiconductor industry is healthy, growing and hiring talented engineers. Smith: If an entrepreneur asked you for advice about starting an EDA or IP company, what advice would you provide? Ligthart: I would tell the entrepreneur to focus on the problem the startup is solving. Stick to the company’s core competency and try not to build in-house what can be purchased from a reputable supplier. In the end, it will save time and jump-start the development effort, and the engineering budget can be allocated to the startup’s core competency. The external supplier presumably has years of product validation, which brings a major QA gain. About Michiel Ligthart Michiel Ligthart, president and COO of Verific Design Automation, has an extensive background in engineering, product marketing and general management. Prior to joining Verific, Ligthart was vice president and general manager of West Coast operations for Theseus Logic, a startup in asynchronous logic. Before that, he spent eight years with Exemplar Logic in engineering and marketing roles. Ligthart started his career with Philips Research Labs in California and was a visiting scholar at the Center for Integrated Systems at Stanford University. He has a Master of Science degree in Electrical Engineering from Delft University of Technology, the Netherlands. Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community.

AI vs. energy. Quantum for everyone. Biofabrication of human organs on a mass scale. Slowing advancements from Moore’s law.In the midst of a market dip, optimism reigned as keynote and AI Design Forum speakers addressed both looming challenges and explosive market opportunities during July 9-10 presentations at SEMICON West 2019 in San Francisco. SEMICON West again proved to be a magnet for visionaries who laid out the path to electronics innovation over the coming years.“The current business environment demands that the industry looks ahead toward issues that need attention sooner, not later – especially since we are approaching a once-in-a-generation inflection point that has the potential to be a $10 trillion opportunity,” observed SEMI Americas president Dave Anderson.Market forecasts punctuate the point: The microelectronics supply chain is on the verge of what has the potential to be the longest-lived electronics era.“Inflection points like this are rare, but not unprecedented,” Anderson added, citing 2007 as the inflection of the growth curve from new technologies that led to last year’s historic high semiconductor sales.SEMICON West squarely focused on the future, with a number of industry leaders noting that chip, tool and materials makers need to look beyond their immediate suppliers and customers in developing strategic partnerships. Dr. Cliff Young, data scientist with the Google Brain Team, for one, invited semiconductor and equipment firms to explore chip codesigning opportunities with his Google.The recently formed Quantum Economic Development Consortium – and its 50 members including Boeing, Google and IBM – debuted roadmapping activities devoted to the pursuit of U.S. leadership in the rapidly emerging global quantum computing industry. IBM’s Jeff Welser showcased the IBM Q Computer model built upon decades of semiconductor industry advances. Markets that could see staggering leaps from a quantum computational capacity include automotive, medical, financial and energy. Today, anyone can dabble with the future quantum computing capabilities by connecting online with IBM’s 16-qubit quantum computer. Dr. Aart de Geus, chairman and co-CEO of Synopsys, suggested that software and other programming tends to develop more quickly if it is open sourced. He recommends an open source model that allows semiconductor and equipment companies to work together in the cloud to speed chip development.Nate Baxter, TEL development and production group general manager, advocated sharing big data with competitors in pre-competitive spaces to ensure data quality, improve measurement and solve problems faster. The key is security. “Yes, we can share data while protecting it,” he said. “We’re quickly seeing opportunities that we didn’t know existed.”Gary Dickerson, Applied Materials president and CEO, said that embedding artificial intelligence (AI) in chips will drive significant long-term industry growth by processing far more big data computations much faster than humans can.That is, if there is enough electricity. Almost invisibly, AI-enabled machines already are crunching massive amounts of data while gulping power in the process. As AI use rapidly expands, current power grids will be stressed as never before. Dickerson added that speed of innovation, societal acceptance, security and safety will guide how well and quickly AI is adopted. A potential hurdle, however, is sustainability. He warned power constraints could be “very high” and a “barrier to AI adoption if we don’t drive innovation” in substantially reducing the power draw of power-hungry AI chips.Of the five members of a venture capitalist panel, four agreed that Moore’s Law as we knew it is dead. The promising news is that the average age of a first-time mobile phone user is 10, more than 40 percent of the world population is now under 25 and about to wield considerable market influence, and 5G is on the cusp of helping connect trillions of devices. AMD CEO Lisa Su noted “there’s a tremendous amount of innovation yet to come” from microarchitectural advances, chiplets and die stacking, and heterogenous platforms.And there’s nothing more innovative – or intriguing – than regenerating human organs in mass volume. Legendary inventor Dean Kamen laid out his well-funded plans to biofabricate the viscera of human existence but warned of two crucial missing pieces – scale and talent. “I’m here at SEMICON West to beg for high-tech’s help in getting artificial human organs out of labs and ramped up for volume manufacturing and widespread distribution,” Kamen said during his keynote. “The basic science already exists, but researchers can’t bring it to scale like Silicon Valley can.”The talent Kamen needs to fulfill his dream will come from the pool of skilled workers the microelectronics industry is feverishly working to recruit to make good on its own ambitions. As if on cue, SEMI endorsed Kamen’s FIRST Global program, establishing a united effort to encourage young people worldwide to pursue engineering careers. “Together, we can better help provide a path to success for generations to come,” SEMI’s Anderson said.Scott Stevens, SEMI

Would you buy your next hotdog in parts, from un-coordinated suppliers? For example: Get the bun from a baker, the sausage from a butcher, mustard and/or ketchup and veggies from the nearest supermarket? If yes, you may find the sausage being too small, the veggies too big for the bun, and, when you finally finished adding mustard/ketchup and start eating, you may “enjoy” a cold sausage on a soggy bun!This “hotdog example” is just a very simple way to highlight the advantages of a well-coordinated semiconductor supply chain. What may be a few dollars and cents wasted in this hotdog purchase, can become millions of dollars lost to delays and inefficiencies during the roll-out of a new electronic system.Complexity is Increasing the ChallengeThe very innovative semiconductor industry is continuing to develop more complete and complex building blocks for electronic system solutions, with the intent of making our customers’ lives easier. However, every new technology takes increasingly more time for technical and business interfaces to mature before all the semiconductor supply chain members can serve customers in a smooth, efficient and cost-effective manner. In particular, coordination between design and manufacturing has always turned out to be in the critical path.SEMI, the manufacturers’ trade organization, and the Electronic System Design (ESD) Alliance, representing electronic design automation (EDA) tools vendors, developers of intellectual property (IP = ready-made building blocks for ICs) and IC design service providers, both recognized these challenges. Late in 2018, these two industry organizations decided to jointly address this painful, costly and often a very frustrating, yet critical path and became Strategic Association Partners, The goal is to establish a well-coordinated semiconductor supply chain.To make the value propositions of this partnership highly visible and demonstrate the first joint accomplishments, SEMI’s well-known SEMICON West conference and, in its first year, ES Design West, will be conveniently co-located in San Francisco’s Moscone Center from July 9 to 11, 2019. The synchronized schedules and geographic proximity of these events not only outlines the multi-faceted interdependence of manufacturing and design but encourages and enables conference attendees to do, what previously would have been viewed as “forming cross-border relationships.” It’s a new word now — please join the path to success and expand your network!Navigating SEMICON West and ES Design WestJust in case you are not yet planning to come to San Francisco early July, please check the Agendas-at-a-Glance for SEMICON West and ES Design West, to see how broad and valuable these parallel conferences are for your business. In addition, every customer, partner and semiconductor industry supplier can, from July 9 –11, walk from one conference section to the other, arrange face-to-face meetings, in dedicated meeting rooms, with representatives from both camps and discuss, from the first project planning step to the final production ramp-up, the many topics that need to be coordinated across parts or the entire supply chain to minimize delays and/or cost over-runs.Who Will Lead the Discussions?Conference attendees can, in addition to meeting many important supply chain partners face-to-face, hear about the latest technologies and market trends from key executives in our industry. Featured speakers are: David Pellerin, Head of Global Business Development, Amazon Web Services Lisa Su, President, and CEO, AMD Gary Dickerson, President, and CEO, Applied Materials Laurent Le Faucheur, Principal Engineer, Digital Signal Processing and Machine Learning, Arm, Ltd. Renee St. Amant, Ph.D., Research Engineer in Emerging Technologies and US Innovator of the Year, ARM Dean Kamen, President DEKA Research Development, Founder First and First Global Jeffrey Welser, Ph.D., Vice President and Lab Director, IBM Research-Almaden Dean Drako, President and CEO, IC Manage, Inc. Oreste Donzella, Sr. VP Chief Marketing Officer, KLA Corporation Prakash Narain, President, and CEO, Real Intent, Inc. Aart de Geus, Chairman, and Co-CEO, Synopsys, Inc. Manish Pandy, Fellow, Synopsys, Inc. Nate Baxter, General Manager, Development and Production Group, TEL US Like in previous years, SEMICON West and ES Design West offer a range of special features, addressing Smart Manufacturing, Smart Transportation, Smart MedTech and Smart Workforce development in dedicated pavilions as well as an AI Design Forum. Also, the many exhibitors from both camps will give conference attendees convenient opportunities to get to know new supply chain partners and/or refresh long-term business relationships. Search for the exhibitors you want to meet early July here. Questions to Ask for a Well-Coordinated Semiconductor Supply ChainIf I may, I would like to ask my many friends in the manufacturing camp to spend some time in the ES Design West section and ask the exhibitors a few questions, like: What can you do to get me to profit faster? To reduce development and unit cost? To improve yield, product quality, and reliability? When can you visit my team to discuss how your company can contribute to our goals?Vice versa, I would like to encourage my friends in the design camp to spend time in the SEMICON West section and ask exhibitors what their companies offer. When talking to manufacturers of IC, passive components or circuit boards, assembly and test houses, please ask very specific questions like: How can we help you reduce iterations between you and your customers? How can we help to improve IC test programs? How can we increase the throughput of your manufacturing equipment? How can we apply machine learning (ML) and Artificial Intelligence (AI) to minimize equipment downtime, improve yields and/or shorten production ramp-up?I can assure you that you’ll not only win great friends “across the border” but will be very impressed by the expertise you’ll find in the other camp and the willingness for and benefits of cross-border cooperation.I look forward to meeting you at SEMICON West and ES Design West. Also, if your schedule allows, mark your calendars for the June 12 MEPTEC Luncheon at SEMI in Milpitas, June 18 for the GSA’s Silicon Summit in Santa Clara and June 25 to 27 for the IMAPS SiP Conference in Monterey, CA. Hope to see you at one or all of these important events!Article originally published in 3D InCites. Herb Reiter is president of eda 2 asic Consulting.