Japan

Each quarter SEMI recognizes the longstanding commitment and support of member companies as they reach a new membership milestone.

On April 16, Japan prime minister Shinzo Abe expanded the state of emergency beyond Tokyo, Osaka and five other prefectures to all 47 prefectures nationwide in an effort to curb the spread of COVID-19.As I reported two weeks ago, SEMI Japan initiated communications with all prefectural governments on April 10. Since then, the government’s concerns over the virus’s impact on the semiconductor supply chain have heightened. Prefectural Governments Plan No Restrictions on the Semiconductor Supply ChainOf the 47 prefectural governors I contacted, urging them to classify the semiconductor industry as an essential business, 40 confirmed in follow-up calls through April 20 that they have no plans to restrict operations of the semiconductor industry and supply chain companies in their jurisdictions. Those prefectures include Aichi, Akita, Aomori, Chiba, Ehime, Fukui, Fukuoka, Fukushima, Gifu, Gunma, Hiroshima, Hyogo, Ishikawa, Iwate, Kagawa, Kagoshima, Kanagawa, Kochi, Kumamoto, Kyoto, Miyagi, Miyazaki, Nagano, Nagasaki, Nara, Niigata, Oita, Okayama, Okinawa, Saga, Saitama, Shiga, Shimane, Shizuoka, Tochigi, Tokushima, Toyama, Wakayama, Yamagata and Yamanashi.However, the Aichi, Iwate, Kumamoto, Nagasaki, Oita and Saga governors cautioned they will reconsider restrictions on the semiconductor and other industries if COVID-19 transmissions worsen.The seven other prefectures including Tokyo and Osaka are not planning to respond to our request until they have COVID-19 transmission mitigation plans in place. In the meantime, SEMI Japan will continue to encourage prefectural governments to allow semiconductor supply chain companies to continue to operate unrestricted, a move consistent with current national policy for novel coronavirus disease control.Japan’s Economic Stimulus PackageOn April 6, a day before prime minister Shinzo Abe declared the emergency state for seven prefectures, he announced an unprecedented 108 trillion yen ($989 billion) stimulus package[1]. The package, equivalent to about 20% of the Japan’s economic output, dwarfs the 56 trillion yen in aid passed in the wake of the 2008 financial crisis.The first phase of the relief package seeks to halt job losses and bankruptcies, while the second will support a V-shaped economic recovery. For businesses, phase-one aid includes: Subsidies for firms that keep workers on the payroll. Large companies keeping at least half of their workers on the payroll and small and medium sized businesses that continue to pay at least two-thirds of their employees are eligible for the payouts. One-year deferment of income and regional tax payments for companies hit by the virus Property tax reductions of 50% in fiscal year 2020 for small and medium sized companies with sales that have fallen by at least 30%, and property tax exemptions for those with sales suffering contractions of at least 50%. Interest-free loans requiring no collateral for small and medium sized companies Low-interest loans available to medium sized and large companies through the Development Bank of Japan and Shoko Chukin Bank The second phase of the package, still under development, could include incentives to recharge consumer spending and tourism and subsidies for regional economies once the coronavirus has been contained.Japan COVID-19 Stimulus and Support ResourcesThe economic support measures planned by the Japan Ministry of Economy, Trade and Industry (METI) are summarized at https://www.meti.go.jp/english/covid-19/index.html#10.Prefectural and municipal stimulus and support information is summarized in Japanese at https://j-net21.smrj.go.jp/support/tsdlje00000085bc.html.SEMI Supports Members with COVID-19 ResourcesSEMI international headquarters and regional offices are here to help you, our members. For more information on our webinars, surveys, best practices and other information designed to help you meet the challenges of the pandemic, please visit the SEMI Coronavirus Updates Resources page.[1] The government increased the stimulus package to ¥117.1 trillion after a sudden policy shift to provide cash handouts of ¥100,000 for every individual in Japan. Originally, the plans were to give ¥300,000 to each household that has seen a sharp fall in income due to the virus outbreak.Jim Hamajima is president of SEMI Japan.

It should really be called SOI photonics – not just silicon photonics, quipped Soitec CTO Christophe Maleville at the SOI Consortium Japan event last fall. You’ve got to have SOI for the waveguides. There are megatrends driving significant growth in photonics – and they were all covered at the event. This is the final post in our coverage of the SOI Consortium’s Japan event (thank you for your patience!). It covers the photonics-related presentations by Soitec, Leti, Cisco/Luxtera, GlobalFoundries, Cadence and TowerJazz. Most of these presentations are now posted on the SOI Consortium website – you can access them if your organization is a member of the consortium. By way of reminder, the Japan SOI Symposium was a great success, with both days well attended. In case you missed our previous posts about the event, you’ll want to go back and read them, too. The first post covered the 5G/RF-SOI presentations by ST, Toshiba, Incize, GF, Silvaco and Sitri – you can read it here. The second post on the event covered eight very informative presentations on SOI in IoT and automotive by NXP, Dolphin Design, Leti, Silvaco, Arm, I-fuse and Secure-IC – you can read that here. Note that you can click on any of the illustrations to see enlarged versions. And now without further ado, here are the summaries of the photonics presentations. SOI Enabling Photonics – Ecosystem and Market Outlook – by Aziz Alami-Idrissi, GM Specialty SOI, Soitec. [caption id="attachment_28773" align="alignleft" width="233"] (Courtesy: Soitec SOI Consortium)[/caption] The megatrends in SOI photonics are: 5G (for more bandwidth, HPC, edge quantum computing), data centers (for high data rate transceivers and high-switch bandwidth), sensors (lidar, gas/chemical and gyroscopes) and biosensors (especially for medical). These are driving big changes: the 44% CAGR means the market is growing from a current TAM of about 500M$ to over 4B$ in 2025. One thing that’s really interesting is the expansion of the photonics market into these new fields in the next few years. While in 2019 90% of the photonics market served data center applications (the other 10% is for long haul), in 2025 optical I/O’s will account for over a third of the photonics market TAM. The other applications making an impact include AI, quantum, lidar (which will move into high-volume manufacturing in 2024) and medical sensors (hitting high-volume in 2023). For its part, Soitec is strengthening its portfolio with 8” and 12” large product coverage, new product sampling engaged, and extended features including newer engineered layers and RF immunity. Advanced Silicon Photonic Solutions Leverage SOI Technology – Eleonore Hardy, Business Development Manager, Silicon Photonics, CEA-Leti [caption id="attachment_28769" align="alignright" width="358"] (Courtesy: Leti SOI Consortium)[/caption] Leti helps companies make photonics products they can bring to volume foundries, explained Hardy. (btw, they’re presenting 21 (!) papers – including 5 invited – at PhotonicsWest 2020. Read about that here). You want to do integrated photonics to bring down costs, reduce power consumption, and scale (for higher volumes and reduced footprint). There are essentially three substrate choices: InP, SiN or SOI. SOI uses CMOS processes, so it’s low-cost and can be used in high-density photonic integrated circuits. What about the laser? Leti has developed III-V on silicon bonding, so you can have the laser on 4” III-V with a 300mm CMOS process (this is what Intel’s doing). They’re moving to 300mm wafers, 3D and advanced packaging. While communications is the big application realm, Leti is also applying photonics in automotive, medical, environment and computing. In the computing realm she gave the example of the European QuantERA SQUARE (Silicon Photonics for Quantum Fibre Networks) project for which Leti is doing the quantum emitter for absolute security and computing, wherein the transceiver/receiver for quantum cryptography integrates a hybrid III-V on silicon pump laser. Other examples of their work include miniature, low-cost and agile lidar for automotive and industrial applications (they’re working on a beam-steering emitter for an optical phased array). GlobalFoundries Silicon Photonics Solutions for Wired Infrastructure – Anthony Yu, VP, GF [caption id="attachment_28770" align="alignleft" width="684"] (Courtesy: GlobalFoundries SOI Consortium)[/caption] GF is giving their photonics business a big push. Optical interconnects are the future, said Yu, so they’re putting a lot of money into it. With data streaming multiplying by 3x/year and a current foundry TAM of $63 billion, the opportunity is huge. Fab 10 in Fishkill runs their 90WG process on 300mm wafers. A new process, 45CLO (also on 300mm) for O and C bands is going into the Malta fab. A big focus here are optical transceivers that convert RF signals to light. They see RF on SOI in a monolithic solution is needed to serve 100Gbs applications. They’re also moving to co-packaging optics: the packing technology will surround it with photonic chiplets. Customers have indicated that pulling the signals off the chips is limited by power, so they’ve worked hard on the fiber attach with MEMS and packaging technology for co-packaging. GF relies on substrate providers for high-quality SOI, and they have a world-class development team, he concluded. Integrated Electro-Photonics Design Platform – A multi-physics, multi-fabrics system design solution – Scott Li, Sr. AE Manager of Custom IC Platform, Cadence [caption id="attachment_28771" align="alignright" width="374"] (Courtesy: Cadence SOI Consortium)[/caption] This talk focused on photonics design challenges and solutions – including the CurvyCore™-based PDK for waveguide creation modal properties calculation that Cadence will soon be announcing. It’s a math-based engine that generates complex curvy shapes to support photonics. The first design challenges, said Li, are at the circuit level: how to do the schematics. The detailing tools, timesteps management and circuit simulation need to give the user the best performance. Cadence is working in close collaboration with a company called Lumericable on this. The next set of design challenges come at layout – especially generating curvilinear layout for any shape so that there are no gaps in connections. This is where CurvyCore comes in, fully automating layout and making it easy to modify. This includes place route, DRC and LVS for curvy shapes. The final challenge is at the system level. There is work to do here, but Cadence is collaborating closely on solutions with key partners. The ultimate goal is for photonics layout and editing to be available with all the features designers get in electronics editing. Silicon Photonics for High Volume and High Performance Optical Interconnects Applications – Thierry Pinguet, Technical Leader Engineering, Cisco /Luxtera [caption id="attachment_28772" align="alignleft" width="396"] (Courtesy: Cisco/Luxtera SOI Consortium)[/caption] Over the last decade there’s been steady growth in optical high speed interconnect solutions, mainly driven by HPC, enterprise, and especially the hyperscale datacenter. The largest volumes are for intra datacenter interconnect (between servers). Now mobile applications for backhaul are also driving volume for high speed optical interconnect for 5G network implementation. ASICs and photonics are getting closer as the industry moves to put them in the same package. But everybody does silicon photonics differently (even within Cisco). Luxtera tries to use the same infrastructure as electronics, but patterning is still a challenge: it’s not 90o “Manhattan” style. The wafers are no problem – they work with leading wafer suppliers like Soitec and SEH. They have explored a “double SOI” substrate (like a mirror), which showed large insertion loss improvements in grating couplers . For the electronics and the laser (MEMS), they do a micropackage, although at one point they also did monolithic integration. For better performance, they’re moving to TSVs. A hot topic is ASIC and photonics co-packaging. You can use optical tiles, but then the light is remote, like a power supply. No matter how you do it, though, the bottom line is that silicon photonics is the only way forward for the data center. PH18: World’s First Open Commercial Silicon Photonics Process and PDK from TowerJazz – Masanobu Kumazaki, Engineer, TowerJazz. This presentation was given in Japanese without translation into English, and is not available on the consortium website. But the slides showed at the event indicated that their PH18 is the world’s first open commercial silicon photonics offering. For optical transceiver components, silicon photonics provides another opportunity for a specialty foundry. It is a high-growth market. The TowerJazz offering is 220nm SOI, and uses standard EDA tools from Synopsys, Cadence and Mentor for design flow.

Here is our second post about the SOI Consortium’s Japan Symposium this past fall. This will provide summaries of eight very informative presentations on SOI in IoT and automotive by NXP, Dolphin Design, Leti, Silvaco, Arm, I-fuse and Secure-IC. There’s a lot of content to summarize, so this post is about twice as long as those we usually do. But you’ll want to read right to the end, for sure! In case you missed our previous post on the 5G/RF-SOI presentations given at the Japan event, you can read it here. Our next and final post on the Japan event will cover photonics presentations by Cisco/Luxtera, TowerJazz, GlobalFoundries, Leti, Cadence and Soitec. By way of reminder, the Japan SOI Symposium was a great success, with both days well attended. If your company is a member of the SOI Consortium, you can now access most of these presentations on our website. You can also click on the illustrations in this post to see them in enlarged versions. [caption id="attachment_28106" align="alignleft" width="366"] (Courtesy: NXP SOI Consortium)[/caption] The IoT World Enabled Through SOI - Jon Cheek, NXP Sr. Director, Front-End Innovation For NXP, FD-SOI introduced the ability to easily add different functionalities to the technology node like ULP, eNVM, support for high-voltage and embedding RF. For them, said Cheek, it’s about the range, and with adaptive back bias, you can “get crazy”, so you can really achieve amazing things. In fact, they think they now have the lowest leakage SRAM in the industry, thanks to body biasing. The i.MX 7ULP is finding significant success in wearables. Their “crossover” chips are the latest beneficiaries of FD-SOI with body biasing. The “new normal”, they offer huge improvements for real-time operating systems – which is of course key for edge computing. (As you can imagine, the audience was intently taking notes throughout -- this was a really excellent talk!) It also is great for machine learning, as it is designed to unlock the potential of voice-assisted end nodes. The IP they needed is now available from multiple vendors, noted Cheek, such as Tensilica and VeriSilicon. Another key play will be in visuals for industrial computing. He concluded by observing that the automobile is the ultimate IoT machine, with 10x the amount of code now found in leading edge airplanes. That’s where the i.MX8 and 8X come in. [caption id="attachment_28104" align="alignright" width="323"] (Courtesy: NXP SOI Consortium)[/caption] High-Voltage SOI – Enabling Automotive- NXP Jon Cheek gave this presentation on the second day of the Japan event. Long-time followers of SOI will know that NXP has been excelling in high-voltage (HV) SOI for well over two decades now (including the pioneering work done by Philips, now part of NXP: their EZ-HV SOI patent dates back to 1993). It’s probably safe to say that NXP's SOI-based automotive chips are used by virtually every carmaker on the planet. HV follows well behind the leading edge – it’s currently mostly around 130nm (the limits are related to metalization). Reason #1 it’s on SOI? SOI-based technologies are incredibly reliable, especially in the automotive culture targeting the three zeros (0 emissions, 0 accidents and 0 time wasted). Today’s car manufacturer’s are going to a distributed environment, and SOI still provides a huge advantage, making parts that are smaller, lower power and more reliable – so it drives a lower BOM for automakers.In conclusion, said Cheek, NXP’s leadership through SOI innovation enables scalable solutions, high voltage analog integration, sensor integration, and reliable safe passenger experience. [caption id="attachment_28101" align="alignleft" width="432"] (Courtesy: Dolphin Design SOI Consortium)[/caption] Improving SoC Energy-Efficiency with Dolphin Design Platforms – Nicolaus Gaude, BizDev Product Marketing, Dolphin Design Dolphin has a series of platforms, techniques and IP for increasing speed and drastically improving energy efficiency in SoC design. Gaude introduced their Speed Platforms, which include a Power Management Platform and a Processing platform, both of which make dramatic improvements in energy efficiency. The Power Management Platform keeps control of power management from architecture to design, resulting in a 10x improvement in energy efficiency. The Processing Platform comprises configurable RTL clusters for best-in-class (100x) energy-efficiency. Gaude then turned to the Dolphin’s Adaptive-Body Bias (ABB) IP for breakthrough energy-efficiency with FD-SOI. This is real-time, “on-the-fly” body biasing: the IP does it all. It is silicon-proven on GlobalFoundries’ 22FDX with Arm cores and Invecus standards cells SRAM, with breakthrough energy efficiency. [caption id="attachment_28108" align="alignright" width="363"] (Courtesy: Silvaco SOI Consortium)[/caption] Platform Infrastructure for SOI-IP Ecosystem – Thomas Blaesi, VP of Global Marketing, Silvaco The massive use of IP is both an advantage and a challenge, began Blaesi. There are solutions out there, but they are disconnected. Typically SoC/IP designers, IP librarians and support folks use various systems, while procurement, finance and legal use others. This is a problem for both the providers and the consumers of IP. Silvaco has a new system called Xena that centrally organizes all IP data: it’s an IP repository for tracking accounts, products, contracts, devices, support, compliance and reporting. One of the first beneficiaries of Xena will be the SOI ecosystem, as providers of SOI IP are already signing on. Beyond the organizational advantages, Xena has patented “finger printing” and “DNA analysis”, so there is a digital representation of each IP on an SoC that can’t be reverse engineered. Each fingerprint contains list of unique signatures of each file in an IP or SoC. A file’s unique signature is created from the entire file content, and that signature is guaranteed to be unique to that content. It enhances support for all versions of common design files: hard IP, soft IP, and embedded software. Because it’s cloud or enterprise based, it will be particularly useful for large organizations. Fingerprinting and DNA analysis are vendor agnostic, universal, and easy-to-use tools and methodologies for IP lifecycle management, he concluded. [caption id="attachment_28103" align="alignleft" width="463"] (Courtesy: Leti SOI Consortium)[/caption] Ultra-low power, FD-SOI based IP, in the space of IoT, Health Care, Smart Connectivity 5G – Michael Tchagaspanian, EVP Industrial Partnerships, CEA-Leti This presentation began with a review of the explosion in devices with IoT and related investments, then connected all the ways in which innovations powerhouse Leti is contributing – from the SOI wafer level to the chip level – which is to say practically everywhere! Especially hot topics in FD-SOI included: the roadmap to sub-10nm; CoolCube monolithic 3D; new embedded memories; power amplifiers; Ultra-Wide Range DSP; smart sensing local processing (including haptics, imaging, infrared advanced processing); local processing with edge AI; and spike coding for deep neural networks. He showed information on two always-on/on-demand transmission 28nm FD-SOI IoT test chips that taped out in mid-2019: the Warrior and the Samurai. And finally, he covered silicon-proven IP that Leti has for FD-SOI including power management blocks, lots of RF IP (including low-power RF wake-up), sensor interfaces, clockless network-on-chip and new SRAM technologies. These and more will be covered at the next Leti Innovation Days in Grenoble (June 2020) – during which in parallel, btw, there will also be a European SOI Summit hosted by the SOI Consortium. [caption id="attachment_28099" align="alignright" width="475"] (Courtesy: Arm SOI Consortium)[/caption] FDSOI Enablement for a Total Compute Future – Manuj Rahor, Director Emerging Technologies Product Marketing, Arm Subtitled A perspective on system optimization with Arm FDSOI IP, this presentation reviewed how Arm is enabling system gains through optimization across IP boundaries. This is work happening in the Arm Artisan Physical Design Group (PDG), which provides logic, memory and POP (processor optimization package) IP as well as various products to help ease implementation challenges for advanced nodes. In this case the focus is on Total Compute enablers on Samsung 28nm FD-SOI (called 28FDS) – specifically three building blocks recently launched on FD-SOI. The first is the 128Mb Wide Capacity embedded MRAM (an eNVM to replace eFlash) compiler for storage delivered to Samsung in July `19. It was demonstrated in silicon in the Musca-S1 Smart IoT Device Demonstrator on 28FDS, an energy efficient IoT device with eMRAM secure boot on-chip storage. [Read our coverage from March 2019 here.] The second is a novel design developed with Spin Memory. It recently taped out on 28FDS and is slated for delivery in 2020. Adding an “Endurance Engine to the eMRAM that was delivered in 2019, the ARM-Spin innovation delivers RAM-like performance with increased speed and endurance. What’s at issue here is a change in use cases. Use cases served by eFlash were not written to that often; now with sensors (as in IoT) that continually gather and write data, eFlash endurance is not sufficient. The third is billed as an SRAM replacement compiler. Its MRAM as RAM in A-class systems, with significant energy and performance gains. Again, this is a use-case issue: retention is lower (this is for weeks months, whereas the other solutions are for 10 years). But you can get more RAM than SRAM into the same footprint, so you get a 60% reduction in DRAM traffic and increased performance. Delivery for this is marked as 2020+. [caption id="attachment_28100" align="alignleft" width="294"] (Courtesy: Attopsemi SOI Consortium)[/caption] I-fuse™: A Disruptive OTP Technology – Dr. Shine Chung, Chairman, Attopsemi I-fuse is a disruptive OTP (One-Time Programmable) technology without disrupting a fuse. The goal was a 100x increase in reliability at 1/100th of the cell size and 1/10th the power. It has now been demonstrated in GlobalFoundries’ 22FDX FD-SOI technology for energy harvesting applications. In the OTP IP technologies, explained Dr. Chung, they defied the conventional wisdom of breaking a fuse to maintain a permanent programmed state forever: Attopsemi’s I-fuse™ is actually a “non-breaking” fuse. “I don’t mind to break a fuse, but I do care about breaking a fuse by explosion”, said Dr. Chung. “The I-V curve of programming a fuse beyond the break point actually shows more like an explosion. The anti-fuse OTP also ruptures gate oxide by explosion. On the contrary, I-fuse™ is a disruptive OTP technology without disrupting a fuse.” He concluded, “By using MOS as switches to enable discharging two capacitors, through cell and reference cell respectively, and compare the discharge rates, the resistance in the cell can be determined higher or lower than the reference resistance so as to convert into logic data. The read energy consumed is only 1/100 of the conventional sensing, which is good for energy harvest IoT applications. Eventually most IoT devices will be battery-less.” [caption id="attachment_28107" align="alignright" width="398"] (Courtesy: Secure-IC SOI Consortium)[/caption] AIoT Embedded Security Using FD-SOI – Yan-Taro Clochard, Japan Sales Director, Secure-IC In addition to opportunities, the impact of AI on IoT (aka AIoT) adds new threats to edge devices. Design for security and in-depth security is required, down to the physical layer. For example in automotive, sensors gather data and AI analyzes it – but the enabler is security. The challenge of AI is the increase in data and connectivity with unsecured devices. FD-SOI is a key for Secure-IC’s Securyzer security module: it leveragesFD-SOI properties to secure the AIoT world. It is flexible, and tuned for each customer. Here, FD-SOI enables the creation of physically secure systems, with secure boot and firmware updates, cryptographic services, key management and secure storage.

The SOI Consortium’s Japan Symposium this past fall covered a wide array of topics over two days. The first day was devoted to IP and products for RF and ultra-low-power (ULP) on SOI. The second day covered high voltage and photonics. It will take several posts to summarize all the presentations. In this post, we’ll cover presentations related to 5G. In the next posts we’ll cover IoT/ultra-low-power/automotive and photonics. (BTW, if your company is a member of the SOI Consortium, you can now access most of these presentations on our website.) The Japan SOI Symposium was organized for the 4th time at the Yokohama Landmark Tower (from which there was a fabulous view of Mount Fuji). It was a great success, with both days well attended. The event followed the day after (and in the same location as) Silvaco’s SURGE user event, so there were plenty of opportunities for synergy there. (Samsung Foundry talked about their partnership with Silvaco, for example, and their work together on RF and eMRAM on 28nm FD-SOI.) STMicroelectronics [caption id="attachment_27068" align="alignnone" width="589"] From “5G Deployment Driving RF and SOI Technology Opportunity” (Courtesy: ST SOI Consortium)[/caption] As noted in the ST presentation, 5G standards are getting a big push in the Asia-Pacific region, and by China in particular, which is leaping ahead especially in sub-6GHz. It’s a complex standard, noted John Carey, the company’s director of Digital RF for the A-P region, and it’s disruptive, demanding new silicon architectures and technologies. Next year’s premium phones, he said, will include over $30 in RF components, 40mm2 of which will be based on SOI. ST has been working on RF-SOI for over two decades, and offers a range of technologies and foundry services supported by three high-volume fabs. The key benefits with RF-SOI, he explained, stem from RF FEM integration of switches, LNAs and PAs. RF-SOI technologies are here now and are successful in the markets: ST has a long-term technology roadmap and is making continued strategic investments, he concluded. Toshiba [caption id="attachment_27069" align="alignnone" width="410"] From “RF-SOI Switch LNA for Mobile Applications” (Courtesy: Toshiba SOI Consortium)[/caption] Another long-time RF-SOI user is Toshiba, although this marked their first participation in a recent Consortium event. As Group Manager Kazuyuki Uchida talked about RF techology trends, there was lots of note- and picture-taking in the audience. He pointed out that the character and size of the switch LNA modules are particularly important in the move to 5G. They’ve been leveraging their TaRFSOI(tm) process, which he said achieves the industry's lowest insertion loss, for about a decade now. The latest version, TaRF11 will be launching in Q1 of 2020. TaRF10 integrated the LNA with the switch and control circuitry in a single chip. TaRF11 will feature performance improved by about 25%. Incize [caption id="attachment_27065" align="alignnone" width="405"] From “RF Characterization” (Courtesy: Incize and SOI Consortium)[/caption] During the Incize presentation, the company’s CEO Mostafa Emam affirmed that RF-SOI is a very good business opportunity. Incize works with the complete supply chain. For foundries and wafer suppliers, they measure harmonics and output with very high precision, which is especially critical for switches. For the wafer suppliers, it’s predictive. For the foundries, it’s measuring noise for models and PDKs. While RF may be an art, second tier foundries using Incize services are now able to compete with the first tier players, he noted. He sees trap-rich RF-SOI wafers as being especially important for 5G. GlobalFoundries [caption id="attachment_27064" align="alignnone" width="599"] From “RF Reliability for SOI CMOS Si-based Power Amplifier for 5G applications” (Courtesy: GlobalFoundries SOI Consortium)[/caption] The focus of the GlobalFoundries talk was reliability in RF processes. In 5G, you need technologies that are viable for both mmWave and sub-6GHz across handsets, wifi and automotive, noted Purushothaman Srinivasan (who goes by SP and is a senior member of the company’s technical staff). In SOI, you can stack FETs (which you can’t do in bulk) for PAs, which is a big advantage in mmWave. However, delivering scalable, linear, efficient and reliable RF power technology is more challenging than digital, and requires a holistic, collaborative approach that includes the foundry, the customers and the test equipment suppliers. GF has used its RelXpert simulation tool on aging simulations and lifetime predictions for both their 22FDX and 45RFSOI processes. They have observed good RF model-to-hardware correlation, and have built Safe Operating Maps that provide guidance to RF designs. This first-in-industry RF reliability evaluation provides “highly differentiated” solutions for GF. Silvaco [caption id="attachment_27066" align="alignnone" width="606"] From “RFSOI TCAD Solution” (Courtesy: Silvaco and SOI Consortium)[/caption] Silvaco is a leading EDA provider of software tools used for process and device development and for analog/mixed-signal, power IC and memory design. Their presentation began with a review of recent updates to their TCAD simulation framework, including the TCAD design flow, Victory ProcessTM simulation for speeding up 2D/3D process simulations, and Victory DeviceTM simulation. Under Silvaco’s DTCO – Design Technology Co-Optimization – semiconductor physics are connected to circuit design, recognizing that each technology has specific requirements that need to be taken into account at every stage of the flow. Applications Engineer Sun Tao then continued by showing useful TCAD simulations and analysis of SOI for RF applications. In trap-rich substrate simulations, for example, the Silvaco tools can predict the harmonic balance from the active device, device biasing and substrate, all of which can be co-optimized using Victory Process and Device. SITRI [caption id="attachment_27067" align="alignnone" width="305"] From “NB IoT FEM based on SOI” (Courtesy: SITRI SOI Consortium)[/caption] Shanghai Industrial μTechnology Research Institute – aka SITRI – is an international innovation center, focused on globally accelerating the innovation and commercialization of “More than Moore” technologies to power IoT. SITRI Director Wenwei Yang’s talk focused on their narrowband front-end module for IoT (NB IoT FEM). NB-IoT is especially meant to handle small amounts of data from remote places over long periods. There are a lot of players in this market, so taking a “good-enough” approach to performance wherein cost is primordial is key. SITRI’s low-cost NB-IoT FEM integrates everything on a single chip, including the power amplifier (PA) and integrated passive devices (IPD), so packaging costs are low. Putting it on SOI (either trap-rich or high-resistivity) gives them better isolation and simplifies integration. ~ ~ ~ Our next post will continue our coverage of the Japan Symposium. Note: 2019 marks a decade of SOI Consortium events – yes, our first one was in 2009! Because a lot of the presentations in the past were so forward-looking, many of them are still of great interest today. Currently the presentations from 2015 through to the beginning of 2019 are available freely to everyone – and are well worth perusing.

2019 will be a busy fall for the SOI Consortium and our members.First off are the SOI Consortium events in Shanghai and Tokyo, which are very popular indeed. We now have the dates locations locked in, so you’ll want to mark your calendars:Shanghai: 16 17 September 2019, FD-SOI Forum / RF-SOI Workshop. Both days will be held at the Pudong Shangri-La Hotel in Shanghai. The first day will focus on FD-SOI. The second day is all about 5G and RF-SOI. These are huge events – to get an idea of the magnitude, you can read our coverage of the 2018 event. Tokyo: 30 31 October 2019, Japan SOI Design Workshops. This year both days of workshops will take place in the Yokohama Landmark tower. The first day will be devoted to FD-SOI; the second day turns to More-Than-Moore – especially photonics and MEMS. Last year’s workshops were packed with excellent presentations and panel discussions, which we covered here. The SOI Consortium and members will also be giving talks at Semicon Europa, which is being held 13 – 15 November 2019 in Munich, Germany. The programs are currently being finalized. As soon as they’re ready, we’ll be sure to let you know so you can register and/or share the news with your colleagues and clients. But in the meantime, make sure you save the dates.Would you like to check out the presentations given at Consortium events in previous years? If you hover your cursor over the Events tab at the top of our home page, you’ll get a drop-down menu of events for the last five years (we’re working on adding more – we’ve been doing these events for over a decade!). Click through to any past event and you’ll land on a page where you can download most of the presentations that were given there. Of if you’re looking for past presentations given by any particular company, use the search engine at the bottom of any page on our website. S3SYou’ll also find many of our members at the IEEE/EDS S3S Conference in San Jose, CA, October 14 – 19th. S3S (formerly known as The SOI Conference) has been running in various forms for over 30 years. They always have an excellent line-up of speakers, plus it’s a great opportunity for networking with researchers from across the worldwide SOI ecosystem. BTW, while the deadline for general paper selection has already closed, papers of exceptional merit are currently being accepted for their Late News Sessions. See the 2019 Call for Papers for more information – those Late News papers need to be received by 23 August 2019 for consideration. Also, IEEE S3S Conference will once again host a full-day short course and a half day tutorial. These are very popular. The short course this year will be on SOI Design and Technology for Analog and Mixed Signal. As of this writing, the program is still being finalized, but more will be announced in the next few weeks, so check back on their website soon for updated information.Member EventsAnd finally, don’t forget to learn more about the offerings from and in support of the SOI ecosystem at our members’ events around the globe, including: GlobalFoundries – GTC | Samsung Foundry – SFF | ST – Technology Tour | Synopsys – SNUG | Cadence – CDNLive | Silvaco – SURGE | Arm – TechCon | NXP – Tech Days | Leti – Events | imec -Events |

Wedged among four major tectonic plates, Japan is at the mercy of their abrupt herculean shifts and the earthquakes and tsunamis they can trigger. The fallout can be devastating. The magnitude 9 Great East Japan (Tohoku) temblor in 2011 and ensuing tsunami took nearly 20,000 lives, destroyed 138,000 buildings and cost $360 billion in economic damage.Factories including silicon wafer production facilities owned by Shin-Etsu Chemical and MEMC Electronic Materials – together accounting for 25 percent of the global silicon wafer production – sustained heavy damage. Operations were suspended. The Kumamoto earthquake in 2016 also caused significant damage. The economic cost: as much as $7.5 billion.With disaster risk rising on a global scale, these calamities offer valuable lessons in disaster preparedness and how companies can draw from their experiences to strengthen business continuity planning (BCP).Earthquake experiences and lessons in BCP were the focus of the recent SEMI Japan Members Day as speakers from five semiconductor device and equipment manufacturers offered their BCP strategies to about 150 SEMI members. Following are key takeaways from their presentations. Renesas: Create a robust production plant that is hard to break and easy to fixRenesas Semiconductor Manufacturing’s Naka plant took about 80 days to resume production while its ability to deliver semiconductors was delayed even longer as it recovered from damage caused by the Tohoku earthquake, said Yoshiyuki Miyamoto, Representative Director and President at Renesas. Operations at the company’s Kawajiri plant were disrupted by the Kumamoto earthquake.A key lesson from both earthquakes: The company needed to promote risk visualization from top-to-bottom in the supply chain. With the goal of making its plants easy to repair but hard to break down, Renesas implemented a risk management plan for earthquake preparedness plan to ensure stronger production line resistance and a stable supply to customers. The company ran simulations of multiple earthquake scenarios including aftershocks, enabling it to develop new BCP training and preparedness measures. Sony: Staying transparent about the disaster, sharing and interacting with related companiesYukihide Keigo, a representative from the Sony Semiconductor Manufacturing, showed footage taken the day the Kumamoto earthquake damaged a production line at its Kumamoto Technology Center. Sony is the top manufacturer of imaging sensors worldwide, and the Kumamoto plant is the backbone of that production. The magnitude of the foreshock fell within levels Sony had accounted for in its BCP at that time, and the line was expected to return to full production within a week. However, the magnitude of the earthquake that followed outstripped expectations, and the company’s BCP didn’t hold up. Three and a half months later, the plant had finally fully recovered. The protracted recovery prompted Sony to develop an earthquake preparedness plan using a model that assumed double the magnitude of expectations. For full restoration, the company identified challenges to returning to full operation at each stage of the production line. Then it went even further, developing in-house diagnostics, implementing critical path methods and strengthening earthquake resistance of equipment that manages bottlenecks for the restart of the plant. The revision of its BCP plan led to the establishment of a system to shorten the resumption of production after a major earthquake to just two months.Sony shared the contents of its BCP review with other companies to solicit help identifying any gaps and highlighted its partnership with Renesas in the Semiconductor Industry Association in Japan (JSIA), a committee of the Japan Electronics and Information Technology Industries Association (JEITA), to share materials procurement resources for the purposes of disaster preparedness and business continuity. HORIBA STEC: Steady daily practices protect hundreds of millions of yen worth of products HORIBA STEC’s Aso plant, near the epicenter of the Kumamoto earthquake, suffered heavy damage that cut off electricity and the water supply, yet production in its clean room resumed in just 10 days, said Hiroyuki Koyama, a factory manager at the plant. The plant’s quick recovery stemmed from daily preventive measures implemented before the quake such as connecting freestanding shelves for greater stability, applying thick rubber bands as rails to prevent manufactured goods from falling to the floor, and placing equipment on rolling carriages instead of fixed shelves.The practices saved the Aso plant hundreds of millions of yen in products and materials that otherwise could have been lost in the earthquake. Koyama also offered the reminder that, with regulations governing factory layout and construction differing widely depending on factors such as a building’s age, companies need to tailor their BCPs to the unique characteristics of each building. THK: The key point of dampening earthquakesTHK’s ACE Division develops earthquake dampening and vibration control devices designed to absorb the vibrational energy of an earthquake, though the devices must also be designed for precise analysis of that energy, said Hidemi Murao. Murao provided an overview of the latest technologies and products for dampening earthquake vibrations and shared test results from experimental devices.Murao described how THK’s recently introduced Linear Motion (LM) Guide, an earthquake vibration dampening technology, can significantly reduce building vibrations during a temblor. In a video Murao showed to demonstrate how the guide works, a shelf loaded with equipment rests on a platform equipped with THK’s LM Guide equipment. Simulating an earthquake, the platform shakes vigorously in every direction but the shelf remains steady as the LM Guide dampens the vibrations. The platforms can be installed on floors or underground in buildings or factories to prevent shelves from toppling. Tokyo Electron: The ideal BCP management systemOne risk associated with BCP training is that it can become overly routine, dulling the response of employees in actual disasters, said Tokyo Electron Vice President Tatsuya Aso. To help keep its workers’ skills sharp, TEL held surprise drills with employees assigned to particular BCP roles to test their ability to adapt quickly to when disaster strikes. In addition, TEL has launched surveys in more than 70 overseas locations to optimize safety in these high-hazard facilities.The SEMI Japan Members Day presentations made clear that the issue of BCP transcends boundaries between individuals, manufacturers, regions, and sectors within the global electronics supply chain. Disaster preparedness requires problem-solving across the entire supply chain, with companies sharing technical knowledge, offering mutual aid, and striving for continual improvement. Collaborative is essential. At SEMICON Japan 2019, SEMI will continue to bring companies together to address BCP initiatives and share their technical knowledge with members. Jim Hamajima is president of SEMI Japan.

Lots of great information came out of the two days of workshops in Japan recently organized by the SOI Consortium. Some of the presentations are now posted on the consortium website (get them here). The first day (held in Yokohama and sponsored by Silvaco) focused on FD-SOI and RF-SOI design. The second day (held at U. Tokyo) focused on More than Moore (especially silicon photonics, MEMS sensors), and the SOI manufacturing ecosystem. The 1st day panel discussion was so interesting we'll give it a post of its own, then follow up with round-ups of the presentations from both days. And now to ramp! The morning panel discussion on end-user deployment for FD and RF-SOI was moderated by SOI Consortium Executive Director Giorgio Cesana. GF's CTO Subi Kengeri led off saying that that 2017 had been the year of FD-SOI adoption. Samsung Director Adam Lee noted that in the beginning nobody believed it would get traction, but now everybody does, and Samsung is commercializing it: chips coming out this year will ramp in volume in 2019. [caption id="attachment_12578" align="aligncenter" width="875"] Panel on FD-SOI and RF-SOI end-user deployment, SOI Workshop Japan, 2018. Giorgio Cesana, SOI Consortium Executive Director, Moderator; John Carey, ST Director; Adam Lee, Samsung Director; Subramani Kengeri, GF CTO; Wayne Dai, VeriSilicon CEO; Mostafa Emam, Incize CEO. (Courtesy: SOI Consortium)[/caption] VeriSilicon CEO Wayne Dai said he sees great potential in IoT, where the volumes are high but fragmented. In IoT, he said, you need RF, but you really only need very high performance about 20% of the time, which is a perfect fit for FD-SOI. ST Director John Carey noted that ST's been using FD-SOI since 2014. They've fabbed products for cryptocurrency and infrastructure. Now in their second and third generations of designing with it, they've got some big FD-SOI chips coming out next year with embedded memory and RF. He sees it being particularly successful in mmWave, automotive and IoT. The conversation then shifted to RF-SOI. Mostofa Emam, CEO of Incize, explained that since RF-SOI is already in every smart phone, it's in a different situation from FD-SOI. The emphasis here is now on adding more blocks. “RF is an art,” he said. “It takes an artist. You need talented artists and tools.” One of the biggest challenges for fabs that are newcomers is models – not just at the transistor level, but also at the substrate level. The big players have addressed this, but Incize is working to support more foundries with new, innovative approaches, and helping them develop robust PDKs. The industry needs more good RF designers as well as better RF design flow, he concluded. Coming back to FD-SOI, Cesana asked about non-volatile memory (NVM). Samsung's Lee said they've already got NVM options including eMRAM for 28nm, and customers are now requesting eMRAM PDKs for the next node (18FDS). ST's Kengeri added eNVM is important for FD-SOI, especially since flash is not scaling. While there are lots of options, MRAM gives you all the value, and in FD-SOI it only adds three more mask steps, so cost savings are maintained. With respect to local computing for AI with FD-SOI, everyone agreed on the importance of the edge. In addition to RF, FD-SOI gives you density even at 28nm, explained Carey. You can manually control power with back biasing, so you get something very flexible, especially for NB-IoT applications where the battery will have to last for 10 years. In fact Kengeri sees FD-SOI as enabling fog/edge computing. 5G – What's First? The next question was about 5G: which applications would we be seeing first, and how does FD-SOI help? Lee said Samsung's seeing it for apps up to 10GHz as well as mmWave. Customers are telling them they want FD-SOI for technical reasons. Kengeri expanded on that point, saying it comes down to fundamental physics: gate resistance, capacitance, mismatch. FD-SOI has lower Vmin and better Fmax compared to FinFETs, and that's what tier-one players want. Carey brought it back to RF-SOI (noting that ST's introducing a 45nm version), which supports a large number of elements and increased complexity with smaller power budgets. Emam then asked the foundry guys about mmWave. Substrates won't be the bottleneck he said, so what's the FD-SOI/mmWave roadmap? Kengeri responded that GF's ready. Lee said Samsung is also ready, and you'd see it next year on handsets. Samsung has engaged with customers on 30GHz for the middle of next year, he added: it's qualified. Carey said ST sees it first in consumer premises equipment that's connected by satellite. The right enabler Cesana then asked about image sensor processors (ISPs), noting that analyst Handel Jones has said this is a big opportunity for FD-SOI. You can do 3D integration with sensors, but heat makes noise, so you need technology that decreases heat production and doesn't give you hotspots (which would be visible in the image). Kengeri pointed to challenges in power density, thermal envelopes and the RTS (random telegraph noise signal). Although there are a lot of options, FD-SOI plays well for thermals and noise, so GF sees a good opportunity here. Dai added that the industry needs volume applications for FD-SOI, and ISPs need to bring more logic closer to the camera. And he concurred that you need FD-SOI for the thermals: it's very important. In closing, Dai noted that as a design house, “We walk on two legs: FinFETs and FD-SOI.” 28, 22, 18 and 12nm FD-SOI all enable differentiation. In particular, you need something between 20nm and 7nm: FD-SOI is here. Asked about Japan in particular, Dai said beyond automotive he saw lots of potential in ULP for AVR. Kengeri added that for any applications besides performance-at-any-cost, FD-SOI is the right enabler.

Specialty foundry TowerJazz is ramping a 65nm version of its RF-SOI process on 300mm wafers at Fab 7 in Uozu, Japan. To support the ramp, the company has signed a contract with long-term partner, Soitec, guaranteeing a supply of tens of thousands of 300mm SOI silicon wafers, securing wafer prices for the next years and ensuring supply to its customers, despite a tight SOI wafer market. [caption id="attachment_12108" align="alignright" width="300"] The 300mm 65nm RF-SOI process will be offered at the Uozu, Japan fab, which is operated by the TowerJazz Panasonic Semiconductor Company (TPSCo). (Photo courtesy: TowerJazz)[/caption] Five of TJ's seven fabs do RF-SOI. LNA (low-noise amplifers) are a big market driver, and with RF-SOI they can integrate the LNA with the switch, CEO Russell Ellwanter said in his lead keynote at the SOI Consortium’s 5th International RF-SOI Workshop in Shanghai (spring, 2018). BTW, that was in fact a very inspirational talk about Value Creation, and the importance of treating your suppliers with respect. He credited his company’s close relationship with RF-SOI wafer-supplier Soitec for TJ’s claim to the world’s best linearity. “We are delighted to see the strong adoption of 300mm RF SOI through this large capacity and supply agreement with TowerJazz to augment our already significant 200mm RF-SOI partnership,” said Soitec CEO Paul Boudre. “TowerJazz was the first foundry to ramp our RFeSI products to high volume production in 200mm and continues as one of the industry leaders in innovation in this exciting RF market with advanced and differentiated offerings.” According to the TJ press release (you can read it here), with its best in class metrics the TowerJazz 65nm RF-SOI process enables the combination of low insertion loss and high power handling RF switches with options for high-performance low-noise amplifiers as well as digital integration. The process can reduce losses in an RF switch improving battery life and boosting data rates in handsets and IoT terminals. It's a high-growth market, to be sure. Market researchers Mobile Experts predict that the mobile RF front-end market will reach $22 billion in 2022 from an estimated $16 billion in 2018. TowerJazz says its breakthrough RF SOI technology continues to support this high-growth market and is well-poised to take advantage of next-generation 5G standards, which will boost data rates and provide further content growth opportunities in the coming years. Customers are already getting into position. For example, Maxscend (WuXi, China), a provider of RF components and IoT integrated circuits, is ramping in this new technology. “We chose TowerJazz for its advanced technology capabilities and its ability to deliver in high volume while continuously innovating with a strong roadmap. We specifically selected its 300mm 65nm RF SOI platform for our next-generation product line due to its superior performance, enabling low insertion loss and high power handling,” said Maxscend CEO Zhihan Xu. As longtime ASN readers will know, we've been covering the evolutions of TJ's RF-SOI platforms since the beginning of the decade. It's worth noting, too, that beyond RF, TowerJazz also offers foundry customers other SOI-based processes, such as the new 0.18μm BCD SOI, a 200V SOI technology platform (announced in 2017, press release here) for motor drivers, industrial tools, electric vehicles and more. The previous generation 0.18μm SOI for automotive power management also offers exceptional area savings and is well-suited for high temperature operation. Back in 2014, here at ASN we did a great interview with TJ SVP Dr. Marco Racanelli about when and why they use SOI – and while processes have advanced, the basic drivers are still there, so it's a still a good read. And finally, designers will want to know that the TJ Multi-Project Wafer (MPW) Shuttle Program offers the 65nm RF-SOI process, as well as other SOI-based processes. See the website for scheduling and details.