Dialog Semiconductor

Emerging applications powered by 5G and artificial intelligence (AI) are expected to be a boon to the semiconductor industry, but only once chipmakers overcome a key challenge: Architecting chips that meet the exacting performance, power consumption, size and cost requirements of devices for mid- to high-end applications. One technology – heterogeneous integration – promises to meet these demands and help drive future leaps in semiconductor innovation in the post-Moore era. To help the industry better grasp the technology challenges and business opportunities associated with deploying highly integrated chip and packaging technologies, SEMI and AI on Chip Taiwan Alliance recently gathered industry leaders from organizations including ASE, Unimicron, Dialog Semiconductor, Cadence and AITA to discuss technology trends and the vital importance of building a cross-industry exchange platform to advance next-generation manufacturing processes critical to heterogeneous integration. Following are key takeaways from the forum, Heterogeneous Integration Enables 5G and AI. Overcoming Heterogeneous Integration Technology Challenges Key to Advances in Taiwan High-End Semiconductor Manufacturing The introduction of the Heterogeneous Integration Roadmap (HIR) by the International Technology Roadmap for Semiconductors team in 2016 was an important first step, Dr. C.P. Hung, Vice President of ASE Group, noted in his opening remarks. The HIR is designed to stimulate pre-competitive collaboration to advance heterogeneous integration technology development and accelerate electronics innovation. The roadmap provides a long-term vision for the electronics industry, identifying future technology requirements and potential solutions. Today, the HIR working group focuses on high-performance computing (HPC), 5G and other leading-edge technologies.Dr. Hung predicted that heterogenous integration will reshape traditional collaborations between the semiconductor ecosystem and supply chain in order to clear I/O bottlenecks that hamstring high-performance applications. The retooled industry connections will also need to enable high I/O pin counts, ultra-thin devices, and high-frequency signal shields. In an important step forward, the chip industry today is developing a platform that enhances wafer-level advanced packaging services and deepens cooperation with Oversea Assembly and Testing (OSAT) and substrate supply chain partners. Overcoming the current limits of IC substrates – the connection between IC chips the PCB – is one key for heterogeneous integration technology to flourish, said Dr. Yu-Hua Chen, Vice President, Carrier SBU, RD Division of Unimicron. He noted that the industry must tackle limits to PCB thickness, substrate density, fine pitch and automation to meet the needs of high-end packaging customers. Another barrier the industry must be surmounted is to make the currently inscrutable confidentiality requirements for patents of foreign materials – key to improving chip yields – easier to access and understand for substrate engineers. Chen said partnerships across the entire industry will be necessary to break through this and other technology breakthroughs. Supply Chain and Cross-Border Ecosystem to Strengthen Partnerships for Further DevelopmentTaiwan has long invested heavily in advancing semiconductor manufacturing and application engineering technologies to become a top global chipmaking hub and, in the process, has been behind significant leaps in optimizing chip functionality, said Leroy Liu, General Manager, Asia Headquarters, of Dialog Semiconductor (Germany). With its semiconductor manufacturing prowess, Taiwan can also play a central role in maturing advanced heterogeneous integration packaging technology while managing development costs by partnering with its international supply chain community to overcome technical challenges more effectively, Liu said. The region can also help forge partnerships, even among competitors, to build the ecosystem essential for heterogeneous integration technology to shine.EDA tools will be critical in understanding and resolving heterogeneous integration technical issues since IC substrate, packaging and chip design all pose interdisciplinary engineering challenges, said Julian Sun, Product Marketing Director at Cadence. To help the industry navigate these challenges, Cadence has launched intelligent system design products – solutions that address a wide range of design problems with semiconductor nanometers, micrometers on packaging and testing, and PCB level micro/millimeters to Pin/Pitch, I/O models, and thermals and electricity. By supporting various technical designs, Cadence helps customers shorten the design cycle to strengthen design quality and reduce costs.Sun also pointed to the vital importance of overcoming the significant challenge of designing silicon interposers for heterogeneous integration. Today’s EDA tools are capable of optimizing the design of complex structures including 5GAiP and HBM and are instrumental in aiding Taiwan’s semiconductor ecosystem players to quickly adapt to shifts in the evolving heterogeneous integration market.Heterogeneous Integration Enables 5G and AI speakers (L-R): Julian Sun, Product Marketing Director at Cadence, Dr. Yu-Hua Chen, Vice President, Carrier SBU, RD Division of Unimicron, Dr. C.P. Hung, Vice President of ASE Group, Leroy Liu, General Manager, Asia Headquarters, of Dialog Semiconductor (Germany), Dr. Shih-Chieh Chang, AITA Executive Secretary Designing AI chips is particularly difficult as semiconductor makers struggle with high costs and low yields, said Dr. Shih-Chieh Chang, AITA’s Executive Secretary. That’s why the chip industry now uses FPGAs for small-volume production of AI chips, which makes it easier to improve manufacturing yield through redundant design. For its part, AITA has formed a special interest group (SIG) to help form connections among the chip industry, academia and research institutes. The association’s goal is to build a platform for mass production of AI chips.To get involved in SEMI Taiwan Heterogeneous Integration related events, please contact Ula Huang, outreach senior specialist, at [email protected] Fang is a coordinator and Ashley Huang is a specialist in marketing and public relations at SEMI Taiwan.

SEMI spoke with Balaji Nandhivaram Muthuraman, Package and Material Simulation engineer at Dialog Semiconductor, about the state of reliability testing for wafer-level chip scale packages ahead of his presentation at the Advanced Packaging Conference at SEMICON Europa 2018, 13-16, November 2018, in Munich, Germany. To register for the event, click here. SEMI: Since the beginning of package development reliability testing has played a key role in Wafer Level Chips Scale package (WLCSP) investigation. Lately, the role of simulation and predictive reliability significantly contributed in reducing package development time. To what extend can we predict potential failures for WLCSP packages in an early design phase by simulation?Muthuraman: Reliability testing is essential and crucial for the electronic packages. It is during the package development phase that several design iterations need to be considered and, in some cases, many feasibility studies for the package are executed. This means we require significant reliability test measurements, which could influence product-development time. For example, Temperature Cycling on Board (TCoB) reliability testing would take approximately 65-75 days for testing the package reliability subjected to 1500 temperature cycles. Each cycle involves exposing the device at hot and cold temperatures with a specified temperature profile. Executing such Board Level Reliability (BLR) tests for all feasible package designs is a tedious process that could lead to an increase in package development time. This is the stage where numerical simulation methodology helps us to foresee potential failures in Board Level Reliability. Predicting delamination or cracking of passivation/metal interface layers based on the WLCSP design layout and estimating the characteristic life of smart device subjected to temperature load are some classic examples of predicting WLCSP package behavior in an early design phase by simulation methodology.SEMI: We can definitely say that predictions occurring during the early stage are key to success. But how exactly can numerical simulation help estimating?Muthuraman: From a thermal reliability point of view, determination of the optimum material combination – bill of materials for device – is used to predict whether a heat sink is required for the device to meet thermal performance. This is not all. At an early design stage, the simulation methodology can be used to estimate device performance under varying thermomechanical loads. Numerical simulation at early package development phase helps the researchers by predicting the possible temperature contour field and stress contour field of the smart device under a given loading condition. The estimation accuracy of potential issues through numerical simulation depends on the material models implemented and consideration of realistic load condition under which the package operate in real life situation. For example, engineering judgements can be made using numerical simulation of Solder Joint Reliability (SJR) analysis to decide whether an Underfill material is required between the Package and the Printed Circuit Board (PCB).SEMI: Are all conditions tested during the reliability investigations specific to fit a certain type of applications or do these vary?Muthuraman: Reliability investigations are based on the end application of the electronic devices. For example, handheld device applications will be exposed to a reliability condition up to a maximum of +85oC, whereas smart devices designed for an automotive application would be tested with a typical temperature of +125 oC or up to +150 oC. In some cases, the testing conditions are customized based on specific customer requirements. Moreover, reliability conditions can also be customized to study some specific failure mechanism. SEMI: Can you describe for which one?Muthuraman: Thermal cycling profile is based on device application and/or specific requirement from our customer. For example, handheld devices use a typical temperature range of +85°C to -40°C with 20°C/min ramp time and 20 minutes of dwell time. There is possibility of adjusting the ramp and dwell time of the Temperature Cycling qualification test, provided such accelerated test does not lead to other failure modes.SEMI: What failure mechanism was the subject of the study in this specific case?Muthuraman: Electronic package reliability behavior without and with underfilled devices is explained in this study with the help of temperature cycling on board (TCoB) measurements and validated with numerical simulation. In the paper to be presented at SEMICON Europa, failure occurring at the interface of the solder and Under-Bump Metallization (UBM) structure is discussed. Behavior of such failure mechanism is illustrated with different WLCSP package sizes subjected to varying thermal load condition. One of the key aspects of the subject is the board-level reliability (BLR) measurement and simulation validation showing how the failure mode could be shifted from solder joint to the metal interface layers between UBM and interconnection to Silicon Chip, depending on the WLCSP design layout. The reasons for such shifts in Failure phenomenon are explained and necessary design optimization is suggested for improvement. Another key aspect of this study is determination of Fatigue Life Model for WLCSP family using the SACQ solder. SEMI: Are you currently working and experimenting on something particularly exciting?Muthuraman: Recently, we concluded our engineering analysis of thermomechanical reliability of Large Wafer Level Chip Scale packages. In September 2018, I presented this research work in an International Conference held in Dresden, Germany. Dialog Semiconductor GmbH was awarded the “Best Paper Presentation for the year 2018” for this work. This success is attributed to the entire team of Package and Material simulation experts at Dialog Semiconductor GmbH lead by Mr. Baltazar Canete and IC Package-Design Simulation group managed by Mr. Rajesh Aiyandra. We have started our investigation on the influence of Board Level Reliability of WLCSPs due to varying metal concentration of inter-metallic layer. We, at Dialog, are also working on possibility of thinner WLCSP. All these activities would include extensive Temperature Cycling on Board (TCoB) measurements, Statistical Analysis of measurement Data and would then be validated by Numerical Simulation. SEMI: What are your expectations for the future and why would you recommend attending SEMICON Europa Advance Packaging Conference?Muthuraman: SEMICON Europa is an important platform for Dialog Semiconductor GmbH to showcase the latest developments in the semiconductor industry. It is an opportunity to meet other industry experts, partners, and customers, and exchange various innovative ideas and to get new insights. Many semiconductor companies are based around the Munich area as well world-class universities. We are particularly interested in innovation, workforce and talent development themes. SEMICON Europa gives us a platform for greater interaction with the academicians and research scientists. This way, we bridge the gap between industry and University researches, thereby moving forward in innovative technologies. We, as Dialog Semiconductor GmbH, have also a development center near Munich (Germering). Our expectations for the future are very positive and vibrant. We are always ready to take up the industry challenges and demands and provide the best-in-class solutions to our product users. Dialog Semiconductor GmbH is certainly poised for higher growth in coming years. Balaji Nandhivaram Muthuraman BioBalaji Nandhivaram Muthuraman is a Packaging and Material Simulation engineer at Dialog Semiconductor GmbH, Germany. He has authored/co-authored conference publications including in the area of molecular dynamics simulation on assembly of carbon nanostructures; Analysis of thermoset material used in smart devices and reliability of wafer level packages. Recently, he has been awarded with the “Best Paper Presentation for year 2018” in the area of Board Level Reliability of Wafer Level Chip Scale Packages, in a recently held international semiconductor conference. His current areas of working interest include reliability investigation of electronic packages and developing fatigue models for reliability assessment of Dialogs products. He obtained his Bachelor’s degree in Aeronautical Engineering from Anna University, India and Master’s degree in Computational Mechanics of Materials and Structures from University of Stuttgart, Germany. Serena Brischetto is a marketing and communications manager at SEMI Europe.