manufacturing

Presentations from SEMICON West’s “The Convergence of Semiconductor Manufacturing and Design” offer great insights into the collaboration between the two, as I was recently reminded by presenter Sutirtha Kabir, R D Engineering, Executive Director at Synopsys.Reviewing his talk “Revolutionizing Silicon to Systems Design: Unlocking the Future with 2.5D and 3D Multi-Die Innovations” was a good kick-off for our discussion that covered the continuous need for collaboration and where AI fits. Kabir, as I quickly learned, is a technical innovator and articulate communicator passionate about ongoing collaborations between design and manufacturing. Today’s blog post is the second in a four-part series featuring presentations from the SEMICON West design program, organized by the ESD Alliance, a SEMI Technology Community. The first blog, with Dave Kelf, CEO of Breker Verification Systems, appeared on January 6 (“Circular Collaboration Leverages EDA Advances”).Smith: How do you define collaboration between design and manufacturing?Kabir: Multi-die design and advanced packaging are a big focus of high-performance computing (HPC) and AI chips. Engineers are trailblazing and foundries are coming up with new stacking combinations. For this reason, design and manufacturing teams need to be closer than ever. Solutions must be made available to give ample visibility to manufacturing from the very start of the design process. Single die design has been done for 15 to 20 years with a continuity of power, area, and performance (PPA). Design flows, methodologies and the ecosystem between design houses, EDA vendors and foundries are mature and stable. The conundrum is that it's a different situation with multi-die designs. Not only is multi-die emerging rapidly, but the types of design innovations are different.We have been working closely with our foundry partners to move multi-die innovation forward by enabling more advanced process and packaging technologies. I don't see this slowing down as they are coming up with different ways of doing designs. Design teams are collaborating closely with the foundries to take advantage of the benefits of these new multi-die designs.Smith: You mentioned new stacking combinations and collaboration with the foundries. What about collaboration with the OSATs? Kabir: Generally, it’s both silicon foundries and OSATs. With advanced packaging, both play a significant role depending on the types of applications being targeted. Design house targets may shift from the traditional silicon foundry to several OSATs. For example, if an organic interposer is required, the collaboration could be with an OSAT in conjunction with the silicon foundry. There are many possible collaborations that may be required. The point I’m trying to make is that there is a strong need for collaboration between EDA and the foundries during design that continues through manufacturing and test.Smith: What trends in general are driving the need for this collaboration?Kabir: The trends are performance and scalability and the need for high-performance compute. Look at some of the mega-chip systems coming out today compared to the bigger systems from five years ago. HPC was not driving that much in 2.5D. The big interposers used to be on silicon, maybe 1.2 to somewhere around less than three reticle sizes. Today, the reticle limit is more than 5X. Leapfrog to today, and the configuration has changed where the state of the art is to use an organic interposer with multiple embedded bridges (up to 20 or more) buried inside the interposer to support high-speed interconnect. The organic interposer with multiple layers on the front side and back side communicates with bridges and the SoC and HBM that sit on top of that interposer.3D architectures stack dies with GPUs and a large amount of HBM such as an HBM4 memory stack. The memory stacks may be 8 or 16 high. All of this memory needs to be as close as possible to compute for scalability. In terms of the high-power demand, the designer needs to make sure that the voltage that is pushed from the bottom of the stack can feed the power hungry SoC blocks on top of the 3D stack. At the end of the day, EDA is all about giving design and manufacturing houses the capability to predict how a design is going to perform in all different kinds of scenarios. EDA must keep up with this trend and that requires collaboration.Smith: What about the verification side, specifically system verification? Kabir: Let’s say I am using a spreadsheet and doing back-of-the-napkin calculations, a technique that used to work well for single die or design blocks. Multi-die doesn't scale since multiple heterogeneous dies in a single package must be considered. Design planning must include directional changes to measure the effects with key performance indicators. The challenge is to correlate signoff and verification. Signoff engineers can no longer just verify at the end of the design cycle. Instead, it has become a continuous process that transcends the flow from design planning through implementation and signoff and release to manufacturing.The industry is repeating a pattern from about 20 years ago, when single-die design evolved from relatively naive approaches to much more sophisticated EDA-flow-driven methodologies.Smith: As you drive the tools forward, who are your counterparts on the manufacturing side? Kabir: It depends on the different stages of design—design planning, implementation or signoff. It starts at the architecture stage from the left when architects and physical design engineers are doing floorplanning. The term design technological co-optimization (DTCO) has evolved into S (system)TCO now because we are trying to co-optimize system design and technology. I'll give you a simple example. A working chip manufactured in a certain technology node is going to be used in a multi-die design. Is the existing chip technology good enough to support the design or will it require a new chip at a different node? In either case, how does an engineer work with the manufacturing house to make sure it has the right metal layers or a different number of metal layers or a different metal width or some other property on the technology side? Designers need to make data-driven decisions based on the configuration and technology numbers to meet power budgets.In the past, what was once managed through designer-ASIC house-manufacturing interactions are now increasingly being handled by EDA flows as part of design implementation.Smith: Ultimately, it's driven by business. The hard work and decisions are made by two teams of knowledgeable technical people who must come together.Kabir: And then of course it has to be rolled into program management, business development and all this needs to be supported by data. We all recognize that the design window is not increasing. It’s always about trying to get more out in less time with less people. That doesn't help the equation.Bob Smith: How does AI fit into this and how is it best leveraged? Kabir: I’m hearing, learning, and reading about the tremendous advantages AI could bring. AI has a huge role to play, but it won’t eliminate the need for savvy design and verification engineers.Multi-die design brings together different users from different tool backgrounds. Even the language between a packaging person and a silicon person is different. The terminologies they use are different, as are the ways they have done design over the last 15-20 years. The same applies to thermal, power or signal integrity engineering. Bringing them together requires that EDA will provide platforms where the whole system design, including chip design, is managed. That’s a tall ask for people from all different backgrounds to come in, learn different technologies and tools within a short time. This is where ChatGPT or Microsoft’s Co-Pilot can be applied in the EDA world today to quickly find solutions by reading through manuals, application notes, forums and the like to find solutions. This use of AI agents can save tremendous amounts of time for designers. Another aspect that can be positively impacted are roles. We have customers coming to us and brainstorming on the use of workflows and methodologies, instead of the design aspect. Scalability from the human perspective has become difficult because of the need to closely guide engineers to get them up to speed on new technologies and workflows. This is where Agentic AI can deliver a huge productivity boost. It's not replacing anyone. It's getting them to decisions and end results faster.Smith: Can Agentic AI play a big role? Kabir: Current AI is like the person who, when asked a question, has to give an answer even if it’s the wrong answer. The same thing is going to happen when we bring in all these EDA technologies with AI capabilities.The point I'm trying to make is how do we verify that AI is doing the right thing? In EDA, one of the biggest questions and concerns is if a result or outcome or design can be verified. If it can't be verified accurately, verification engineers will not trust what AI is telling them no matter how fantastic the algorithm is. The verifiability of AI solutions is important for EDA. The key question is: Why would I trust what your tool is telling me to do?EDA flows that are more mature rely on decades of expertise, thorough documentation, and various scenarios to train AI algorithms. Those are the AI-powered EDA flows that I trust the most. About Sutirtha KabirSutirtha Kabir, an Executive Director of R D for Synopsys’ 3DIC Compiler, has over 20 years of product engineering experience, driving, building, and inspiring teams across companies in the EDA industry. In his role at Synopsys, he supports construction and analysis of multi-die systems including stacked ICs plus Interposer configurations. Prior to joining Synopsys, Kabir was a Group Director of Engineering at Cadence. Kabir has a Master of Science degree in Electrical Engineering. Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community.

The SEMICON West 2025 design program “The Convergence of Semiconductor Manufacturing and Design,” organized by the ESD Alliance (ESDA), a SEMI Technology Community, featured presentations about successful collaborations between the design and manufacturing markets. The three-hour program in a packed conference room included plenty of great material that we’re using as the basis for a blog series that you will see over the next several months. I’m working on them now based on my conversations with four of the speakers where we discuss key drivers behind the need for collaboration and what’s ahead.I’m starting with Dave Kelf, CEO of Breker Verification Systems, a company steeped in front-end chip verification, who describes an actual circular collaboration that effectively leverages AI and other electronic design automation (EDA) advances. We recently talked about collaboration, integrated design and manufacturing flows and AI.Smith: How does Breker define collaboration between design and manufacturing? Kelf: In general, at a technical level, we would define this collaboration as the sharing of data, methodology and/or information that improves both processes. As semiconductors become more complex, this sharing process is increasingly important to effectively manage the overall complexity of today’s chip designs.Smith: What trends are driving the need for this collaboration?Kelf: Apart from the ever-increasing size and density of semiconductors, there are specific trends that require more interaction between design, verification and manufacturing. Obvious developments include the advent of chiplets, given the changes in performance of signal paths, and 3D devices driving complex packaging, power dissipation and other issues. Design issues such as the increased need for SoC coherency testing and complex device structures such as multi-core processors, also play a role. With many of these issues, design and verification (D/V) trade-offs have an impact on manufacturing, and vice versa. For example, differing delays on a Universal Chiplet Interconnect Express (UCIe) interface—an open specification for a die-to-die interconnect and serial bus between chiplets—will have an impact on hazard testing in coherency verification. As another example, thermal hotspots on some parts of a chip package might need additional testing during the verification phase. Smith: What trends and challenges are preventing a fully integrated design and manufacturing design flow?Kelf: Traditionally, the D/V and manufacturing teams have remained separate in most organizations, as well as between the two industries. EDA companies sell primarily to the design teams, although they do interact with the foundries at the back end of the process. Manufacturing companies work directly with different teams at the foundries and not with the D/V teams at all. New relationships need to be built up. The general know-how in these disciplines is different, and methodology approaches tend to be disconnected. The tradition is to separate the processes and use standardized interfaces for communication that leaves little room for improvisation. All this needs to change so that teams can begin to work more closely.Smith: What is circular EDA-manufacturing collaboration and vertical integration?Kelf: In past EDA flows, we have seen disparate tools performing specific functions. As semiconductors got smaller, their physics changed and this led to the design process absorbing new characteristics. For example, abstract designs were run through synthesis to create gates connected by wires. This format was then passed to place and route (P R) tools that would lay out the gates in terms of transistors and interconnects on the silicon wafer. On large devices, the gate level signal delays were larger than the interconnect, allowing design to be separated from layout. As silicon became denser, the interconnect delays became the dominant factor, and the layout of the device impacted the design synthesis process. The two tools required forward integration—synthesis projected layout rules to P R, and a reverse integration where layout characteristics were sent back to synthesis for redesign where required delays could not be handled during P R. The methodology went from a simple flow to a circular design approach as synthesis and P R cooperated. The same is now true of design and manufacturing where solving the problems noted above requires this same circular cooperation. Smith: What will it take to have an integrated design and manufacturing flow?Kelf: A lot of cooperation between different groups. As we reach limits in areas such as signal integrity and thermal management that will squeeze silicon efficiency improvements, these methodology linkages will be required for continued progress and growth. The industry (both design and manufacturing) will be highly motivated to make this happen. Smith: From a personnel perspective, who (on both sides) are the typical touchpoints? Kelf: It will be the engineering staff from both the design side and manufacturing that work closely to develop technical solutions. Executive-level support is, of course, needed to cement the collaboration. Smith: Where does AI fit?Kelf: AI will have a role to play in this. Estimating the factors that drive efficient design to manufacturing to design flows is a critical step in speeding interaction and providing sensible estimated starting points. AI can process the large amounts of data necessary to provide these estimates as we now see complex chips that contain billions of transistors. AI will be needed to accelerate the interactions for different tools through the development process.As design and manufacturing collaboration becomes a critically important industry strategy, companies are turning to SEMI and its Technical Communities such as the ESDA and their wide-ranging initiatives. For details and to get involved, visit the ESDA website at https://www.semi.org/en/communities/esda. To learn more about Breker and its solutions that provide test content portability and reuse to solve complex semiconductor challenges across the functional verification process, go to: https://brekersystems.com.About Dave KelfDave Kelf holds the position of CEO of Breker Verification after serving as its Chief Marketing Officer responsible for all aspects of Breker’s marketing activities, strategic programs and channel management.Earlier, he served as vice president of worldwide marketing solutions at formal verification provider OneSpin Solutions, was president and CEO of Sigmatix, Inc., and held senior positions at Cadence, Synopsys and Springsoft. Kelf holds a Bachelor of Science degree in Electronic Computer Systems from the University of Salford and a Master of Science degree in Microelectronics from Brunel University, both in the U.K., and an MBA from Boston University.Robert (Bob) Smith is executive director of the ESD Alliance, a SEMI Technology Community. 

The semiconductor industry is on track to expand and launch 97 new high-volume fabs online worldwide from 2023 through 2025, a major milestone that highlights the massive investment in chip production capacity. This rapid expansion is expected to drive a sharp increase in the deployment of pendulum valves. These valves, found in tens of thousands of semiconductor tools, are critical to the wafer manufacturing process.  Though hidden inside complex etch and deposition chambers, pendulum valves play a vital role in semiconductor manufacturing. They regulate gas flow and maintain the vacuum conditions required for precise wafer processing, ensuring efficient etching or deposition by controlling gases, managing exhaust flows, and maintaining chamber integrity. But what happens if a pendulum valve fails? It disrupts the vacuum necessary for wafer processing, causing chamber contamination and potentially ruining wafers. This leads to costly material scrapping, unplanned downtime, and production delays. Persistent failures can damage the turbo molecular pump or the entire tool, significantly increasing repair costs. Clearly, pendulum valves are essential for the reliability and performance of semiconductor equipment, particularly in etching and deposition chambers. Here are four critical reasons why:Consistent Vacuum Control: Maintaining a consistent vacuum environment is crucial for uniform layer deposition and etching, directly impacting the yield and performance of semiconductor chips. These valves regulate pressure and gas flow to ensure consistent and precise wafer fabrication processes. Contamination Prevention: Contaminants are a semiconductor manufacturer’s worst nightmare. Even microscopic impurities can destroy a wafer. Pendulum valves mitigate this risk with high-quality sealing mechanisms that create airtight environments, leading to high quality wafers and reducing waste.  Enhanced Yield: Pendulum valves are vital to achieving the highest possible yield in wafer manufacturing. Their ability to maintain operational stability and enhance process efficiency leads to fewer defects and higher productivity. By precisely controlling gas flows and preventing contamination, these valves reduce the likelihood of wafer defects and improve overall throughput. Minimal Footprint: Semiconductor fabs are high-tech, high-density environments where every square inch counts. Pendulum valves are designed with compact dimensions, allowing engineers to maximize production capacity without compromising performance or reliability.  Seal Performance Defines Valves’ Longevity  One of the core components of pendulum valves is its seals, directly impacting its durability, reliability, and maintenance. High-performance seals minimize downtime, reduce maintenance costs, and ensure a long operating life. However, achieving this performance requires attention to the challenges in semiconductor processes that impact performance and lifespan. Exposure to aggressive chemicals and plasma environments can degrade seals, causing erosion, sticking, and cracking. Continuous dynamic motion, including compression, decompression, and rotational movements, leads to friction and wear, shortening seal longevity. Errors, such as improper installation of static seals, can disrupt valve operation and cause delays. Extreme heat in wafer fabrication further tests the durability of valve components, while poor maintenance increases the risk of failures, resulting in costly downtime and repairs.  To keep valves operating at their peak efficiency, manufacturers need to prioritize five types of seals, identifying potential risks and tackling them effectively. The Pendulum Plate Face Seal, a dynamic component, must endure repeated compression and decompression during use. This constant motion, coupled with exposure to harsh chemicals, makes the seal vulnerable to issues like sticking and cracking. Without proper installation and attention, extreme failures, such as the seal dislodging entirely, can occur, disrupting operations.  Similarly, the Pendulum Plate Radial Seal performs a vital role, moving vertically within a piston bore. This component faces threats such as rolling, twisting, and chemical degradation, often leading to cracks or even fragmenting under severe torsional stress.   The Bonnet Seal, though static, is not exempt from potential difficulties. Improper installation or material cracking can severely compromise its functionality.  For dynamic applications like the Rotating Paddle Shaft Seal, friction is a constant adversary, compounded by chemical exposure that accelerates wear and tear.  Lastly, the Actuating Pins Seal, pivotal for enabling precise up-and-down movement within a piston bore, is particularly sensitive to installation errors.  When Failure is Not an Option  Addressing these challenges is essential to maintain the reliability and longevity of pendulum valves in semiconductor manufacturing. Greene Tweed uses a structured framework ‘Right Seal Pyramid’ to select the most suitable seal for every application. This process considers key factors like material compatibility, seal geometry, and operating conditions to develop solutions tailored to the specific needs of semiconductor manufacturing. By aligning seal types with precise engineering criteria, the Right Seal Pyramid methodology addresses key challenges like chemical resistance, mechanical stress, and installation accuracy, ensuring reliable performance in the harshest semiconductor manufacturing environments.  Explore MoreWant to learn how to prevent premature pendulum failure? Catch our full webinar replay or download our Semiconductor Playbook for expert insights, innovative solutions, and best practices tailored to your most critical applications. Carmen Quartapella is a Senior Engineer of Design Analysis at Greene Tweed. Quartapella has developed deep technical expertise over a three-decade career that spans multiple facets of the semiconductor industry. Throughout his career, he has gained expertise in Semiconductor Engineering, Engineering Management, Sales, Business Management, and Emerging Technologies. He graduated from Drexel University with a degree in Mechanical Engineering

As more than 400 speakers took the stages at SEMICON West 2024, sustainability and workforce development stood out as two major focus areas. The second day of this year’s CEO Summit keynote program, themed Seizing the Global Opportunities and Challenges Ahead, featured sessions on both topics. One of the first sessions of the day was the Chief Sustainability Officer (CSO) panel discussion, titled Bracing for the Evolving Global Risk for the Semiconductor Ecosystem, moderated by Vice President of SEMI Global Sustainability Programs, Dr. Mousumi Bhat. Later that morning, Shari Liss, Vice President of SEMI Global Workforce Development Programs and Executive Director of the SEMI Foundation, moderated a fireside chat, Advocating for Real Change: Why Inclusion and Belonging Need to be Everyone’s Concern, with Sandra Mahadwar from KLA Corporation. Bhat and Liss were later interviewed for a podcast by Francoise von Trapp of 3D InCites to share additional insights on sustainability and workforce development, respectively. Bhat was also joined by Paul Kelly, COO of the New York Center for Research, Economic Advancement, Technology, Engineering, and Science (NY CREATES). Creating a More Sustainable Semiconductor Industry During their interview, both Bhat and Kelly emphasized that the industry will need to reduce its use of per and polyfluoroalkyl substances (PFAS) to sustainably innovate at today’s nanometer pace. For this reason, Kelly highlighted the importance of learning to balance current production demands with the health of climate.To achieve this balance, they discussed the efforts of the Semiconductor Climate Consortium (SCC). Much of the SCC’s efforts, they said, will focus on driving the industry toward net zero emissions. SEMI and NY CREATES announced a memorandum of understanding (MOU) at SEMICON West 2024 to promote sustainable practices within the industry, with a focus on PFAS reduction. Kelly pointed to the ability of SCC members to test new materials, gases, and chemicals at NY CREATES’ R D facilities in upstate New York to work toward replacing PFAS with more sustainable alternatives. Bhat also shared that this collaboration helps facilitate prototyping, experimentation, and tests and measurements for newer, more sustainable substances.Dr. Mousumi Bhat of SEMI and Dave Anderson of NY CREATES celebrate their organizations’ sustainability MOU at SEMICON West 2024.“The thought leadership comes from the Consortium, and the support on infrastructure comes from NY CREATES,” said Bhat. “This should become a blueprint to solve some of the challenging problems that we have in our industry.” When it comes to reducing emissions, Bhat mentioned two key objectives. The first, she said, is access to clean energy, and the second is the reduction of greenhouse gases. Bhat cited these as the issues that will take the longest for the industry to solve and pointed to the importance of industry collaboration and partnerships to support the needed experimentation. But while partnerships will bring the industry closer to net zero, both Bhat and Kelly cautioned that it won’t be reached overnight. “Much more needs to be done in the industry to reach that net zero goal,” said Kelly. “New chip technologies, new chemicals, and new processes are very much large leaps to achieving that. But right now, even some of the most advanced will only reduce [emissions] by 70%.” To help bridge this gap, Bhat encouraged others to join and participate in the SCC. “Rather than everybody doing a one-to-one experimentation in their own space and spending those resources, I would like to invite anyone that's not part of the climate consortium,” she said. “And [I invite] those that are part of the climate consortium to engage more actively, so that we are all accelerating the journey toward net zero.” Addressing the Talent Shortage This year’s SEMICON West also featured five keynote sessions dedicated to workforce development, as well as a Workforce Development Pavilion that included several talks around diversity, equity, inclusion, and belonging (DEIB). With the estimated one million jobs the industry will need to fill by 2030, Liss shared that every role is needed – from entry level all the way to Ph.D. researchers. “We need to try and bring in as many people as we can over the next few years,” said Liss. “The talent shortage is a global issue, not just a U.S. one.” Shari Liss of SEMI moderated the fireside chat at SEMICON West 2024 with Sandra Mahadwar from KLA Corporation.To begin to close the talent gap, Liss stressed the importance of educating children about the semiconductor industry. “We are just invisible to kids,” she said. “In every part of the globe, they carry chips in their hands all day every day, and they don’t know. So to me, breaking that barrier and making sure kids know about our work as an industry is going to be so critical to making this successful.” Liss also highlighted differences in workforce development programs across the world, noting that what works in one region may not translate to another. For example, apprenticeships are widely embraced in Europe, she said, but they’re a fairly new practice in the U.S. Conversely, she shared that veteran-focused programs wouldn’t work for some regions, but they’re a “powerful win” in the U.S. Each SEMICON show across the world, she shared, includes similar workforce development and DEIB programming, in addition to targeted sessions for students and HR professionals. Companies can interview for open positions at SEMICON shows as well. To learn more about SEMI’s workforce development initiatives and programming, visit semi foundation.org, or check out this overview of DEIB content at SEMICON West 2024. Samer Bahou is director of Marketing Communications at SEMI.

Seeking to spur more green technology innovation for our industry, SEMI Startups for Sustainable Semiconductors launched the third year of the program by inviting startups, academics, and innovators with compelling ideas for advancing semiconductor industry sustainability to apply to participate.

Tokyo Electron has implemented various programs and initiatives aimed at helping veterans find meaningful employment opportunities and providing them with a supportive and inclusive work environment. TEL is a founding member of the SEMI Foundation’s VetWorks working group.

In the podcast, SEMI president and CEO Ajit Manocha discuses how the industry is addressing challenges to growth in the final episode of the SEMICON West podcast series featuring conversations with keynote and panel speakers, exhibitors and SEMI executives recorded before and at the event.

To help companies create their workforce development plans as part of the CHIPS Act funding application, we created the SEMI Foundation Workforce Development and DEI Menu of Services – packages of workforce development programs currently offered by the SEMI Foundation.

SEMI Southeast Asia continues to implement workforce development initiatives to strengthen the region's position as a global manufacturing hub. SEMI launched the global SEMI University online learning management system in February.

Building on the success of the first year of Startups for Semiconductor Sustainability to spur more green tech innovation, SEMI invites startups, academics, and innovators with compelling ideas for advancing semiconductor industry sustainability to apply to participate.