Surface Preparation & Cleaning Conference—Call For Abstracts Now Closed
The Surface Preparation & Cleaning Conference (SPCC) 2026 will be held at the Wild Horse Pass Resort in Chandler, AZ from May 18-20, 2026.
SPCC Call for Abstracts Deadlines
- Abstract Submissions Due
- January 16, 2026
- Review Period Ends
- February 27, 2026
- Author Notification
- March 2, 2026
The Surface Preparation and Cleaning Conference focuses on addressing the current and future challenges that the surface preparation and cleaning industry is facing. The presentations specifically target the latest research on cleaning technologies for the electronics industry. They cover a wide range of topics, including front-end, back-end, packaging, equipment, materials, and metrology developments, as well as general issues related to wafer cleaning.
Abstracts (in MS Word or PDF only) should be two-page (maximum) and include the selected topic. Authors of accepted abstracts are also invited to submit expanded manuscripts for submission to a special peer-reviewed edition of Microelectronics Engineering to be published after the conference. Only full papers submitted by July 1st, 2026 will be considered for publication. When submitting an abstract, please indicate if you also plan to submit a full paper for this publication.
We strongly encourage global semiconductor manufacturers, suppliers, researchers, and students to submit abstracts on various aspects of advanced cleaning and surface preparation. This includes, but is not limited to, the following topics:
- Wet processes, surface preparation, new experimental work and findings, and subject area reviews.
- Cleaning challenges associated with advanced memory technologies, including pattern collapse, contaminant removal from high aspect-ratio structures, selective etching, particle removal and surface preparation in DRAM, 3D-NAND, and emerging memories.
- Challenges associated with wet and dry cleaning, surface preparation, and controlled removal of materials associated with advanced logic/memory structures - including FinFET, gate-all-around (“GAA”) structures, nanosheets and both horizontal and vertical nanowire devices.
- New surface preparation approaches to enable More-than-Moore process scaling.
- Defect/particle reduction techniques for advanced CMOS or automotive devices.
- Improvement in environmental, safety, health, and sustainability performance.
- Surface preparation and clean challenges associated with Ge, III-V, GaN, SiC and 2D systems.
- Multi-metal post etch cleans challenges in FEOL, BEOL and emerging memory structures.
- Post-CMP cleaning challenges.
- Metal and low-κ dielectric related cleaning and ashing issues for 3D and advanced interconnect.
- Unique challenges associated with advanced, optical, and EUV mask cleaning, including surface preparation and treatment for resist adhesion enhancement.
- Control of contamination during cleaning, fabrication, exposure, storage, and transport of substrates and masks.
- Challenges associated with providing high purity water and chemicals and the associated delivery systems.
- Analytical techniques relevant to surface preparation.
- In-situ monitoring techniques and statistical process control of cleaning or wet processes.
- Use of advanced process control and artificial intelligence/machine learning techniques in cleaning processes in high-volume manufacturing.
- Advances in trace particle and metal detection metrology on wafer and in-situ.
- The effect of surface preparation on electrical/device performance.
- Influence of back-end processes and contaminants on packaging performance & reliability.
- Surface preparation and passivation challenges in photovoltaics, MEMS, and nanoelectronics.
Authors will be notified on March 2, 2026.
For more information, please contact Krish Raghunath at [email protected], or Agnes Cobar at [email protected].