Si/SiGe Selective Wet Etchant for BSPDN Application: Maximization of Selectivity in Single Wafer Spin Wet Processing
With continued device scaling, performance degradation caused by power delivery issues, such as wiring delay and IR drop, has become increasingly severe. To address these challenges, backside power delivery network (BSPDN) technologies have attracted significant attention. In typical BSPDN fabrication processes, buried power rails, device structures, and signal interconnects are first fabricated on a silicon wafer. A second silicon wafer is then bonded to the front side, followed by wafer flipping, after which the original substrate is thinned through a combination of mechanical and wet etching processes. During backside silicon removal, SiGe layers are widely used as etch stop layers (ESLs) or as source/drain materials. However, conventional wet silicon etchants cannot completely and abruptly stop on SiGe during the final silicon etching step. As a result, the ESL thickness must be increased to ensure sufficient process margin, leading to increased fabrication cost and wafer warpage. Therefore, the development of a highly selective silicon etchant with excellent etch-stop capability on SiGe is critically required for advanced BSPDN integration.
In this work, we propose a novel wet silicon etchant that exhibits an exceptionally high Si/Si0.75Ge0.25 selectivity ratio of up to 760, even under single-wafer spin wet etching conditions. The etchant formulation was developed and evaluated using silicon and Si1-xGex wafers with different germanium contents. Etching behavior and selectivity were quantitatively assessed under optimized process conditions. As a baseline, simple alkaline solutions such as ammonium hydroxide (NH4OH) and tetramethylammonium hydroxide (TMAH) were first examined. Under spin wet etching conditions, these conventional alkaline etchants exhibited a maximum Si/SiGe selectivity ratio of approximately 160. In addition, scanning electron microscopy (SEM) revealed the formation of numerous micro-pyramidal structures on silicon surfaces etched with NH₄OH, indicating significant surface roughening.
By contrast, the proposed etchant formulation achieved both a high Si-ER and a dramatically enhanced Si/Si0.75Ge0.25 selectivity ratio of up to 760. SEM analysis further confirmed that the formation of micro-pyramidal surface features was effectively suppressed, resulting in a significantly smoother silicon surface after etching. The combination of ultra-high selectivity and improved surface morphology enables more precise backside silicon removal and allows for a substantial reduction in SiGe ESL thickness. This, in turn, is expected to mitigate wafer warpage and reduce fabrication cost in BSPDN processes. These results demonstrate that the developed etchant provides a viable and scalable solution for next-generation backside power delivery integration.
BIOGRAPHY
Tomoki Nara is a research scientist at Mitsubishi Chemical Corporation, where he is engaged in the development of advanced semiconductor process chemicals. His research focuses on selective wet etching and surface treatment technologies in Si- and SiGe-based device manufacturing, with a particular interest in process integration for next-generation logic devices.
He has contributed to the optimization of single wafer spin-etch processes and developed highly selective etchants suitable for advanced device architectures such as CFET and backside power delivery network. He holds a Master of Science degree from Osaka University. Through close collaboration between research and manufacturing, he aims to bridge the gap between chemical theory and actual semiconductor manufacturing processes and contribute to the development of scalable and reliable device technologies.