Crystallographic Orientation-Dependent on Native Oxide Evolution for Advanced CMOS Surface Control
There is a great deal of engineering interest in Si(110) wafer as substrate by its current drivability advantage. However, the surface sensitivity on native oxide formation from orientation structure is challenging for fabrication compared to conventional Si(100). In this work, X-ray photoemission spectroscopy (XPS) is used to classify the localization of the intermediate suboxide species of the SiOx transition layer after final cleaning. The effect of different storage times will be investigated on oxide formation. The analysis reveals a strong crystallographic dependence in the formation of intermediate oxidation states during native oxide growth on Si(100) and Si(110) surfaces, in which the native oxide growth for both wafers is obviously a function of storage time. Notably, the Si⁴⁺ state is more pronounced on Si(110) with a higher percent ratio of peak intensity detectable as early as only 1 day after cleaning. This indicates that native oxide forms more readily on Si(110) compared to conventional Si(100). Moreover, the measured thickness from ellipsometry shows the equivalent trend in the native oxide thickness increase with storage time for both wafers. These observations support the greater environmental sensitivity of Si(110) compared to conventional Si(100) due to the crystallographic orientation effect. The higher densities of dangling bonds and more anisotropic atomic rearrangement on the surface of Si(110), which is rapidly promoting the oxidation states. These oxide findings are highly valuable for surface control of Si(110) wafers, especially in the effort to achieve extremely clean, smooth, and oxide-free surfaces for the next-generation semiconductor device fabrication.
BIOGRAPHY
Nawaphorn Kuhakongkiat was born in Bangkok, Thailand in 1988. She received doctoral degree in material science from Japan Advanced Institute of Science and Technology in 2016. After graduation, she worked for a postdoctoral at Kyoto Institute of Technology for half year then started to join in semiconductor business as a senior engineer in the process development and integration department at Seagate Technology, Thailand. Along 5 years there, she was a lead-team for surface analysis using several techniques especially time-of-flight secondary ion mass spectroscopy (ToF-SIMS) in many projects. She got the company award recognition from the achievement on corrosion factory improvement for the new head (writer and reader) material and design of heat-assisted magnetic recording (HAMR). Moreover, she also established an idea of alternative new surfactant for process and cost improvement which passed first stage factory qualification.
Once moving back to Japan, she is currently a researcher at Research Institute for Semiconductor Engineering (RISE) of Hiroshima University. Her research area mainly focuses on silicon wafer surface improvement especially on (110) orientation for MOS devices. She does work collaboratively with several universities and companies such as SUMCO under Japan`s semiconductor research association and partnership of Leading-edge Semiconductor Technology or LSTC.