Wafer-level Validation of Si Trimming Process by Wet Etching in 3D DRAM Applications
ABTRACT
Three-dimensional DRAM (3D DRAM) architectures require highly uniform isotropic silicon etching within stacked Si/SiGe channel structures. In our previous work, we demonstrated an alkaline etchant capable of suppressing Si(111) facet formation while maintaining a high etch rate for Si(100), using coupon-scale beaker tests. In this study, we extend the evaluation to full 300 mm wafer processing using manufacturing class equipment to verify scalability, uniformity, and robustness under production relevant conditions.
Experiments were conducted on blanket and structured Si wafers using a batch-type tool operated at atmospheric pressure. Prior to the main etching step, wafers were pre-treated by dipping in 0.5% hydrofluoric acid for 2 minutes to remove the native oxide layer. Subsequently, etching was carried out for 2 to 10 minutes. Two process modes were evaluated: static and dynamic conditions, using equipment employed in actual production environments. Within wafer non uniformity (WIWNU) was assessed by measuring Si thickness at seven points along the wafer diameter. For both Si(100) and Si(110) epitaxial wafers, the difference between maximum and minimum etch rates remained as low as 0.2 nm/min, confirming excellent in plane uniformity. The full wafer etch rate for Si(100) (~4 nm/min) was consistent Three dimensional DRAM (3D DRAM) architectures require precise isotropic Si channel thinning within stacked Si/SiGe channel structures. imec has proposed a channel formation approach in which multilayers of Si/SiGe are grown epitaxially to prepare high quality channel stacks. In our previous study, we demonstrated an alkaline etchant capable of suppressing Si(111) facet formation while maintaining a high etch rate for Si(100), and verified its performance in coupon scale beaker tests. This work demonstrates successful scale up to 300 mm wafers using production class equipment, achieving uniform isotropic etching and etch rates comparable to beaker results while maintaining facet suppression.
All experiments were performed on 300 mm wafers using a batch type tool operated at atmospheric pressure. The alkaline formulation was maintained at 60 °C throughout the process. Prior to etching, wafers were dipped in 0.5% hydrofluoric acid for 2 minutes to remove the native oxide layer. Etching was then carried out for 2 to 10 minutes under both static and dynamic conditions, using equipment employed in actual manufacturing environments.
Within wafer non uniformity (WIWNU) was evaluated by measuring silicon thickness at seven points across the wafer diameter. Structured wafer evaluation further confirmed the manufacturability of the process. Cross sectional SEM imaging revealed consistent Si trimming across the wafer center, middle, and edge, with no observable Si(111) facet formation—behavior that contrasts with benchmark TMAH chemistry. The similarity of wafer level and coupon level etching profiles confirms that the additive controlled isotropic etching mechanism is robust against size scaling.
Overall, these results demonstrate that the alkaline formulation enables uniform and reproducible isotropic Si etching at the wafer scale. Its facet suppression capability, high uniformity, and compatibility with 300 mm production tools make it a promising solution for high volume 3D DRAM manufacturing, where precise Si trimming is essential.
BIOGRAPHY
Naoko Kuwabara received her M.S. degree in Chemical Engineering from Tokyo University of Agriculture and Technology in 2014 and subsequently joined Mitsubishi Chemical Corporation. After contributing to a variety of technology development projects within the company, she has focused in recent years on wet‑chemical processes for semiconductor applications. Her current research centers on alkaline chemistries for precise silicon trimming in 3D DRAM structures, as well as selective Si/SiGe etching for backside power delivery network (BSPDN) integration. She works closely with industrial and academic partners to translate chemical concepts into robust, manufacturable processes on 300‑mm wafer platforms, supporting the advancement of next‑generation device architectures.