Reducing CFET wet clean process defectivity with advanced liquid filtration solutions
ABSTRACT
Controlling contamination in the advanced semiconductor manufacturing process continues to grow in complexity, requiring multiple approaches in parallel to achieve desired levels of yield and reliability. This is especially true for CFET (Complementary Field- Effect Transistor) integration, where nFET and pFET transistors are vertically stacked within a single structure. Unlike traditional planar or FinFET device configurations, CFET introduces multiple critical interfaces, making stricter contamination control a fundamental requirement for achieving the promised device characteristics.
To evaluate the role of next-generation filtration in achieving lower defectivity, we selected a single-wafer clean tool used for critical front-end cleaning steps in CFET integration. We identified specific chemical applications on the tool that used older filtration products (>5nm) and upgraded them to newer generation (2nm and below) filters.
The impact of advanced filtration was measured with standard bare wafer defect analysis inspecting particles greater than 19 nm. Additionally, in-process statistical process control (SPC) measurements, collected before and after the filter upgrade, showed the positive effect on process performance and stability.
This collaboration highlights the value of optimizing liquid filtration solutions to enable low defectivity in process chemicals for next-generation CFET architectures that are more sensitive to small defects.
BIOGRAPHY
Kusum Maharjan is a Lead Engineer in Solutions Engineering at Entegris, supporting advanced semiconductor R&D programs at IMEC, Belgium. She specializes in semiconductor process technology, contamination control, filtration, and materials compatibility, working closely with research institutes and industry partners to develop and qualify next‑generation process solutions.